[qemu.git] / target / m68k / cpu.h

/*
 * m68k virtual CPU header
 *
 *  Copyright (c) 2005-2007 CodeSourcery
 *  Written by Paul Brook
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef M68K_CPU_H
#define M68K_CPU_H

#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "cpu-qom.h"

#define OS_BYTE     0
#define OS_WORD     1
#define OS_LONG     2
#define OS_SINGLE   3
#define OS_DOUBLE   4
#define OS_EXTENDED 5
#define OS_PACKED   6
#define OS_UNSIZED  7

#define MAX_QREGS 32

#define EXCP_ACCESS         2   /* Access (MMU) error.  */
#define EXCP_ADDRESS        3   /* Address error.  */
#define EXCP_ILLEGAL        4   /* Illegal instruction.  */
#define EXCP_DIV0           5   /* Divide by zero */
#define EXCP_CHK            6   /* CHK, CHK2 Instructions */
#define EXCP_TRAPCC         7   /* FTRAPcc, TRAPcc, TRAPV Instructions */
#define EXCP_PRIVILEGE      8   /* Privilege violation.  */
#define EXCP_TRACE          9
#define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
#define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
#define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
#define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
#define EXCP_FORMAT         14  /* RTE format error.  */
#define EXCP_UNINITIALIZED  15
#define EXCP_SPURIOUS       24  /* Spurious interrupt */
#define EXCP_INT_LEVEL_1    25  /* Level 1 Interrupt autovector */
#define EXCP_INT_LEVEL_7    31  /* Level 7 Interrupt autovector */
#define EXCP_TRAP0          32   /* User trap #0.  */
#define EXCP_TRAP15         47   /* User trap #15.  */
#define EXCP_FP_BSUN        48 /* Branch Set on Unordered */
#define EXCP_FP_INEX        49 /* Inexact result */
#define EXCP_FP_DZ          50 /* Divide by Zero */
#define EXCP_FP_UNFL        51 /* Underflow */
#define EXCP_FP_OPERR       52 /* Operand Error */
#define EXCP_FP_OVFL        53 /* Overflow */
#define EXCP_FP_SNAN        54 /* Signaling Not-A-Number */
#define EXCP_FP_UNIMP       55 /* Unimplemented Data type */
#define EXCP_MMU_CONF       56  /* MMU Configuration Error */
#define EXCP_MMU_ILLEGAL    57  /* MMU Illegal Operation Error */
#define EXCP_MMU_ACCESS     58  /* MMU Access Level Violation Error */

#define EXCP_RTE            0x100
#define EXCP_HALT_INSN      0x101

#define M68K_DTTR0   0
#define M68K_DTTR1   1
#define M68K_ITTR0   2
#define M68K_ITTR1   3

#define M68K_MAX_TTR 2
#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]

#define TARGET_INSN_START_EXTRA_WORDS 1

typedef CPU_LDoubleU FPReg;

typedef struct CPUM68KState {
    uint32_t dregs[8];
    uint32_t aregs[8];
    uint32_t pc;
    uint32_t sr;

    /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
    int current_sp;
    uint32_t sp[3];

    /* Condition flags.  */
    uint32_t cc_op;
    uint32_t cc_x; /* always 0/1 */
    uint32_t cc_n; /* in bit 31 (i.e. negative) */
    uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
    uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
    uint32_t cc_z; /* == 0 or unused */

    FPReg fregs[8];
    FPReg fp_result;
    uint32_t fpcr;
    uint32_t fpsr;
    float_status fp_status;

    uint64_t mactmp;
    /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
       two 8-bit parts.  We store a single 64-bit value and
       rearrange/extend this when changing modes.  */
    uint64_t macc[4];
    uint32_t macsr;
    uint32_t mac_mask;

    /* MMU status.  */
    struct {
        uint32_t ar;
        uint32_t ssw;
        /* 68040 */
        uint16_t tcr;
        uint32_t urp;
        uint32_t srp;
        bool fault;
        uint32_t ttr[4];
        uint32_t mmusr;
    } mmu;

    /* Control registers.  */
    uint32_t vbr;
    uint32_t mbar;
    uint32_t rambar0;
    uint32_t cacr;
    uint32_t sfc;
    uint32_t dfc;

    int pending_vector;
    int pending_level;

    uint32_t qregs[MAX_QREGS];

    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

    CPU_COMMON

    /* Fields from here on are preserved across CPU reset. */
    uint32_t features;
} CPUM68KState;

/**
 * M68kCPU:
 * @env: #CPUM68KState
 *
 * A Motorola 68k CPU.
 */
struct M68kCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUM68KState env;
};

static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
{
    return container_of(env, M68kCPU, env);
}

#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))

#define ENV_OFFSET offsetof(M68kCPU, env)

void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

void m68k_tcg_init(void);
void m68k_cpu_init_gdb(M68kCPU *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_m68k_signal_handler(int host_signum, void *pinfo,
                           void *puc);
uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);


/* Instead of computing the condition codes after each m68k instruction,
 * QEMU just stores one operand (called CC_SRC), the result
 * (called CC_DEST) and the type of operation (called CC_OP). When the
 * condition codes are needed, the condition codes can be calculated
 * using this information. Condition codes are not generated if they
 * are only needed for conditional branches.
 */
typedef enum {
    /* Translator only -- use env->cc_op.  */
    CC_OP_DYNAMIC,

    /* Each flag bit computed into cc_[xcnvz].  */
    CC_OP_FLAGS,

    /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v.  */
    CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
    CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,

    /* X in cc_x, {N,Z,C,V} via cc_n/cc_v.  */
    CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,

    /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n.  */
    CC_OP_LOGIC,

    CC_OP_NB
} CCOp;

#define CCF_C 0x01
#define CCF_V 0x02
#define CCF_Z 0x04
#define CCF_N 0x08
#define CCF_X 0x10

#define SR_I_SHIFT 8
#define SR_I  0x0700
#define SR_M  0x1000
#define SR_S  0x2000
#define SR_T_SHIFT 14
#define SR_T  0xc000

#define M68K_SSP    0
#define M68K_USP    1
#define M68K_ISP    2

/* bits for 68040 special status word */
#define M68K_CP_040  0x8000
#define M68K_CU_040  0x4000
#define M68K_CT_040  0x2000
#define M68K_CM_040  0x1000
#define M68K_MA_040  0x0800
#define M68K_ATC_040 0x0400
#define M68K_LK_040  0x0200
#define M68K_RW_040  0x0100
#define M68K_SIZ_040 0x0060
#define M68K_TT_040  0x0018
#define M68K_TM_040  0x0007

#define M68K_TM_040_DATA  0x0001
#define M68K_TM_040_CODE  0x0002
#define M68K_TM_040_SUPER 0x0004

/* bits for 68040 write back status word */
#define M68K_WBV_040   0x80
#define M68K_WBSIZ_040 0x60
#define M68K_WBBYT_040 0x20
#define M68K_WBWRD_040 0x40
#define M68K_WBLNG_040 0x00
#define M68K_WBTT_040  0x18
#define M68K_WBTM_040  0x07

/* bus access size codes */
#define M68K_BA_SIZE_MASK    0x60
#define M68K_BA_SIZE_BYTE    0x20
#define M68K_BA_SIZE_WORD    0x40
#define M68K_BA_SIZE_LONG    0x00
#define M68K_BA_SIZE_LINE    0x60

/* bus access transfer type codes */
#define M68K_BA_TT_MOVE16    0x08

/* bits for 68040 MMU status register (mmusr) */
#define M68K_MMU_B_040   0x0800
#define M68K_MMU_G_040   0x0400
#define M68K_MMU_U1_040  0x0200
#define M68K_MMU_U0_040  0x0100
#define M68K_MMU_S_040   0x0080
#define M68K_MMU_CM_040  0x0060
#define M68K_MMU_M_040   0x0010
#define M68K_MMU_WP_040  0x0004
#define M68K_MMU_T_040   0x0002
#define M68K_MMU_R_040   0x0001

#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
                              M68K_MMU_U0_040 | M68K_MMU_S_040 | \
                              M68K_MMU_CM_040 | M68K_MMU_M_040 | \
                              M68K_MMU_WP_040)

/* bits for 68040 MMU Translation Control Register */
#define M68K_TCR_ENABLED 0x8000
#define M68K_TCR_PAGE_8K 0x4000

/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
#define M68K_DESC_WRITEPROT 0x00000004
#define M68K_DESC_USED      0x00000008
#define M68K_DESC_MODIFIED  0x00000010
#define M68K_DESC_CACHEMODE 0x00000060
#define M68K_DESC_CM_WRTHRU 0x00000000
#define M68K_DESC_CM_COPYBK 0x00000020
#define M68K_DESC_CM_SERIAL 0x00000040
#define M68K_DESC_CM_NCACHE 0x00000060
#define M68K_DESC_SUPERONLY 0x00000080
#define M68K_DESC_USERATTR  0x00000300
#define M68K_DESC_USERATTR_SHIFT     8
#define M68K_DESC_GLOBAL    0x00000400
#define M68K_DESC_URESERVED 0x00000800

#define M68K_ROOT_POINTER_ENTRIES   128
#define M68K_4K_PAGE_MASK           (~0xff)
#define M68K_POINTER_BASE(entry)    (entry & ~0x1ff)
#define M68K_ROOT_INDEX(addr)       ((address >> 23) & 0x1fc)
#define M68K_POINTER_INDEX(addr)    ((address >> 16) & 0x1fc)
#define M68K_4K_PAGE_BASE(entry)    (next & M68K_4K_PAGE_MASK)
#define M68K_4K_PAGE_INDEX(addr)    ((address >> 10) & 0xfc)
#define M68K_8K_PAGE_MASK           (~0x7f)
#define M68K_8K_PAGE_BASE(entry)    (next & M68K_8K_PAGE_MASK)
#define M68K_8K_PAGE_INDEX(addr)    ((address >> 11) & 0x7c)
#define M68K_UDT_VALID(entry)       (entry & 2)
#define M68K_PDT_VALID(entry)       (entry & 3)
#define M68K_PDT_INDIRECT(entry)    ((entry & 3) == 2)
#define M68K_INDIRECT_POINTER(addr) (addr & ~3)
#define M68K_TTS_POINTER_SHIFT      18
#define M68K_TTS_ROOT_SHIFT         25

/* bits for 68040 MMU Transparent Translation Registers */
#define M68K_TTR_ADDR_BASE 0xff000000
#define M68K_TTR_ADDR_MASK 0x00ff0000
#define M68K_TTR_ADDR_MASK_SHIFT    8
#define M68K_TTR_ENABLED   0x00008000
#define M68K_TTR_SFIELD    0x00006000
#define M68K_TTR_SFIELD_USER   0x0000
#define M68K_TTR_SFIELD_SUPER  0x2000

/* m68k Control Registers */

/* ColdFire */
/* Memory Management Control Registers */
#define M68K_CR_ASID     0x003
#define M68K_CR_ACR0     0x004
#define M68K_CR_ACR1     0x005
#define M68K_CR_ACR2     0x006
#define M68K_CR_ACR3     0x007
#define M68K_CR_MMUBAR   0x008

/* Processor Miscellaneous Registers */
#define M68K_CR_PC       0x80F

/* Local Memory and Module Control Registers */
#define M68K_CR_ROMBAR0  0xC00
#define M68K_CR_ROMBAR1  0xC01
#define M68K_CR_RAMBAR0  0xC04
#define M68K_CR_RAMBAR1  0xC05
#define M68K_CR_MPCR     0xC0C
#define M68K_CR_EDRAMBAR 0xC0D
#define M68K_CR_SECMBAR  0xC0E
#define M68K_CR_MBAR     0xC0F

/* Local Memory Address Permutation Control Registers */
#define M68K_CR_PCR1U0   0xD02
#define M68K_CR_PCR1L0   0xD03
#define M68K_CR_PCR2U0   0xD04
#define M68K_CR_PCR2L0   0xD05
#define M68K_CR_PCR3U0   0xD06
#define M68K_CR_PCR3L0   0xD07
#define M68K_CR_PCR1U1   0xD0A
#define M68K_CR_PCR1L1   0xD0B
#define M68K_CR_PCR2U1   0xD0C
#define M68K_CR_PCR2L1   0xD0D
#define M68K_CR_PCR3U1   0xD0E
#define M68K_CR_PCR3L1   0xD0F

/* MC680x0 */
/* MC680[1234]0/CPU32 */
#define M68K_CR_SFC      0x000
#define M68K_CR_DFC      0x001
#define M68K_CR_USP      0x800
#define M68K_CR_VBR      0x801 /* + Coldfire */

/* MC680[234]0 */
#define M68K_CR_CACR     0x002 /* + Coldfire */
#define M68K_CR_CAAR     0x802 /* MC68020 and MC68030 only */
#define M68K_CR_MSP      0x803
#define M68K_CR_ISP      0x804

/* MC68040/MC68LC040 */
#define M68K_CR_TC       0x003
#define M68K_CR_ITT0     0x004
#define M68K_CR_ITT1     0x005
#define M68K_CR_DTT0     0x006
#define M68K_CR_DTT1     0x007
#define M68K_CR_MMUSR    0x805
#define M68K_CR_URP      0x806
#define M68K_CR_SRP      0x807

/* MC68EC040 */
#define M68K_CR_IACR0    0x004
#define M68K_CR_IACR1    0x005
#define M68K_CR_DACR0    0x006
#define M68K_CR_DACR1    0x007

#define M68K_FPIAR_SHIFT  0
#define M68K_FPIAR        (1 << M68K_FPIAR_SHIFT)
#define M68K_FPSR_SHIFT   1
#define M68K_FPSR         (1 << M68K_FPSR_SHIFT)
#define M68K_FPCR_SHIFT   2
#define M68K_FPCR         (1 << M68K_FPCR_SHIFT)

/* Floating-Point Status Register */

/* Condition Code */
#define FPSR_CC_MASK  0x0f000000
#define FPSR_CC_A     0x01000000 /* Not-A-Number */
#define FPSR_CC_I     0x02000000 /* Infinity */
#define FPSR_CC_Z     0x04000000 /* Zero */
#define FPSR_CC_N     0x08000000 /* Negative */

/* Quotient */

#define FPSR_QT_MASK  0x00ff0000
#define FPSR_QT_SHIFT 16

/* Floating-Point Control Register */
/* Rounding mode */
#define FPCR_RND_MASK   0x0030
#define FPCR_RND_N      0x0000
#define FPCR_RND_Z      0x0010
#define FPCR_RND_M      0x0020
#define FPCR_RND_P      0x0030

/* Rounding precision */
#define FPCR_PREC_MASK  0x00c0
#define FPCR_PREC_X     0x0000
#define FPCR_PREC_S     0x0040
#define FPCR_PREC_D     0x0080
#define FPCR_PREC_U     0x00c0

#define FPCR_EXCP_MASK 0xff00

/* CACR fields are implementation defined, but some bits are common.  */
#define M68K_CACR_EUSP  0x10

#define MACSR_PAV0  0x100
#define MACSR_OMC   0x080
#define MACSR_SU    0x040
#define MACSR_FI    0x020
#define MACSR_RT    0x010
#define MACSR_N     0x008
#define MACSR_Z     0x004
#define MACSR_V     0x002
#define MACSR_EV    0x001

void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
void m68k_switch_sp(CPUM68KState *env);

void do_m68k_semihosting(CPUM68KState *env, int nr);

/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
   Each feature covers the subset of instructions common to the
   ISA revisions mentioned.  */

enum m68k_features {
    M68K_FEATURE_M68000,
    M68K_FEATURE_CF_ISA_A,
    M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
    M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
    M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
    M68K_FEATURE_CF_FPU,
    M68K_FEATURE_CF_MAC,
    M68K_FEATURE_CF_EMAC,
    M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
    M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
    M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
    M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
    M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
    M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
    M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
    M68K_FEATURE_BCCL, /* Long conditional branches.  */
    M68K_FEATURE_BITFIELD, /* Bit field insns.  */
    M68K_FEATURE_FPU,
    M68K_FEATURE_CAS,
    M68K_FEATURE_BKPT,
    M68K_FEATURE_RTD,
    M68K_FEATURE_CHK2,
    M68K_FEATURE_M68040, /* instructions specific to MC68040 */
    M68K_FEATURE_MOVEP,
};

static inline int m68k_feature(CPUM68KState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void m68k_cpu_list(void);

void register_m68k_insns (CPUM68KState *env);

enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_SUPER = 0x01,
    /* 1 bit to indicate direction */
    ACCESS_STORE = 0x02,
    /* 1 bit to indicate debug access */
    ACCESS_DEBUG = 0x04,
    /* PTEST instruction */
    ACCESS_PTEST = 0x08,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_DATA  = 0x20, /* Data load/store access        */
};

#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_M68K_CPU

#define cpu_signal_handler cpu_m68k_signal_handler
#define cpu_list m68k_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
{
    return (env->sr & SR_S) == 0 ? 1 : 0;
}

bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);
void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                 unsigned size, MMUAccessType access_type,
                                 int mmu_idx, MemTxAttrs attrs,
                                 MemTxResult response, uintptr_t retaddr);

typedef CPUM68KState CPUArchState;
typedef M68kCPU ArchCPU;

#include "exec/cpu-all.h"

/* TB flags */
#define TB_FLAGS_MACSR          0x0f
#define TB_FLAGS_MSR_S_BIT      13
#define TB_FLAGS_MSR_S          (1 << TB_FLAGS_MSR_S_BIT)
#define TB_FLAGS_SFC_S_BIT      14
#define TB_FLAGS_SFC_S          (1 << TB_FLAGS_SFC_S_BIT)
#define TB_FLAGS_DFC_S_BIT      15
#define TB_FLAGS_DFC_S          (1 << TB_FLAGS_DFC_S_BIT)

static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
    if (env->sr & SR_S) {
        *flags |= TB_FLAGS_MSR_S;
        *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
        *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
    }
}

void dump_mmu(CPUM68KState *env);

#endif
Commit	Line	Data
e6e5906b PB	1	/*
e6e5906b PB	2	* m68k virtual CPU header
5fafdf24	3	*
0633879f	4	* Copyright (c) 2005-2007 CodeSourcery
e6e5906b PB	5	* Written by Paul Brook
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
d749fb85	10	* version 2.1 of the License, or (at your option) any later version.
e6e5906b PB	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
d749fb85	15	* Lesser General Public License for more details.
e6e5906b PB	16	*
e6e5906b PB	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
e6e5906b	19	*/
07f5a258 MA	20
	21	#ifndef M68K_CPU_H
	22	#define M68K_CPU_H
e6e5906b	23
9a78eead	24	#include "qemu-common.h"
022c62cb	25	#include "exec/cpu-defs.h"
a836b8fa	26	#include "cpu-qom.h"
e6e5906b	27
7ef25cdd LV	28	#define OS_BYTE 0
	29	#define OS_WORD 1
	30	#define OS_LONG 2
	31	#define OS_SINGLE 3
	32	#define OS_DOUBLE 4
	33	#define OS_EXTENDED 5
	34	#define OS_PACKED 6
f2224f2c	35	#define OS_UNSIZED 7
7ef25cdd	36
e6e5906b PB	37	#define MAX_QREGS 32
e6e5906b PB	38
e6e5906b PB	39	#define EXCP_ACCESS 2 /* Access (MMU) error. */
	40	#define EXCP_ADDRESS 3 /* Address error. */
	41	#define EXCP_ILLEGAL 4 /* Illegal instruction. */
	42	#define EXCP_DIV0 5 /* Divide by zero */
5beb144e LV	43	#define EXCP_CHK 6 /* CHK, CHK2 Instructions */
5beb144e LV	44	#define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */
e6e5906b PB	45	#define EXCP_PRIVILEGE 8 /* Privilege violation. */
	46	#define EXCP_TRACE 9
	47	#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
	48	#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
	49	#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
	50	#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
	51	#define EXCP_FORMAT 14 /* RTE format error. */
	52	#define EXCP_UNINITIALIZED 15
5beb144e LV	53	#define EXCP_SPURIOUS 24 /* Spurious interrupt */
	54	#define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */
	55	#define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */
e6e5906b PB	56	#define EXCP_TRAP0 32 /* User trap #0. */
e6e5906b PB	57	#define EXCP_TRAP15 47 /* User trap #15. */
f83311e4 LV	58	#define EXCP_FP_BSUN 48 /* Branch Set on Unordered */
	59	#define EXCP_FP_INEX 49 /* Inexact result */
	60	#define EXCP_FP_DZ 50 /* Divide by Zero */
	61	#define EXCP_FP_UNFL 51 /* Underflow */
	62	#define EXCP_FP_OPERR 52 /* Operand Error */
	63	#define EXCP_FP_OVFL 53 /* Overflow */
	64	#define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */
	65	#define EXCP_FP_UNIMP 55 /* Unimplemented Data type */
5beb144e LV	66	#define EXCP_MMU_CONF 56 /* MMU Configuration Error */
	67	#define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */
	68	#define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */
e6e5906b	69
0633879f	70	#define EXCP_RTE 0x100
a87295e8	71	#define EXCP_HALT_INSN 0x101
0633879f	72
c05c73b0 LV	73	#define M68K_DTTR0 0
	74	#define M68K_DTTR1 1
	75	#define M68K_ITTR0 2
	76	#define M68K_ITTR1 3
	77
	78	#define M68K_MAX_TTR 2
	79	#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
	80
20a8856e	81	#define TARGET_INSN_START_EXTRA_WORDS 1
6ebbf390	82
f83311e4 LV	83	typedef CPU_LDoubleU FPReg;
f83311e4 LV	84
e6e5906b PB	85	typedef struct CPUM68KState {
	86	uint32_t dregs[8];
	87	uint32_t aregs[8];
	88	uint32_t pc;
	89	uint32_t sr;
	90
20dcee94 PB	91	/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
20dcee94 PB	92	int current_sp;
6e22b28e	93	uint32_t sp[3];
20dcee94	94
e6e5906b PB	95	/* Condition flags. */
e6e5906b PB	96	uint32_t cc_op;
620c6cf6 RH	97	uint32_t cc_x; /* always 0/1 */
	98	uint32_t cc_n; /* in bit 31 (i.e. negative) */
	99	uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
	100	uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
	101	uint32_t cc_z; /* == 0 or unused */
e6e5906b	102
f83311e4 LV	103	FPReg fregs[8];
f83311e4 LV	104	FPReg fp_result;
e6e5906b PB	105	uint32_t fpcr;
	106	uint32_t fpsr;
	107	float_status fp_status;
	108
acf930aa PB	109	uint64_t mactmp;
	110	/* EMAC Hardware deals with 48-bit values composed of one 32-bit and
	111	two 8-bit parts. We store a single 64-bit value and
	112	rearrange/extend this when changing modes. */
	113	uint64_t macc[4];
	114	uint32_t macsr;
	115	uint32_t mac_mask;
	116
e6e5906b PB	117	/* MMU status. */
	118	struct {
	119	uint32_t ar;
88b2fef6 LV	120	uint32_t ssw;
	121	/* 68040 */
	122	uint16_t tcr;
	123	uint32_t urp;
	124	uint32_t srp;
	125	bool fault;
c05c73b0	126	uint32_t ttr[4];
e55886c3	127	uint32_t mmusr;
e6e5906b	128	} mmu;
0633879f PB	129
	130	/* Control registers. */
	131	uint32_t vbr;
	132	uint32_t mbar;
	133	uint32_t rambar0;
20dcee94	134	uint32_t cacr;
5fa9f1f2 LV	135	uint32_t sfc;
5fa9f1f2 LV	136	uint32_t dfc;
0633879f	137
0633879f PB	138	int pending_vector;
0633879f PB	139	int pending_level;
e6e5906b PB	140
	141	uint32_t qregs[MAX_QREGS];
	142
1f5c00cf AB	143	/* Fields up to this point are cleared by a CPU reset */
	144	struct {} end_reset_fields;
	145
e6e5906b	146	CPU_COMMON
aaed909a	147
f0c3c505	148	/* Fields from here on are preserved across CPU reset. */
aaed909a	149	uint32_t features;
e6e5906b PB	150	} CPUM68KState;
e6e5906b PB	151
a836b8fa PB	152	/**
	153	* M68kCPU:
	154	* @env: #CPUM68KState
	155	*
	156	* A Motorola 68k CPU.
	157	*/
	158	struct M68kCPU {
	159	/< private >/
	160	CPUState parent_obj;
	161	/< public >/
	162
	163	CPUM68KState env;
	164	};
	165
	166	static inline M68kCPU m68k_env_get_cpu(CPUM68KState env)
	167	{
	168	return container_of(env, M68kCPU, env);
	169	}
	170
	171	#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
	172
	173	#define ENV_OFFSET offsetof(M68kCPU, env)
	174
	175	void m68k_cpu_do_interrupt(CPUState *cpu);
	176	bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
90c84c56	177	void m68k_cpu_dump_state(CPUState cpu, FILE f, int flags);
a836b8fa PB	178	hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	179	int m68k_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	180	int m68k_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	181
e1f3808e	182	void m68k_tcg_init(void);
6d1bbc62	183	void m68k_cpu_init_gdb(M68kCPU *cpu);
e6e5906b PB	184	/* you can call this signal handler from your SIGBUS and SIGSEGV
	185	signal handlers to inform the virtual CPU of exceptions. non zero
	186	is returned if the signal was handled by the virtual CPU. */
5fafdf24	187	int cpu_m68k_signal_handler(int host_signum, void *pinfo,
e6e5906b	188	void *puc);
99c51448 RH	189	uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
99c51448 RH	190	void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
d2f8fb8e	191	void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
ba624944	192	void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
e6e5906b	193
c3ce5a23 PB	194
	195	/* Instead of computing the condition codes after each m68k instruction,
	196	* QEMU just stores one operand (called CC_SRC), the result
	197	* (called CC_DEST) and the type of operation (called CC_OP). When the
	198	* condition codes are needed, the condition codes can be calculated
	199	* using this information. Condition codes are not generated if they
	200	* are only needed for conditional branches.
	201	*/
9fdb533f	202	typedef enum {
620c6cf6	203	/* Translator only -- use env->cc_op. */
7deddf96	204	CC_OP_DYNAMIC,
620c6cf6 RH	205
	206	/* Each flag bit computed into cc_[xcnvz]. */
	207	CC_OP_FLAGS,
	208
	209	/* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */
db3d7945 LV	210	CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
db3d7945 LV	211	CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
620c6cf6 RH	212
620c6cf6 RH	213	/* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */
db3d7945	214	CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
620c6cf6 RH	215
	216	/* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
	217	CC_OP_LOGIC,
	218
	219	CC_OP_NB
9fdb533f	220	} CCOp;
e6e5906b PB	221
	222	#define CCF_C 0x01
	223	#define CCF_V 0x02
	224	#define CCF_Z 0x04
	225	#define CCF_N 0x08
0633879f PB	226	#define CCF_X 0x10
	227
	228	#define SR_I_SHIFT 8
	229	#define SR_I 0x0700
	230	#define SR_M 0x1000
	231	#define SR_S 0x2000
cc523026 LV	232	#define SR_T_SHIFT 14
cc523026 LV	233	#define SR_T 0xc000
e6e5906b	234
20dcee94 PB	235	#define M68K_SSP 0
20dcee94 PB	236	#define M68K_USP 1
6e22b28e LV	237	#define M68K_ISP 2
6e22b28e LV	238
88b2fef6 LV	239	/* bits for 68040 special status word */
	240	#define M68K_CP_040 0x8000
	241	#define M68K_CU_040 0x4000
	242	#define M68K_CT_040 0x2000
	243	#define M68K_CM_040 0x1000
	244	#define M68K_MA_040 0x0800
	245	#define M68K_ATC_040 0x0400
	246	#define M68K_LK_040 0x0200
	247	#define M68K_RW_040 0x0100
	248	#define M68K_SIZ_040 0x0060
	249	#define M68K_TT_040 0x0018
	250	#define M68K_TM_040 0x0007
	251
	252	#define M68K_TM_040_DATA 0x0001
	253	#define M68K_TM_040_CODE 0x0002
	254	#define M68K_TM_040_SUPER 0x0004
	255
	256	/* bits for 68040 write back status word */
	257	#define M68K_WBV_040 0x80
	258	#define M68K_WBSIZ_040 0x60
	259	#define M68K_WBBYT_040 0x20
	260	#define M68K_WBWRD_040 0x40
	261	#define M68K_WBLNG_040 0x00
	262	#define M68K_WBTT_040 0x18
	263	#define M68K_WBTM_040 0x07
	264
	265	/* bus access size codes */
	266	#define M68K_BA_SIZE_MASK 0x60
	267	#define M68K_BA_SIZE_BYTE 0x20
	268	#define M68K_BA_SIZE_WORD 0x40
	269	#define M68K_BA_SIZE_LONG 0x00
	270	#define M68K_BA_SIZE_LINE 0x60
	271
	272	/* bus access transfer type codes */
	273	#define M68K_BA_TT_MOVE16 0x08
	274
	275	/* bits for 68040 MMU status register (mmusr) */
	276	#define M68K_MMU_B_040 0x0800
	277	#define M68K_MMU_G_040 0x0400
	278	#define M68K_MMU_U1_040 0x0200
	279	#define M68K_MMU_U0_040 0x0100
	280	#define M68K_MMU_S_040 0x0080
	281	#define M68K_MMU_CM_040 0x0060
	282	#define M68K_MMU_M_040 0x0010
	283	#define M68K_MMU_WP_040 0x0004
	284	#define M68K_MMU_T_040 0x0002
	285	#define M68K_MMU_R_040 0x0001
	286
	287	#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 \| M68K_MMU_U1_040 \| \
	288	M68K_MMU_U0_040 \| M68K_MMU_S_040 \| \
	289	M68K_MMU_CM_040 \| M68K_MMU_M_040 \| \
	290	M68K_MMU_WP_040)
	291
	292	/* bits for 68040 MMU Translation Control Register */
	293	#define M68K_TCR_ENABLED 0x8000
	294	#define M68K_TCR_PAGE_8K 0x4000
	295
	296	/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
	297	#define M68K_DESC_WRITEPROT 0x00000004
	298	#define M68K_DESC_USED 0x00000008
	299	#define M68K_DESC_MODIFIED 0x00000010
	300	#define M68K_DESC_CACHEMODE 0x00000060
	301	#define M68K_DESC_CM_WRTHRU 0x00000000
	302	#define M68K_DESC_CM_COPYBK 0x00000020
303	#define M68K_DESC_CM_SERIAL 0x00000040
304	#define M68K_DESC_CM_NCACHE 0x00000060
305	#define M68K_DESC_SUPERONLY 0x00000080
306	#define M68K_DESC_USERATTR 0x00000300
307	#define M68K_DESC_USERATTR_SHIFT 8
308	#define M68K_DESC_GLOBAL 0x00000400
309	#define M68K_DESC_URESERVED 0x00000800
310
2097dca6	311	#define M68K_ROOT_POINTER_ENTRIES 128
88b2fef6 LV	312	#define M68K_4K_PAGE_MASK (~0xff)
	313	#define M68K_POINTER_BASE(entry) (entry & ~0x1ff)
	314	#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc)
	315	#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc)
	316	#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK)
	317	#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc)
	318	#define M68K_8K_PAGE_MASK (~0x7f)
	319	#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK)
	320	#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c)
	321	#define M68K_UDT_VALID(entry) (entry & 2)
	322	#define M68K_PDT_VALID(entry) (entry & 3)
	323	#define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2)
	324	#define M68K_INDIRECT_POINTER(addr) (addr & ~3)
2097dca6 LV	325	#define M68K_TTS_POINTER_SHIFT 18
2097dca6 LV	326	#define M68K_TTS_ROOT_SHIFT 25
88b2fef6	327
c05c73b0 LV	328	/* bits for 68040 MMU Transparent Translation Registers */
	329	#define M68K_TTR_ADDR_BASE 0xff000000
	330	#define M68K_TTR_ADDR_MASK 0x00ff0000
	331	#define M68K_TTR_ADDR_MASK_SHIFT 8
	332	#define M68K_TTR_ENABLED 0x00008000
	333	#define M68K_TTR_SFIELD 0x00006000
	334	#define M68K_TTR_SFIELD_USER 0x0000
	335	#define M68K_TTR_SFIELD_SUPER 0x2000
	336
6e22b28e LV	337	/* m68k Control Registers */
	338
	339	/* ColdFire */
	340	/* Memory Management Control Registers */
	341	#define M68K_CR_ASID 0x003
	342	#define M68K_CR_ACR0 0x004
	343	#define M68K_CR_ACR1 0x005
	344	#define M68K_CR_ACR2 0x006
	345	#define M68K_CR_ACR3 0x007
	346	#define M68K_CR_MMUBAR 0x008
	347
	348	/* Processor Miscellaneous Registers */
	349	#define M68K_CR_PC 0x80F
	350
	351	/* Local Memory and Module Control Registers */
	352	#define M68K_CR_ROMBAR0 0xC00
	353	#define M68K_CR_ROMBAR1 0xC01
	354	#define M68K_CR_RAMBAR0 0xC04
	355	#define M68K_CR_RAMBAR1 0xC05
	356	#define M68K_CR_MPCR 0xC0C
	357	#define M68K_CR_EDRAMBAR 0xC0D
	358	#define M68K_CR_SECMBAR 0xC0E
	359	#define M68K_CR_MBAR 0xC0F
	360
	361	/* Local Memory Address Permutation Control Registers */
	362	#define M68K_CR_PCR1U0 0xD02
	363	#define M68K_CR_PCR1L0 0xD03
	364	#define M68K_CR_PCR2U0 0xD04
	365	#define M68K_CR_PCR2L0 0xD05
	366	#define M68K_CR_PCR3U0 0xD06
	367	#define M68K_CR_PCR3L0 0xD07
	368	#define M68K_CR_PCR1U1 0xD0A
	369	#define M68K_CR_PCR1L1 0xD0B
	370	#define M68K_CR_PCR2U1 0xD0C
	371	#define M68K_CR_PCR2L1 0xD0D
	372	#define M68K_CR_PCR3U1 0xD0E
	373	#define M68K_CR_PCR3L1 0xD0F
	374
	375	/* MC680x0 */
	376	/* MC680[1234]0/CPU32 */
	377	#define M68K_CR_SFC 0x000
	378	#define M68K_CR_DFC 0x001
	379	#define M68K_CR_USP 0x800
	380	#define M68K_CR_VBR 0x801 /* + Coldfire */
	381
	382	/* MC680[234]0 */
	383	#define M68K_CR_CACR 0x002 /* + Coldfire */
	384	#define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */
	385	#define M68K_CR_MSP 0x803
	386	#define M68K_CR_ISP 0x804
	387
	388	/* MC68040/MC68LC040 */
	389	#define M68K_CR_TC 0x003
	390	#define M68K_CR_ITT0 0x004
	391	#define M68K_CR_ITT1 0x005
	392	#define M68K_CR_DTT0 0x006
	393	#define M68K_CR_DTT1 0x007
	394	#define M68K_CR_MMUSR 0x805
	395	#define M68K_CR_URP 0x806
	396	#define M68K_CR_SRP 0x807
	397
	398	/* MC68EC040 */
	399	#define M68K_CR_IACR0 0x004
	400	#define M68K_CR_IACR1 0x005
401	#define M68K_CR_DACR0 0x006
402	#define M68K_CR_DACR1 0x007
20dcee94	403
ba624944 LV	404	#define M68K_FPIAR_SHIFT 0
	405	#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
	406	#define M68K_FPSR_SHIFT 1
	407	#define M68K_FPSR (1 << M68K_FPSR_SHIFT)
	408	#define M68K_FPCR_SHIFT 2
	409	#define M68K_FPCR (1 << M68K_FPCR_SHIFT)
	410
	411	/* Floating-Point Status Register */
	412
	413	/* Condition Code */
	414	#define FPSR_CC_MASK 0x0f000000
	415	#define FPSR_CC_A 0x01000000 /* Not-A-Number */
	416	#define FPSR_CC_I 0x02000000 /* Infinity */
	417	#define FPSR_CC_Z 0x04000000 /* Zero */
	418	#define FPSR_CC_N 0x08000000 /* Negative */
	419
	420	/* Quotient */
	421
	422	#define FPSR_QT_MASK 0x00ff0000
591596b7	423	#define FPSR_QT_SHIFT 16
ba624944 LV	424
	425	/* Floating-Point Control Register */
	426	/* Rounding mode */
	427	#define FPCR_RND_MASK 0x0030
	428	#define FPCR_RND_N 0x0000
	429	#define FPCR_RND_Z 0x0010
	430	#define FPCR_RND_M 0x0020
	431	#define FPCR_RND_P 0x0030
	432
	433	/* Rounding precision */
	434	#define FPCR_PREC_MASK 0x00c0
	435	#define FPCR_PREC_X 0x0000
	436	#define FPCR_PREC_S 0x0040
	437	#define FPCR_PREC_D 0x0080
	438	#define FPCR_PREC_U 0x00c0
	439
	440	#define FPCR_EXCP_MASK 0xff00
	441
20dcee94 PB	442	/* CACR fields are implementation defined, but some bits are common. */
	443	#define M68K_CACR_EUSP 0x10
	444
acf930aa PB	445	#define MACSR_PAV0 0x100
	446	#define MACSR_OMC 0x080
	447	#define MACSR_SU 0x040
	448	#define MACSR_FI 0x020
	449	#define MACSR_RT 0x010
	450	#define MACSR_N 0x008
	451	#define MACSR_Z 0x004
	452	#define MACSR_V 0x002
	453	#define MACSR_EV 0x001
	454
cb3fb38e	455	void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
20dcee94	456	void m68k_switch_sp(CPUM68KState *env);
e6e5906b	457
a87295e8 PB	458	void do_m68k_semihosting(CPUM68KState *env, int nr);
a87295e8 PB	459
d315c888 PB	460	/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
	461	Each feature covers the subset of instructions common to the
	462	ISA revisions mentioned. */
	463
0402f767	464	enum m68k_features {
f076803b	465	M68K_FEATURE_M68000,
0402f767	466	M68K_FEATURE_CF_ISA_A,
d315c888 PB	467	M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
	468	M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
	469	M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
0402f767 PB	470	M68K_FEATURE_CF_FPU,
	471	M68K_FEATURE_CF_MAC,
	472	M68K_FEATURE_CF_EMAC,
d315c888 PB	473	M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
d315c888 PB	474	M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
e6dbd3b3	475	M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
f076803b LV	476	M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
	477	M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
	478	M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
	479	M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
	480	M68K_FEATURE_BCCL, /* Long conditional branches. */
	481	M68K_FEATURE_BITFIELD, /* Bit field insns. */
	482	M68K_FEATURE_FPU,
	483	M68K_FEATURE_CAS,
	484	M68K_FEATURE_BKPT,
18059c9e	485	M68K_FEATURE_RTD,
8bf6cbaf	486	M68K_FEATURE_CHK2,
9d4f0429	487	M68K_FEATURE_M68040, /* instructions specific to MC68040 */
1226e212	488	M68K_FEATURE_MOVEP,
0402f767 PB	489	};
	490
	491	static inline int m68k_feature(CPUM68KState *env, int feature)
	492	{
	493	return (env->features & (1u << feature)) != 0;
	494	}
	495
0442428a	496	void m68k_cpu_list(void);
009a4356	497
0402f767 PB	498	void register_m68k_insns (CPUM68KState *env);
0402f767 PB	499
88b2fef6 LV	500	enum {
	501	/* 1 bit to define user level / supervisor access */
	502	ACCESS_SUPER = 0x01,
	503	/* 1 bit to indicate direction */
	504	ACCESS_STORE = 0x02,
	505	/* 1 bit to indicate debug access */
	506	ACCESS_DEBUG = 0x04,
e55886c3 LV	507	/* PTEST instruction */
e55886c3 LV	508	ACCESS_PTEST = 0x08,
88b2fef6 LV	509	/* Type of instruction that generated the access */
	510	ACCESS_CODE = 0x10, /* Code fetch access */
	511	ACCESS_DATA = 0x20, /* Data load/store access */
	512	};
9467d44c	513
f61797bd IM	514	#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
f61797bd IM	515	#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
0dacec87	516	#define CPU_RESOLVING_TYPE TYPE_M68K_CPU
f61797bd	517
9467d44c	518	#define cpu_signal_handler cpu_m68k_signal_handler
009a4356	519	#define cpu_list m68k_cpu_list
9467d44c	520
6ebbf390 JM	521	/* MMU modes definitions */
	522	#define MMU_MODE0_SUFFIX _kernel
	523	#define MMU_MODE1_SUFFIX _user
88b2fef6	524	#define MMU_KERNEL_IDX 0
6ebbf390	525	#define MMU_USER_IDX 1
97ed5ccd	526	static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
6ebbf390 JM	527	{
	528	return (env->sr & SR_S) == 0 ? 1 : 0;
	529	}
	530
fe5f7b1b RH	531	bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	532	MMUAccessType access_type, int mmu_idx,
	533	bool probe, uintptr_t retaddr);
e1aaf3a8 PM	534	void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
	535	unsigned size, MMUAccessType access_type,
	536	int mmu_idx, MemTxAttrs attrs,
	537	MemTxResult response, uintptr_t retaddr);
aaedd1f9	538
4f7c64b3	539	typedef CPUM68KState CPUArchState;
2161a612	540	typedef M68kCPU ArchCPU;
4f7c64b3	541
022c62cb	542	#include "exec/cpu-all.h"
622ed360	543
5fa9f1f2 LV	544	/* TB flags */
	545	#define TB_FLAGS_MACSR 0x0f
	546	#define TB_FLAGS_MSR_S_BIT 13
	547	#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT)
	548	#define TB_FLAGS_SFC_S_BIT 14
	549	#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
	550	#define TB_FLAGS_DFC_S_BIT 15
	551	#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
	552
2b3e3cfe	553	static inline void cpu_get_tb_cpu_state(CPUM68KState env, target_ulong pc,
89fee74a	554	target_ulong cs_base, uint32_t flags)
6b917547 AL	555	{
	556	*pc = env->pc;
	557	*cs_base = 0;
5fa9f1f2 LV	558	*flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
	559	if (env->sr & SR_S) {
	560	*flags \|= TB_FLAGS_MSR_S;
	561	*flags \|= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
	562	*flags \|= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
	563	}
6b917547 AL	564	}
6b917547 AL	565
fad866da MA	566	void dump_mmu(CPUM68KState *env);
fad866da MA	567
e6e5906b	568	#endif