[qemu.git] / target / m68k / cpu.h

/*
 * m68k virtual CPU header
 *
 *  Copyright (c) 2005-2007 CodeSourcery
 *  Written by Paul Brook
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef M68K_CPU_H
#define M68K_CPU_H

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUM68KState

#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "fpu/softfloat.h"

#define OS_BYTE     0
#define OS_WORD     1
#define OS_LONG     2
#define OS_SINGLE   3
#define OS_DOUBLE   4
#define OS_EXTENDED 5
#define OS_PACKED   6
#define OS_UNSIZED  7

#define MAX_QREGS 32

#define EXCP_ACCESS         2   /* Access (MMU) error.  */
#define EXCP_ADDRESS        3   /* Address error.  */
#define EXCP_ILLEGAL        4   /* Illegal instruction.  */
#define EXCP_DIV0           5   /* Divide by zero */
#define EXCP_CHK            6   /* CHK, CHK2 Instructions */
#define EXCP_TRAPCC         7   /* FTRAPcc, TRAPcc, TRAPV Instructions */
#define EXCP_PRIVILEGE      8   /* Privilege violation.  */
#define EXCP_TRACE          9
#define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
#define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
#define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
#define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
#define EXCP_FORMAT         14  /* RTE format error.  */
#define EXCP_UNINITIALIZED  15
#define EXCP_SPURIOUS       24  /* Spurious interrupt */
#define EXCP_INT_LEVEL_1    25  /* Level 1 Interrupt autovector */
#define EXCP_INT_LEVEL_7    31  /* Level 7 Interrupt autovector */
#define EXCP_TRAP0          32   /* User trap #0.  */
#define EXCP_TRAP15         47   /* User trap #15.  */
#define EXCP_FP_BSUN        48 /* Branch Set on Unordered */
#define EXCP_FP_INEX        49 /* Inexact result */
#define EXCP_FP_DZ          50 /* Divide by Zero */
#define EXCP_FP_UNFL        51 /* Underflow */
#define EXCP_FP_OPERR       52 /* Operand Error */
#define EXCP_FP_OVFL        53 /* Overflow */
#define EXCP_FP_SNAN        54 /* Signaling Not-A-Number */
#define EXCP_FP_UNIMP       55 /* Unimplemented Data type */
#define EXCP_MMU_CONF       56  /* MMU Configuration Error */
#define EXCP_MMU_ILLEGAL    57  /* MMU Illegal Operation Error */
#define EXCP_MMU_ACCESS     58  /* MMU Access Level Violation Error */
#define EXCP_UNSUPPORTED    61

#define EXCP_RTE            0x100
#define EXCP_HALT_INSN      0x101

#define NB_MMU_MODES 2
#define TARGET_INSN_START_EXTRA_WORDS 1

typedef CPU_LDoubleU FPReg;

typedef struct CPUM68KState {
    uint32_t dregs[8];
    uint32_t aregs[8];
    uint32_t pc;
    uint32_t sr;

    /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
    int current_sp;
    uint32_t sp[3];

    /* Condition flags.  */
    uint32_t cc_op;
    uint32_t cc_x; /* always 0/1 */
    uint32_t cc_n; /* in bit 31 (i.e. negative) */
    uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
    uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
    uint32_t cc_z; /* == 0 or unused */

    FPReg fregs[8];
    FPReg fp_result;
    uint32_t fpcr;
    uint32_t fpsr;
    float_status fp_status;

    uint64_t mactmp;
    /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
       two 8-bit parts.  We store a single 64-bit value and
       rearrange/extend this when changing modes.  */
    uint64_t macc[4];
    uint32_t macsr;
    uint32_t mac_mask;

    /* MMU status.  */
    struct {
        uint32_t ar;
        uint32_t ssw;
        /* 68040 */
        uint16_t tcr;
        uint32_t urp;
        uint32_t srp;
        bool fault;
    } mmu;

    /* Control registers.  */
    uint32_t vbr;
    uint32_t mbar;
    uint32_t rambar0;
    uint32_t cacr;

    int pending_vector;
    int pending_level;

    uint32_t qregs[MAX_QREGS];

    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

    CPU_COMMON

    /* Fields from here on are preserved across CPU reset. */
    uint32_t features;
} CPUM68KState;

/**
 * M68kCPU:
 * @env: #CPUM68KState
 *
 * A Motorola 68k CPU.
 */
struct M68kCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUM68KState env;
};

static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
{
    return container_of(env, M68kCPU, env);
}

#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))

#define ENV_OFFSET offsetof(M68kCPU, env)

void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
                         int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

void m68k_tcg_init(void);
void m68k_cpu_init_gdb(M68kCPU *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_m68k_signal_handler(int host_signum, void *pinfo,
                           void *puc);
uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);


/* Instead of computing the condition codes after each m68k instruction,
 * QEMU just stores one operand (called CC_SRC), the result
 * (called CC_DEST) and the type of operation (called CC_OP). When the
 * condition codes are needed, the condition codes can be calculated
 * using this information. Condition codes are not generated if they
 * are only needed for conditional branches.
 */
typedef enum {
    /* Translator only -- use env->cc_op.  */
    CC_OP_DYNAMIC,

    /* Each flag bit computed into cc_[xcnvz].  */
    CC_OP_FLAGS,

    /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v.  */
    CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
    CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,

    /* X in cc_x, {N,Z,C,V} via cc_n/cc_v.  */
    CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,

    /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n.  */
    CC_OP_LOGIC,

    CC_OP_NB
} CCOp;

#define CCF_C 0x01
#define CCF_V 0x02
#define CCF_Z 0x04
#define CCF_N 0x08
#define CCF_X 0x10

#define SR_I_SHIFT 8
#define SR_I  0x0700
#define SR_M  0x1000
#define SR_S  0x2000
#define SR_T_SHIFT 14
#define SR_T  0xc000

#define M68K_SSP    0
#define M68K_USP    1
#define M68K_ISP    2

/* bits for 68040 special status word */
#define M68K_CP_040  0x8000
#define M68K_CU_040  0x4000
#define M68K_CT_040  0x2000
#define M68K_CM_040  0x1000
#define M68K_MA_040  0x0800
#define M68K_ATC_040 0x0400
#define M68K_LK_040  0x0200
#define M68K_RW_040  0x0100
#define M68K_SIZ_040 0x0060
#define M68K_TT_040  0x0018
#define M68K_TM_040  0x0007

#define M68K_TM_040_DATA  0x0001
#define M68K_TM_040_CODE  0x0002
#define M68K_TM_040_SUPER 0x0004

/* bits for 68040 write back status word */
#define M68K_WBV_040   0x80
#define M68K_WBSIZ_040 0x60
#define M68K_WBBYT_040 0x20
#define M68K_WBWRD_040 0x40
#define M68K_WBLNG_040 0x00
#define M68K_WBTT_040  0x18
#define M68K_WBTM_040  0x07

/* bus access size codes */
#define M68K_BA_SIZE_MASK    0x60
#define M68K_BA_SIZE_BYTE    0x20
#define M68K_BA_SIZE_WORD    0x40
#define M68K_BA_SIZE_LONG    0x00
#define M68K_BA_SIZE_LINE    0x60

/* bus access transfer type codes */
#define M68K_BA_TT_MOVE16    0x08

/* bits for 68040 MMU status register (mmusr) */
#define M68K_MMU_B_040   0x0800
#define M68K_MMU_G_040   0x0400
#define M68K_MMU_U1_040  0x0200
#define M68K_MMU_U0_040  0x0100
#define M68K_MMU_S_040   0x0080
#define M68K_MMU_CM_040  0x0060
#define M68K_MMU_M_040   0x0010
#define M68K_MMU_WP_040  0x0004
#define M68K_MMU_T_040   0x0002
#define M68K_MMU_R_040   0x0001

#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
                              M68K_MMU_U0_040 | M68K_MMU_S_040 | \
                              M68K_MMU_CM_040 | M68K_MMU_M_040 | \
                              M68K_MMU_WP_040)

/* bits for 68040 MMU Translation Control Register */
#define M68K_TCR_ENABLED 0x8000
#define M68K_TCR_PAGE_8K 0x4000

/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
#define M68K_DESC_WRITEPROT 0x00000004
#define M68K_DESC_USED      0x00000008
#define M68K_DESC_MODIFIED  0x00000010
#define M68K_DESC_CACHEMODE 0x00000060
#define M68K_DESC_CM_WRTHRU 0x00000000
#define M68K_DESC_CM_COPYBK 0x00000020
#define M68K_DESC_CM_SERIAL 0x00000040
#define M68K_DESC_CM_NCACHE 0x00000060
#define M68K_DESC_SUPERONLY 0x00000080
#define M68K_DESC_USERATTR  0x00000300
#define M68K_DESC_USERATTR_SHIFT     8
#define M68K_DESC_GLOBAL    0x00000400
#define M68K_DESC_URESERVED 0x00000800

#define M68K_4K_PAGE_MASK           (~0xff)
#define M68K_POINTER_BASE(entry)    (entry & ~0x1ff)
#define M68K_ROOT_INDEX(addr)       ((address >> 23) & 0x1fc)
#define M68K_POINTER_INDEX(addr)    ((address >> 16) & 0x1fc)
#define M68K_4K_PAGE_BASE(entry)    (next & M68K_4K_PAGE_MASK)
#define M68K_4K_PAGE_INDEX(addr)    ((address >> 10) & 0xfc)
#define M68K_8K_PAGE_MASK           (~0x7f)
#define M68K_8K_PAGE_BASE(entry)    (next & M68K_8K_PAGE_MASK)
#define M68K_8K_PAGE_INDEX(addr)    ((address >> 11) & 0x7c)
#define M68K_UDT_VALID(entry)       (entry & 2)
#define M68K_PDT_VALID(entry)       (entry & 3)
#define M68K_PDT_INDIRECT(entry)    ((entry & 3) == 2)
#define M68K_INDIRECT_POINTER(addr) (addr & ~3)

/* m68k Control Registers */

/* ColdFire */
/* Memory Management Control Registers */
#define M68K_CR_ASID     0x003
#define M68K_CR_ACR0     0x004
#define M68K_CR_ACR1     0x005
#define M68K_CR_ACR2     0x006
#define M68K_CR_ACR3     0x007
#define M68K_CR_MMUBAR   0x008

/* Processor Miscellaneous Registers */
#define M68K_CR_PC       0x80F

/* Local Memory and Module Control Registers */
#define M68K_CR_ROMBAR0  0xC00
#define M68K_CR_ROMBAR1  0xC01
#define M68K_CR_RAMBAR0  0xC04
#define M68K_CR_RAMBAR1  0xC05
#define M68K_CR_MPCR     0xC0C
#define M68K_CR_EDRAMBAR 0xC0D
#define M68K_CR_SECMBAR  0xC0E
#define M68K_CR_MBAR     0xC0F

/* Local Memory Address Permutation Control Registers */
#define M68K_CR_PCR1U0   0xD02
#define M68K_CR_PCR1L0   0xD03
#define M68K_CR_PCR2U0   0xD04
#define M68K_CR_PCR2L0   0xD05
#define M68K_CR_PCR3U0   0xD06
#define M68K_CR_PCR3L0   0xD07
#define M68K_CR_PCR1U1   0xD0A
#define M68K_CR_PCR1L1   0xD0B
#define M68K_CR_PCR2U1   0xD0C
#define M68K_CR_PCR2L1   0xD0D
#define M68K_CR_PCR3U1   0xD0E
#define M68K_CR_PCR3L1   0xD0F

/* MC680x0 */
/* MC680[1234]0/CPU32 */
#define M68K_CR_SFC      0x000
#define M68K_CR_DFC      0x001
#define M68K_CR_USP      0x800
#define M68K_CR_VBR      0x801 /* + Coldfire */

/* MC680[234]0 */
#define M68K_CR_CACR     0x002 /* + Coldfire */
#define M68K_CR_CAAR     0x802 /* MC68020 and MC68030 only */
#define M68K_CR_MSP      0x803
#define M68K_CR_ISP      0x804

/* MC68040/MC68LC040 */
#define M68K_CR_TC       0x003
#define M68K_CR_ITT0     0x004
#define M68K_CR_ITT1     0x005
#define M68K_CR_DTT0     0x006
#define M68K_CR_DTT1     0x007
#define M68K_CR_MMUSR    0x805
#define M68K_CR_URP      0x806
#define M68K_CR_SRP      0x807

/* MC68EC040 */
#define M68K_CR_IACR0    0x004
#define M68K_CR_IACR1    0x005
#define M68K_CR_DACR0    0x006
#define M68K_CR_DACR1    0x007

#define M68K_FPIAR_SHIFT  0
#define M68K_FPIAR        (1 << M68K_FPIAR_SHIFT)
#define M68K_FPSR_SHIFT   1
#define M68K_FPSR         (1 << M68K_FPSR_SHIFT)
#define M68K_FPCR_SHIFT   2
#define M68K_FPCR         (1 << M68K_FPCR_SHIFT)

/* Floating-Point Status Register */

/* Condition Code */
#define FPSR_CC_MASK  0x0f000000
#define FPSR_CC_A     0x01000000 /* Not-A-Number */
#define FPSR_CC_I     0x02000000 /* Infinity */
#define FPSR_CC_Z     0x04000000 /* Zero */
#define FPSR_CC_N     0x08000000 /* Negative */

/* Quotient */

#define FPSR_QT_MASK  0x00ff0000

/* Floating-Point Control Register */
/* Rounding mode */
#define FPCR_RND_MASK   0x0030
#define FPCR_RND_N      0x0000
#define FPCR_RND_Z      0x0010
#define FPCR_RND_M      0x0020
#define FPCR_RND_P      0x0030

/* Rounding precision */
#define FPCR_PREC_MASK  0x00c0
#define FPCR_PREC_X     0x0000
#define FPCR_PREC_S     0x0040
#define FPCR_PREC_D     0x0080
#define FPCR_PREC_U     0x00c0

#define FPCR_EXCP_MASK 0xff00

/* CACR fields are implementation defined, but some bits are common.  */
#define M68K_CACR_EUSP  0x10

#define MACSR_PAV0  0x100
#define MACSR_OMC   0x080
#define MACSR_SU    0x040
#define MACSR_FI    0x020
#define MACSR_RT    0x010
#define MACSR_N     0x008
#define MACSR_Z     0x004
#define MACSR_V     0x002
#define MACSR_EV    0x001

void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
void m68k_switch_sp(CPUM68KState *env);

void do_m68k_semihosting(CPUM68KState *env, int nr);

/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
   Each feature covers the subset of instructions common to the
   ISA revisions mentioned.  */

enum m68k_features {
    M68K_FEATURE_M68000,
    M68K_FEATURE_CF_ISA_A,
    M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
    M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
    M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
    M68K_FEATURE_CF_FPU,
    M68K_FEATURE_CF_MAC,
    M68K_FEATURE_CF_EMAC,
    M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
    M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
    M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
    M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
    M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
    M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
    M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
    M68K_FEATURE_BCCL, /* Long conditional branches.  */
    M68K_FEATURE_BITFIELD, /* Bit field insns.  */
    M68K_FEATURE_FPU,
    M68K_FEATURE_CAS,
    M68K_FEATURE_BKPT,
    M68K_FEATURE_RTD,
    M68K_FEATURE_CHK2,
    M68K_FEATURE_M68040, /* instructions specific to MC68040 */
};

static inline int m68k_feature(CPUM68KState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);

void register_m68k_insns (CPUM68KState *env);

/* Coldfire Linux uses 8k pages
 * and m68k linux uses 4k pages
 * use the smallest one
 */
#define TARGET_PAGE_BITS 12

enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_SUPER = 0x01,
    /* 1 bit to indicate direction */
    ACCESS_STORE = 0x02,
    /* 1 bit to indicate debug access */
    ACCESS_DEBUG = 0x04,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_DATA  = 0x20, /* Data load/store access        */
};

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model)

#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX

#define cpu_signal_handler cpu_m68k_signal_handler
#define cpu_list m68k_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
{
    return (env->sr & SR_S) == 0 ? 1 : 0;
}

int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
                              int mmu_idx);
void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
                                bool is_write, bool is_exec, int is_asi,
                                unsigned size);

#include "exec/cpu-all.h"

static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = (env->sr & SR_S)                   /* Bit  13 */
            | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
}

#endif
Commit	Line	Data
e6e5906b PB	1	/*
e6e5906b PB	2	* m68k virtual CPU header
5fafdf24	3	*
0633879f	4	* Copyright (c) 2005-2007 CodeSourcery
e6e5906b PB	5	* Written by Paul Brook
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
e6e5906b	19	*/
07f5a258 MA	20
	21	#ifndef M68K_CPU_H
	22	#define M68K_CPU_H
e6e5906b PB	23
	24	#define TARGET_LONG_BITS 32
	25
9349b4f9	26	#define CPUArchState struct CPUM68KState
c2764719	27
9a78eead	28	#include "qemu-common.h"
022c62cb	29	#include "exec/cpu-defs.h"
a836b8fa	30	#include "cpu-qom.h"
6b4c305c	31	#include "fpu/softfloat.h"
e6e5906b	32
7ef25cdd LV	33	#define OS_BYTE 0
	34	#define OS_WORD 1
	35	#define OS_LONG 2
	36	#define OS_SINGLE 3
	37	#define OS_DOUBLE 4
	38	#define OS_EXTENDED 5
	39	#define OS_PACKED 6
f2224f2c	40	#define OS_UNSIZED 7
7ef25cdd	41
e6e5906b PB	42	#define MAX_QREGS 32
e6e5906b PB	43
e6e5906b PB	44	#define EXCP_ACCESS 2 /* Access (MMU) error. */
	45	#define EXCP_ADDRESS 3 /* Address error. */
	46	#define EXCP_ILLEGAL 4 /* Illegal instruction. */
	47	#define EXCP_DIV0 5 /* Divide by zero */
5beb144e LV	48	#define EXCP_CHK 6 /* CHK, CHK2 Instructions */
5beb144e LV	49	#define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */
e6e5906b PB	50	#define EXCP_PRIVILEGE 8 /* Privilege violation. */
	51	#define EXCP_TRACE 9
	52	#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
	53	#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
	54	#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
	55	#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
	56	#define EXCP_FORMAT 14 /* RTE format error. */
	57	#define EXCP_UNINITIALIZED 15
5beb144e LV	58	#define EXCP_SPURIOUS 24 /* Spurious interrupt */
	59	#define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */
	60	#define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */
e6e5906b PB	61	#define EXCP_TRAP0 32 /* User trap #0. */
e6e5906b PB	62	#define EXCP_TRAP15 47 /* User trap #15. */
f83311e4 LV	63	#define EXCP_FP_BSUN 48 /* Branch Set on Unordered */
	64	#define EXCP_FP_INEX 49 /* Inexact result */
	65	#define EXCP_FP_DZ 50 /* Divide by Zero */
	66	#define EXCP_FP_UNFL 51 /* Underflow */
	67	#define EXCP_FP_OPERR 52 /* Operand Error */
	68	#define EXCP_FP_OVFL 53 /* Overflow */
	69	#define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */
	70	#define EXCP_FP_UNIMP 55 /* Unimplemented Data type */
5beb144e LV	71	#define EXCP_MMU_CONF 56 /* MMU Configuration Error */
	72	#define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */
	73	#define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */
e6e5906b	74	#define EXCP_UNSUPPORTED 61
e6e5906b	75
0633879f	76	#define EXCP_RTE 0x100
a87295e8	77	#define EXCP_HALT_INSN 0x101
0633879f	78
6ebbf390	79	#define NB_MMU_MODES 2
20a8856e	80	#define TARGET_INSN_START_EXTRA_WORDS 1
6ebbf390	81
f83311e4 LV	82	typedef CPU_LDoubleU FPReg;
f83311e4 LV	83
e6e5906b PB	84	typedef struct CPUM68KState {
	85	uint32_t dregs[8];
	86	uint32_t aregs[8];
	87	uint32_t pc;
	88	uint32_t sr;
	89
20dcee94 PB	90	/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
20dcee94 PB	91	int current_sp;
6e22b28e	92	uint32_t sp[3];
20dcee94	93
e6e5906b PB	94	/* Condition flags. */
e6e5906b PB	95	uint32_t cc_op;
620c6cf6 RH	96	uint32_t cc_x; /* always 0/1 */
	97	uint32_t cc_n; /* in bit 31 (i.e. negative) */
	98	uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
	99	uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
	100	uint32_t cc_z; /* == 0 or unused */
e6e5906b	101
f83311e4 LV	102	FPReg fregs[8];
f83311e4 LV	103	FPReg fp_result;
e6e5906b PB	104	uint32_t fpcr;
	105	uint32_t fpsr;
	106	float_status fp_status;
	107
acf930aa PB	108	uint64_t mactmp;
	109	/* EMAC Hardware deals with 48-bit values composed of one 32-bit and
	110	two 8-bit parts. We store a single 64-bit value and
	111	rearrange/extend this when changing modes. */
	112	uint64_t macc[4];
	113	uint32_t macsr;
	114	uint32_t mac_mask;
	115
e6e5906b PB	116	/* MMU status. */
	117	struct {
	118	uint32_t ar;
88b2fef6 LV	119	uint32_t ssw;
	120	/* 68040 */
	121	uint16_t tcr;
	122	uint32_t urp;
	123	uint32_t srp;
	124	bool fault;
e6e5906b	125	} mmu;
0633879f PB	126
	127	/* Control registers. */
	128	uint32_t vbr;
	129	uint32_t mbar;
	130	uint32_t rambar0;
20dcee94	131	uint32_t cacr;
0633879f	132
0633879f PB	133	int pending_vector;
0633879f PB	134	int pending_level;
e6e5906b PB	135
	136	uint32_t qregs[MAX_QREGS];
	137
1f5c00cf AB	138	/* Fields up to this point are cleared by a CPU reset */
	139	struct {} end_reset_fields;
	140
e6e5906b	141	CPU_COMMON
aaed909a	142
f0c3c505	143	/* Fields from here on are preserved across CPU reset. */
aaed909a	144	uint32_t features;
e6e5906b PB	145	} CPUM68KState;
e6e5906b PB	146
a836b8fa PB	147	/**
	148	* M68kCPU:
	149	* @env: #CPUM68KState
	150	*
	151	* A Motorola 68k CPU.
	152	*/
	153	struct M68kCPU {
	154	/< private >/
	155	CPUState parent_obj;
	156	/< public >/
	157
	158	CPUM68KState env;
	159	};
	160
	161	static inline M68kCPU m68k_env_get_cpu(CPUM68KState env)
	162	{
	163	return container_of(env, M68kCPU, env);
	164	}
	165
	166	#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
	167
	168	#define ENV_OFFSET offsetof(M68kCPU, env)
	169
	170	void m68k_cpu_do_interrupt(CPUState *cpu);
	171	bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
	172	void m68k_cpu_dump_state(CPUState cpu, FILE f, fprintf_function cpu_fprintf,
	173	int flags);
	174	hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	175	int m68k_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	176	int m68k_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	177
e1f3808e	178	void m68k_tcg_init(void);
6d1bbc62	179	void m68k_cpu_init_gdb(M68kCPU *cpu);
e6e5906b PB	180	/* you can call this signal handler from your SIGBUS and SIGSEGV
	181	signal handlers to inform the virtual CPU of exceptions. non zero
	182	is returned if the signal was handled by the virtual CPU. */
5fafdf24	183	int cpu_m68k_signal_handler(int host_signum, void *pinfo,
e6e5906b	184	void *puc);
99c51448 RH	185	uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
99c51448 RH	186	void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
d2f8fb8e	187	void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
ba624944	188	void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
e6e5906b	189
c3ce5a23 PB	190
	191	/* Instead of computing the condition codes after each m68k instruction,
	192	* QEMU just stores one operand (called CC_SRC), the result
	193	* (called CC_DEST) and the type of operation (called CC_OP). When the
	194	* condition codes are needed, the condition codes can be calculated
	195	* using this information. Condition codes are not generated if they
	196	* are only needed for conditional branches.
	197	*/
9fdb533f	198	typedef enum {
620c6cf6	199	/* Translator only -- use env->cc_op. */
7deddf96	200	CC_OP_DYNAMIC,
620c6cf6 RH	201
	202	/* Each flag bit computed into cc_[xcnvz]. */
	203	CC_OP_FLAGS,
	204
	205	/* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */
db3d7945 LV	206	CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
db3d7945 LV	207	CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
620c6cf6 RH	208
620c6cf6 RH	209	/* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */
db3d7945	210	CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
620c6cf6 RH	211
	212	/* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
	213	CC_OP_LOGIC,
	214
	215	CC_OP_NB
9fdb533f	216	} CCOp;
e6e5906b PB	217
	218	#define CCF_C 0x01
	219	#define CCF_V 0x02
	220	#define CCF_Z 0x04
	221	#define CCF_N 0x08
0633879f PB	222	#define CCF_X 0x10
	223
	224	#define SR_I_SHIFT 8
	225	#define SR_I 0x0700
	226	#define SR_M 0x1000
	227	#define SR_S 0x2000
cc523026 LV	228	#define SR_T_SHIFT 14
cc523026 LV	229	#define SR_T 0xc000
e6e5906b	230
20dcee94 PB	231	#define M68K_SSP 0
20dcee94 PB	232	#define M68K_USP 1
6e22b28e LV	233	#define M68K_ISP 2
6e22b28e LV	234
88b2fef6 LV	235	/* bits for 68040 special status word */
	236	#define M68K_CP_040 0x8000
	237	#define M68K_CU_040 0x4000
	238	#define M68K_CT_040 0x2000
	239	#define M68K_CM_040 0x1000
	240	#define M68K_MA_040 0x0800
	241	#define M68K_ATC_040 0x0400
	242	#define M68K_LK_040 0x0200
	243	#define M68K_RW_040 0x0100
	244	#define M68K_SIZ_040 0x0060
	245	#define M68K_TT_040 0x0018
	246	#define M68K_TM_040 0x0007
	247
	248	#define M68K_TM_040_DATA 0x0001
	249	#define M68K_TM_040_CODE 0x0002
	250	#define M68K_TM_040_SUPER 0x0004
	251
	252	/* bits for 68040 write back status word */
	253	#define M68K_WBV_040 0x80
	254	#define M68K_WBSIZ_040 0x60
	255	#define M68K_WBBYT_040 0x20
	256	#define M68K_WBWRD_040 0x40
	257	#define M68K_WBLNG_040 0x00
	258	#define M68K_WBTT_040 0x18
	259	#define M68K_WBTM_040 0x07
	260
	261	/* bus access size codes */
	262	#define M68K_BA_SIZE_MASK 0x60
	263	#define M68K_BA_SIZE_BYTE 0x20
	264	#define M68K_BA_SIZE_WORD 0x40
	265	#define M68K_BA_SIZE_LONG 0x00
	266	#define M68K_BA_SIZE_LINE 0x60
	267
	268	/* bus access transfer type codes */
	269	#define M68K_BA_TT_MOVE16 0x08
	270
	271	/* bits for 68040 MMU status register (mmusr) */
	272	#define M68K_MMU_B_040 0x0800
	273	#define M68K_MMU_G_040 0x0400
	274	#define M68K_MMU_U1_040 0x0200
	275	#define M68K_MMU_U0_040 0x0100
	276	#define M68K_MMU_S_040 0x0080
	277	#define M68K_MMU_CM_040 0x0060
	278	#define M68K_MMU_M_040 0x0010
	279	#define M68K_MMU_WP_040 0x0004
	280	#define M68K_MMU_T_040 0x0002
	281	#define M68K_MMU_R_040 0x0001
	282
	283	#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 \| M68K_MMU_U1_040 \| \
	284	M68K_MMU_U0_040 \| M68K_MMU_S_040 \| \
	285	M68K_MMU_CM_040 \| M68K_MMU_M_040 \| \
	286	M68K_MMU_WP_040)
	287
	288	/* bits for 68040 MMU Translation Control Register */
	289	#define M68K_TCR_ENABLED 0x8000
	290	#define M68K_TCR_PAGE_8K 0x4000
	291
	292	/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
	293	#define M68K_DESC_WRITEPROT 0x00000004
	294	#define M68K_DESC_USED 0x00000008
	295	#define M68K_DESC_MODIFIED 0x00000010
	296	#define M68K_DESC_CACHEMODE 0x00000060
	297	#define M68K_DESC_CM_WRTHRU 0x00000000
	298	#define M68K_DESC_CM_COPYBK 0x00000020
299	#define M68K_DESC_CM_SERIAL 0x00000040
300	#define M68K_DESC_CM_NCACHE 0x00000060
301	#define M68K_DESC_SUPERONLY 0x00000080
302	#define M68K_DESC_USERATTR 0x00000300
303	#define M68K_DESC_USERATTR_SHIFT 8
304	#define M68K_DESC_GLOBAL 0x00000400
305	#define M68K_DESC_URESERVED 0x00000800
306
307	#define M68K_4K_PAGE_MASK (~0xff)
308	#define M68K_POINTER_BASE(entry) (entry & ~0x1ff)
309	#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc)
310	#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc)
311	#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK)
312	#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc)
313	#define M68K_8K_PAGE_MASK (~0x7f)
314	#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK)
315	#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c)
316	#define M68K_UDT_VALID(entry) (entry & 2)
317	#define M68K_PDT_VALID(entry) (entry & 3)
318	#define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2)
319	#define M68K_INDIRECT_POINTER(addr) (addr & ~3)
320
6e22b28e LV	321	/* m68k Control Registers */
	322
	323	/* ColdFire */
	324	/* Memory Management Control Registers */
	325	#define M68K_CR_ASID 0x003
	326	#define M68K_CR_ACR0 0x004
	327	#define M68K_CR_ACR1 0x005
	328	#define M68K_CR_ACR2 0x006
	329	#define M68K_CR_ACR3 0x007
	330	#define M68K_CR_MMUBAR 0x008
	331
	332	/* Processor Miscellaneous Registers */
	333	#define M68K_CR_PC 0x80F
	334
	335	/* Local Memory and Module Control Registers */
	336	#define M68K_CR_ROMBAR0 0xC00
	337	#define M68K_CR_ROMBAR1 0xC01
	338	#define M68K_CR_RAMBAR0 0xC04
	339	#define M68K_CR_RAMBAR1 0xC05
	340	#define M68K_CR_MPCR 0xC0C
	341	#define M68K_CR_EDRAMBAR 0xC0D
	342	#define M68K_CR_SECMBAR 0xC0E
	343	#define M68K_CR_MBAR 0xC0F
	344
	345	/* Local Memory Address Permutation Control Registers */
	346	#define M68K_CR_PCR1U0 0xD02
	347	#define M68K_CR_PCR1L0 0xD03
	348	#define M68K_CR_PCR2U0 0xD04
	349	#define M68K_CR_PCR2L0 0xD05
	350	#define M68K_CR_PCR3U0 0xD06
	351	#define M68K_CR_PCR3L0 0xD07
	352	#define M68K_CR_PCR1U1 0xD0A
	353	#define M68K_CR_PCR1L1 0xD0B
	354	#define M68K_CR_PCR2U1 0xD0C
	355	#define M68K_CR_PCR2L1 0xD0D
	356	#define M68K_CR_PCR3U1 0xD0E
	357	#define M68K_CR_PCR3L1 0xD0F
	358
	359	/* MC680x0 */
	360	/* MC680[1234]0/CPU32 */
	361	#define M68K_CR_SFC 0x000
	362	#define M68K_CR_DFC 0x001
	363	#define M68K_CR_USP 0x800
	364	#define M68K_CR_VBR 0x801 /* + Coldfire */
	365
	366	/* MC680[234]0 */
	367	#define M68K_CR_CACR 0x002 /* + Coldfire */
	368	#define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */
	369	#define M68K_CR_MSP 0x803
	370	#define M68K_CR_ISP 0x804
	371
	372	/* MC68040/MC68LC040 */
	373	#define M68K_CR_TC 0x003
	374	#define M68K_CR_ITT0 0x004
	375	#define M68K_CR_ITT1 0x005
	376	#define M68K_CR_DTT0 0x006
	377	#define M68K_CR_DTT1 0x007
	378	#define M68K_CR_MMUSR 0x805
	379	#define M68K_CR_URP 0x806
	380	#define M68K_CR_SRP 0x807
	381
	382	/* MC68EC040 */
	383	#define M68K_CR_IACR0 0x004
	384	#define M68K_CR_IACR1 0x005
385	#define M68K_CR_DACR0 0x006
386	#define M68K_CR_DACR1 0x007
20dcee94	387
ba624944 LV	388	#define M68K_FPIAR_SHIFT 0
	389	#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
	390	#define M68K_FPSR_SHIFT 1
	391	#define M68K_FPSR (1 << M68K_FPSR_SHIFT)
	392	#define M68K_FPCR_SHIFT 2
	393	#define M68K_FPCR (1 << M68K_FPCR_SHIFT)
	394
	395	/* Floating-Point Status Register */
	396
	397	/* Condition Code */
	398	#define FPSR_CC_MASK 0x0f000000
	399	#define FPSR_CC_A 0x01000000 /* Not-A-Number */
	400	#define FPSR_CC_I 0x02000000 /* Infinity */
	401	#define FPSR_CC_Z 0x04000000 /* Zero */
	402	#define FPSR_CC_N 0x08000000 /* Negative */
	403
	404	/* Quotient */
	405
	406	#define FPSR_QT_MASK 0x00ff0000
	407
	408	/* Floating-Point Control Register */
	409	/* Rounding mode */
	410	#define FPCR_RND_MASK 0x0030
	411	#define FPCR_RND_N 0x0000
	412	#define FPCR_RND_Z 0x0010
	413	#define FPCR_RND_M 0x0020
	414	#define FPCR_RND_P 0x0030
	415
	416	/* Rounding precision */
	417	#define FPCR_PREC_MASK 0x00c0
	418	#define FPCR_PREC_X 0x0000
	419	#define FPCR_PREC_S 0x0040
	420	#define FPCR_PREC_D 0x0080
	421	#define FPCR_PREC_U 0x00c0
	422
	423	#define FPCR_EXCP_MASK 0xff00
	424
20dcee94 PB	425	/* CACR fields are implementation defined, but some bits are common. */
	426	#define M68K_CACR_EUSP 0x10
	427
acf930aa PB	428	#define MACSR_PAV0 0x100
	429	#define MACSR_OMC 0x080
	430	#define MACSR_SU 0x040
	431	#define MACSR_FI 0x020
	432	#define MACSR_RT 0x010
	433	#define MACSR_N 0x008
	434	#define MACSR_Z 0x004
	435	#define MACSR_V 0x002
	436	#define MACSR_EV 0x001
	437
cb3fb38e	438	void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
20dcee94	439	void m68k_switch_sp(CPUM68KState *env);
e6e5906b	440
a87295e8 PB	441	void do_m68k_semihosting(CPUM68KState *env, int nr);
a87295e8 PB	442
d315c888 PB	443	/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
	444	Each feature covers the subset of instructions common to the
	445	ISA revisions mentioned. */
	446
0402f767	447	enum m68k_features {
f076803b	448	M68K_FEATURE_M68000,
0402f767	449	M68K_FEATURE_CF_ISA_A,
d315c888 PB	450	M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
	451	M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
	452	M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
0402f767 PB	453	M68K_FEATURE_CF_FPU,
	454	M68K_FEATURE_CF_MAC,
	455	M68K_FEATURE_CF_EMAC,
d315c888 PB	456	M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
d315c888 PB	457	M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
e6dbd3b3	458	M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
f076803b LV	459	M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
	460	M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
	461	M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
	462	M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
	463	M68K_FEATURE_BCCL, /* Long conditional branches. */
	464	M68K_FEATURE_BITFIELD, /* Bit field insns. */
	465	M68K_FEATURE_FPU,
	466	M68K_FEATURE_CAS,
	467	M68K_FEATURE_BKPT,
18059c9e	468	M68K_FEATURE_RTD,
8bf6cbaf	469	M68K_FEATURE_CHK2,
9d4f0429	470	M68K_FEATURE_M68040, /* instructions specific to MC68040 */
0402f767 PB	471	};
	472
	473	static inline int m68k_feature(CPUM68KState *env, int feature)
	474	{
	475	return (env->features & (1u << feature)) != 0;
	476	}
	477
9a78eead	478	void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
009a4356	479
0402f767 PB	480	void register_m68k_insns (CPUM68KState *env);
0402f767 PB	481
2b04e85a LV	482	/* Coldfire Linux uses 8k pages
2b04e85a LV	483	* and m68k linux uses 4k pages
88b2fef6	484	* use the smallest one
2b04e85a LV	485	*/
2b04e85a LV	486	#define TARGET_PAGE_BITS 12
88b2fef6 LV	487
	488	enum {
	489	/* 1 bit to define user level / supervisor access */
	490	ACCESS_SUPER = 0x01,
	491	/* 1 bit to indicate direction */
	492	ACCESS_STORE = 0x02,
	493	/* 1 bit to indicate debug access */
	494	ACCESS_DEBUG = 0x04,
	495	/* Type of instruction that generated the access */
	496	ACCESS_CODE = 0x10, /* Code fetch access */
	497	ACCESS_DATA = 0x20, /* Data load/store access */
	498	};
9467d44c	499
52705890 RH	500	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	501	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	502
f47cf4e3	503	#define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model)
c7937d9f	504
f61797bd IM	505	#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
	506	#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
	507
9467d44c	508	#define cpu_signal_handler cpu_m68k_signal_handler
009a4356	509	#define cpu_list m68k_cpu_list
9467d44c	510
6ebbf390 JM	511	/* MMU modes definitions */
	512	#define MMU_MODE0_SUFFIX _kernel
	513	#define MMU_MODE1_SUFFIX _user
88b2fef6	514	#define MMU_KERNEL_IDX 0
6ebbf390	515	#define MMU_USER_IDX 1
97ed5ccd	516	static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
6ebbf390 JM	517	{
	518	return (env->sr & SR_S) == 0 ? 1 : 0;
	519	}
	520
98670d47	521	int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
97b348e7	522	int mmu_idx);
88b2fef6 LV	523	void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
	524	bool is_write, bool is_exec, int is_asi,
	525	unsigned size);
aaedd1f9	526
022c62cb	527	#include "exec/cpu-all.h"
622ed360	528
2b3e3cfe	529	static inline void cpu_get_tb_cpu_state(CPUM68KState env, target_ulong pc,
89fee74a	530	target_ulong cs_base, uint32_t flags)
6b917547 AL	531	{
	532	*pc = env->pc;
	533	*cs_base = 0;
ba624944	534	flags = (env->sr & SR_S) / Bit 13 */
6b917547 AL	535	\| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
	536	}
	537
e6e5906b	538	#endif