[qemu.git] / hw / ide / cmd646.c

/*
 * QEMU IDE Emulation: PCI cmd646 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "hw/isa/isa.h"
#include "sysemu/dma.h"
#include "sysemu/reset.h"

#include "hw/ide/pci.h"
#include "trace.h"

/* CMD646 specific */
#define CFR		0x50
#define   CFR_INTR_CH0	0x04
#define CNTRL		0x51
#define   CNTRL_EN_CH0	0x04
#define   CNTRL_EN_CH1	0x08
#define ARTTIM23	0x57
#define    ARTTIM23_INTR_CH1	0x10
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define   MRDMODE_BLK_CH0	0x10
#define   MRDMODE_BLK_CH1	0x20
#define UDIDETCR0	0x73
#define UDIDETCR1	0x7B

static void cmd646_update_irq(PCIDevice *pd);

static void cmd646_update_dma_interrupts(PCIDevice *pd)
{
    /* Sync DMA interrupt status from UDMA interrupt status */
    if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
        pd->config[CFR] |= CFR_INTR_CH0;
    } else {
        pd->config[CFR] &= ~CFR_INTR_CH0;
    }

    if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
        pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
    } else {
        pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
    }
}

static void cmd646_update_udma_interrupts(PCIDevice *pd)
{
    /* Sync UDMA interrupt status from DMA interrupt status */
    if (pd->config[CFR] & CFR_INTR_CH0) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
    }

    if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
    }
}

static uint64_t bmdma_read(void *opaque, hwaddr addr,
                           unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 1:
        val = pci_dev->config[MRDMODE];
        break;
    case 2:
        val = bm->status;
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            val = pci_dev->config[UDIDETCR0];
        } else {
            val = pci_dev->config[UDIDETCR1];
        }
        break;
    default:
        val = 0xff;
        break;
    }

    trace_bmdma_read_cmd646(addr, val);
    return val;
}

static void bmdma_write(void *opaque, hwaddr addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);

    if (size != 1) {
        return;
    }

    trace_bmdma_write_cmd646(addr, val);
    switch(addr & 3) {
    case 0:
        bmdma_cmd_writeb(bm, val);
        break;
    case 1:
        pci_dev->config[MRDMODE] =
            (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
        cmd646_update_dma_interrupts(pci_dev);
        cmd646_update_irq(pci_dev);
        break;
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            pci_dev->config[UDIDETCR0] = val;
        } else {
            pci_dev->config[UDIDETCR1] = val;
        }
        break;
    }
}

static const MemoryRegionOps cmd646_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    BMDMAState *bm;
    int i;

    memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
    for(i = 0;i < 2; i++) {
        bm = &d->bmdma[i];
        memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
                              "cmd646-bmdma-bus", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, OBJECT(d),
                              &bmdma_addr_ioport_ops, bm,
                              "cmd646-bmdma-ioport", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void cmd646_update_irq(PCIDevice *pd)
{
    int pci_level;

    pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
                 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
        ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
         !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
    pci_set_irq(pd, pci_level);
}

/* the PCI irq level is the logical OR of the two channels */
static void cmd646_set_irq(void *opaque, int channel, int level)
{
    PCIIDEState *d = opaque;
    PCIDevice *pd = PCI_DEVICE(d);
    int irq_mask;

    irq_mask = MRDMODE_INTR_CH0 << channel;
    if (level) {
        pd->config[MRDMODE] |= irq_mask;
    } else {
        pd->config[MRDMODE] &= ~irq_mask;
    }
    cmd646_update_dma_interrupts(pd);
    cmd646_update_irq(pd);
}

static void cmd646_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    unsigned int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }
}

static uint32_t cmd646_pci_config_read(PCIDevice *d,
                                       uint32_t address, int len)
{
    return pci_default_read_config(d, address, len);
}

static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
                                    int l)
{
    uint32_t i;

    pci_default_write_config(d, addr, val, l);

    for (i = addr; i < addr + l; i++) {
        switch (i) {
        case CFR:
        case ARTTIM23:
            cmd646_update_udma_interrupts(d);
            break;
        case MRDMODE:
            cmd646_update_dma_interrupts(d);
            break;
        }
    }

    cmd646_update_irq(d);
}

/* CMD646 PCI IDE controller */
static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;
    qemu_irq *irq;
    int i;

    pci_conf[PCI_CLASS_PROG] = 0x8f;

    pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
    if (d->secondary) {
        /* XXX: if not enabled, really disable the seconday IDE controller */
        pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
    }

    /* Set write-to-clear interrupt bits */
    dev->wmask[CFR] = 0x0;
    dev->w1cmask[CFR] = CFR_INTR_CH0;
    dev->wmask[ARTTIM23] = 0x0;
    dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
    dev->wmask[MRDMODE] = 0x0;
    dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;

    memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
                          &d->bus[0], "cmd646-data0", 8);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);

    memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
                          &d->bus[0], "cmd646-cmd0", 4);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);

    memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
                          &d->bus[1], "cmd646-data1", 8);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);

    memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
                          &d->bus[1], "cmd646-cmd1", 4);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);

    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    /* TODO: RST# value should be 0 */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
        ide_init2(&d->bus[i], irq[i]);

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        ide_register_restart_cb(&d->bus[i]);
    }
    g_free(irq);

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
    qemu_register_reset(cmd646_reset, d);
}

static void pci_cmd646_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
    }
}

void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
                         int secondary_ide_enabled)
{
    PCIDevice *dev;

    dev = pci_create(bus, -1, "cmd646-ide");
    qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
    qdev_init_nofail(&dev->qdev);

    pci_ide_create_devs(dev, hd_table);
}

static Property cmd646_ide_properties[] = {
    DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void cmd646_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_cmd646_ide_realize;
    k->exit = pci_cmd646_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_CMD;
    k->device_id = PCI_DEVICE_ID_CMD_646;
    k->revision = 0x07;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    k->config_read = cmd646_pci_config_read;
    k->config_write = cmd646_pci_config_write;
    dc->props = cmd646_ide_properties;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}

static const TypeInfo cmd646_ide_info = {
    .name          = "cmd646-ide",
    .parent        = TYPE_PCI_IDE,
    .class_init    = cmd646_ide_class_init,
};

static void cmd646_ide_register_types(void)
{
    type_register_static(&cmd646_ide_info);
}

type_init(cmd646_ide_register_types)
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI cmd646 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
0b8fa32f	25
53239262	26	#include "qemu/osdep.h"
a9c94277	27	#include "hw/pci/pci.h"
a27bd6c7	28	#include "hw/qdev-properties.h"
d6454270	29	#include "migration/vmstate.h"
0b8fa32f	30	#include "qemu/module.h"
a9c94277	31	#include "hw/isa/isa.h"
9c17d615	32	#include "sysemu/dma.h"
71e8a915	33	#include "sysemu/reset.h"
4c3df0ec	34
a9c94277	35	#include "hw/ide/pci.h"
3eee2611	36	#include "trace.h"
4c3df0ec JQ	37
4c3df0ec JQ	38	/* CMD646 specific */
5bbc0a70 MCA	39	#define CFR 0x50
5bbc0a70 MCA	40	#define CFR_INTR_CH0 0x04
58f16a7b MCA	41	#define CNTRL 0x51
	42	#define CNTRL_EN_CH0 0x04
	43	#define CNTRL_EN_CH1 0x08
5bbc0a70 MCA	44	#define ARTTIM23 0x57
5bbc0a70 MCA	45	#define ARTTIM23_INTR_CH1 0x10
4c3df0ec JQ	46	#define MRDMODE 0x71
	47	#define MRDMODE_INTR_CH0 0x04
	48	#define MRDMODE_INTR_CH1 0x08
	49	#define MRDMODE_BLK_CH0 0x10
	50	#define MRDMODE_BLK_CH1 0x20
	51	#define UDIDETCR0 0x73
	52	#define UDIDETCR1 0x7B
	53
dab91a1e	54	static void cmd646_update_irq(PCIDevice *pd);
4c3df0ec	55
5bbc0a70 MCA	56	static void cmd646_update_dma_interrupts(PCIDevice *pd)
	57	{
	58	/* Sync DMA interrupt status from UDMA interrupt status */
	59	if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
	60	pd->config[CFR] \|= CFR_INTR_CH0;
	61	} else {
	62	pd->config[CFR] &= ~CFR_INTR_CH0;
	63	}
	64
	65	if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
	66	pd->config[ARTTIM23] \|= ARTTIM23_INTR_CH1;
	67	} else {
	68	pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
	69	}
	70	}
	71
271dddd1 MCA	72	static void cmd646_update_udma_interrupts(PCIDevice *pd)
	73	{
	74	/* Sync UDMA interrupt status from DMA interrupt status */
	75	if (pd->config[CFR] & CFR_INTR_CH0) {
	76	pd->config[MRDMODE] \|= MRDMODE_INTR_CH0;
	77	} else {
	78	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
	79	}
	80
	81	if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
	82	pd->config[MRDMODE] \|= MRDMODE_INTR_CH1;
	83	} else {
	84	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
	85	}
	86	}
	87
a8170e5e	88	static uint64_t bmdma_read(void *opaque, hwaddr addr,
a9deb8c6 AK	89	unsigned size)
	90	{
	91	BMDMAState *bm = opaque;
f6c11d56	92	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
4c3df0ec JQ	93	uint32_t val;
4c3df0ec JQ	94
a9deb8c6 AK	95	if (size != 1) {
	96	return ((uint64_t)1 << (size * 8)) - 1;
	97	}
	98
4c3df0ec JQ	99	switch(addr & 3) {
	100	case 0:
	101	val = bm->cmd;
	102	break;
	103	case 1:
f6c11d56	104	val = pci_dev->config[MRDMODE];
4c3df0ec JQ	105	break;
	106	case 2:
	107	val = bm->status;
	108	break;
	109	case 3:
f6c11d56 AF	110	if (bm == &bm->pci_dev->bmdma[0]) {
f6c11d56 AF	111	val = pci_dev->config[UDIDETCR0];
4c3df0ec	112	} else {
f6c11d56	113	val = pci_dev->config[UDIDETCR1];
4c3df0ec JQ	114	}
	115	break;
	116	default:
	117	val = 0xff;
	118	break;
	119	}
3eee2611 JS	120
3eee2611 JS	121	trace_bmdma_read_cmd646(addr, val);
4c3df0ec JQ	122	return val;
	123	}
	124
a8170e5e	125	static void bmdma_write(void *opaque, hwaddr addr,
a9deb8c6	126	uint64_t val, unsigned size)
70ae65f5	127	{
a9deb8c6	128	BMDMAState *bm = opaque;
f6c11d56	129	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
70ae65f5	130
a9deb8c6 AK	131	if (size != 1) {
	132	return;
	133	}
70ae65f5	134
3eee2611	135	trace_bmdma_write_cmd646(addr, val);
4c3df0ec	136	switch(addr & 3) {
50a48094	137	case 0:
a9deb8c6	138	bmdma_cmd_writeb(bm, val);
50a48094	139	break;
4c3df0ec	140	case 1:
f6c11d56 AF	141	pci_dev->config[MRDMODE] =
f6c11d56 AF	142	(pci_dev->config[MRDMODE] & ~0x30) \| (val & 0x30);
5bbc0a70	143	cmd646_update_dma_interrupts(pci_dev);
dab91a1e	144	cmd646_update_irq(pci_dev);
4c3df0ec JQ	145	break;
	146	case 2:
	147	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	148	break;
	149	case 3:
f6c11d56 AF	150	if (bm == &bm->pci_dev->bmdma[0]) {
	151	pci_dev->config[UDIDETCR0] = val;
	152	} else {
	153	pci_dev->config[UDIDETCR1] = val;
	154	}
4c3df0ec JQ	155	break;
	156	}
	157	}
	158
a348f108	159	static const MemoryRegionOps cmd646_bmdma_ops = {
a9deb8c6 AK	160	.read = bmdma_read,
	161	.write = bmdma_write,
	162	};
70ae65f5	163
a9deb8c6	164	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	165	{
a9deb8c6	166	BMDMAState *bm;
4c3df0ec JQ	167	int i;
4c3df0ec JQ	168
1437c94b	169	memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
4c3df0ec	170	for(i = 0;i < 2; i++) {
a9deb8c6	171	bm = &d->bmdma[i];
1437c94b	172	memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
a9deb8c6 AK	173	"cmd646-bmdma-bus", 4);
a9deb8c6 AK	174	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
1437c94b PB	175	memory_region_init_io(&bm->addr_ioport, OBJECT(d),
1437c94b PB	176	&bmdma_addr_ioport_ops, bm,
a9deb8c6 AK	177	"cmd646-bmdma-ioport", 4);
a9deb8c6 AK	178	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	179	}
	180	}
	181
dab91a1e	182	static void cmd646_update_irq(PCIDevice *pd)
4c3df0ec JQ	183	{
4c3df0ec JQ	184	int pci_level;
f6c11d56 AF	185
	186	pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
	187	!(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) \|\|
	188	((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
	189	!(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
9e64f8a3	190	pci_set_irq(pd, pci_level);
4c3df0ec JQ	191	}
	192
	193	/* the PCI irq level is the logical OR of the two channels */
	194	static void cmd646_set_irq(void *opaque, int channel, int level)
	195	{
	196	PCIIDEState *d = opaque;
f6c11d56	197	PCIDevice *pd = PCI_DEVICE(d);
4c3df0ec JQ	198	int irq_mask;
	199
	200	irq_mask = MRDMODE_INTR_CH0 << channel;
f6c11d56 AF	201	if (level) {
	202	pd->config[MRDMODE] \|= irq_mask;
	203	} else {
	204	pd->config[MRDMODE] &= ~irq_mask;
	205	}
5bbc0a70	206	cmd646_update_dma_interrupts(pd);
dab91a1e	207	cmd646_update_irq(pd);
4c3df0ec JQ	208	}
	209
	210	static void cmd646_reset(void *opaque)
	211	{
	212	PCIIDEState *d = opaque;
	213	unsigned int i;
	214
4a643563 BS	215	for (i = 0; i < 2; i++) {
4a643563 BS	216	ide_bus_reset(&d->bus[i]);
4a643563	217	}
4c3df0ec JQ	218	}
4c3df0ec JQ	219
1d113ef8 MCA	220	static uint32_t cmd646_pci_config_read(PCIDevice *d,
	221	uint32_t address, int len)
	222	{
	223	return pci_default_read_config(d, address, len);
	224	}
	225
	226	static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
	227	int l)
	228	{
	229	uint32_t i;
	230
	231	pci_default_write_config(d, addr, val, l);
	232
	233	for (i = addr; i < addr + l; i++) {
	234	switch (i) {
271dddd1 MCA	235	case CFR:
	236	case ARTTIM23:
	237	cmd646_update_udma_interrupts(d);
	238	break;
1d113ef8 MCA	239	case MRDMODE:
	240	cmd646_update_dma_interrupts(d);
	241	break;
	242	}
	243	}
	244
	245	cmd646_update_irq(d);
	246	}
	247
4c3df0ec	248	/* CMD646 PCI IDE controller */
9af21dbe	249	static void pci_cmd646_ide_realize(PCIDevice dev, Error *errp)
4c3df0ec	250	{
f6c11d56 AF	251	PCIIDEState *d = PCI_IDE(dev);
f6c11d56 AF	252	uint8_t *pci_conf = dev->config;
4c3df0ec	253	qemu_irq *irq;
61d9d6b0	254	int i;
4c3df0ec	255
409570a7	256	pci_conf[PCI_CLASS_PROG] = 0x8f;
4c3df0ec	257
58f16a7b	258	pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
4c3df0ec JQ	259	if (d->secondary) {
4c3df0ec JQ	260	/* XXX: if not enabled, really disable the seconday IDE controller */
58f16a7b	261	pci_conf[CNTRL] \|= CNTRL_EN_CH1; /* enable IDE1 */
4c3df0ec JQ	262	}
4c3df0ec JQ	263
1d113ef8	264	/* Set write-to-clear interrupt bits */
271dddd1 MCA	265	dev->wmask[CFR] = 0x0;
	266	dev->w1cmask[CFR] = CFR_INTR_CH0;
	267	dev->wmask[ARTTIM23] = 0x0;
	268	dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
1d113ef8 MCA	269	dev->wmask[MRDMODE] = 0x0;
	270	dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1;
	271
8ac98d1a BZ	272	memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
	273	&d->bus[0], "cmd646-data0", 8);
	274	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
	275
	276	memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
	277	&d->bus[0], "cmd646-cmd0", 4);
	278	pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
	279
	280	memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
	281	&d->bus[1], "cmd646-data1", 8);
	282	pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
	283
	284	memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
	285	&d->bus[1], "cmd646-cmd1", 4);
	286	pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
	287
a9deb8c6	288	bmdma_setup_bar(d);
e824b2cc	289	pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	290
409570a7 MT	291	/* TODO: RST# value should be 0 */
409570a7 MT	292	pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
4c3df0ec JQ	293
4c3df0ec JQ	294	irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
61d9d6b0	295	for (i = 0; i < 2; i++) {
c6baf942	296	ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
61d9d6b0 SH	297	ide_init2(&d->bus[i], irq[i]);
61d9d6b0 SH	298
a9deb8c6	299	bmdma_init(&d->bus[i], &d->bmdma[i], d);
f56b18c0	300	d->bmdma[i].bus = &d->bus[i];
f878c916	301	ide_register_restart_cb(&d->bus[i]);
61d9d6b0	302	}
f5f72e8f	303	g_free(irq);
4c3df0ec	304
f6c11d56	305	vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
4c3df0ec	306	qemu_register_reset(cmd646_reset, d);
4c3df0ec JQ	307	}
4c3df0ec JQ	308
f90c2bcd	309	static void pci_cmd646_ide_exitfn(PCIDevice *dev)
a9deb8c6	310	{
f6c11d56	311	PCIIDEState *d = PCI_IDE(dev);
a9deb8c6 AK	312	unsigned i;
	313
	314	for (i = 0; i < 2; ++i) {
	315	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
a9deb8c6	316	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
a9deb8c6	317	}
a9deb8c6 AK	318	}
a9deb8c6 AK	319
4c3df0ec JQ	320	void pci_cmd646_ide_init(PCIBus bus, DriveInfo *hd_table,
	321	int secondary_ide_enabled)
	322	{
	323	PCIDevice *dev;
	324
556cd098	325	dev = pci_create(bus, -1, "cmd646-ide");
4c3df0ec JQ	326	qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
	327	qdev_init_nofail(&dev->qdev);
	328
	329	pci_ide_create_devs(dev, hd_table);
	330	}
	331
40021f08 AL	332	static Property cmd646_ide_properties[] = {
	333	DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
	334	DEFINE_PROP_END_OF_LIST(),
	335	};
	336
	337	static void cmd646_ide_class_init(ObjectClass klass, void data)
	338	{
39bffca2	339	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	340	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	341
9af21dbe	342	k->realize = pci_cmd646_ide_realize;
40021f08 AL	343	k->exit = pci_cmd646_ide_exitfn;
	344	k->vendor_id = PCI_VENDOR_ID_CMD;
	345	k->device_id = PCI_DEVICE_ID_CMD_646;
	346	k->revision = 0x07;
	347	k->class_id = PCI_CLASS_STORAGE_IDE;
1d113ef8 MCA	348	k->config_read = cmd646_pci_config_read;
1d113ef8 MCA	349	k->config_write = cmd646_pci_config_write;
39bffca2	350	dc->props = cmd646_ide_properties;
74623e73	351	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
40021f08 AL	352	}
40021f08 AL	353
8c43a6f0	354	static const TypeInfo cmd646_ide_info = {
39bffca2	355	.name = "cmd646-ide",
f6c11d56	356	.parent = TYPE_PCI_IDE,
39bffca2	357	.class_init = cmd646_ide_class_init,
4c3df0ec JQ	358	};
4c3df0ec JQ	359
83f7d43a	360	static void cmd646_ide_register_types(void)
4c3df0ec	361	{
39bffca2	362	type_register_static(&cmd646_ide_info);
4c3df0ec	363	}
83f7d43a AF	364
83f7d43a AF	365	type_init(cmd646_ide_register_types)