[qemu.git] / hw / spapr_hcall.c

#include "sysemu.h"
#include "cpu.h"
#include "qemu-char.h"
#include "sysemu.h"
#include "qemu-char.h"
#include "helper_regs.h"
#include "hw/spapr.h"

#define HPTES_PER_GROUP 8

#define HPTE_V_SSIZE_SHIFT      62
#define HPTE_V_AVPN_SHIFT       7
#define HPTE_V_AVPN             0x3fffffffffffff80ULL
#define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
#define HPTE_V_COMPARE(x, y)    (!(((x) ^ (y)) & 0xffffffffffffff80UL))
#define HPTE_V_BOLTED           0x0000000000000010ULL
#define HPTE_V_LOCK             0x0000000000000008ULL
#define HPTE_V_LARGE            0x0000000000000004ULL
#define HPTE_V_SECONDARY        0x0000000000000002ULL
#define HPTE_V_VALID            0x0000000000000001ULL

#define HPTE_R_PP0              0x8000000000000000ULL
#define HPTE_R_TS               0x4000000000000000ULL
#define HPTE_R_KEY_HI           0x3000000000000000ULL
#define HPTE_R_RPN_SHIFT        12
#define HPTE_R_RPN              0x3ffffffffffff000ULL
#define HPTE_R_FLAGS            0x00000000000003ffULL
#define HPTE_R_PP               0x0000000000000003ULL
#define HPTE_R_N                0x0000000000000004ULL
#define HPTE_R_G                0x0000000000000008ULL
#define HPTE_R_M                0x0000000000000010ULL
#define HPTE_R_I                0x0000000000000020ULL
#define HPTE_R_W                0x0000000000000040ULL
#define HPTE_R_WIMG             0x0000000000000078ULL
#define HPTE_R_C                0x0000000000000080ULL
#define HPTE_R_R                0x0000000000000100ULL
#define HPTE_R_KEY_LO           0x0000000000000e00ULL

#define HPTE_V_1TB_SEG          0x4000000000000000ULL
#define HPTE_V_VRMA_MASK        0x4001ffffff000000ULL

static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
                                     target_ulong pte_index)
{
    target_ulong rb, va_low;

    rb = (v & ~0x7fULL) << 16; /* AVA field */
    va_low = pte_index >> 3;
    if (v & HPTE_V_SECONDARY) {
        va_low = ~va_low;
    }
    /* xor vsid from AVA */
    if (!(v & HPTE_V_1TB_SEG)) {
        va_low ^= v >> 12;
    } else {
        va_low ^= v >> 24;
    }
    va_low &= 0x7ff;
    if (v & HPTE_V_LARGE) {
        rb |= 1;                         /* L field */
#if 0 /* Disable that P7 specific bit for now */
        if (r & 0xff000) {
            /* non-16MB large page, must be 64k */
            /* (masks depend on page size) */
            rb |= 0x1000;                /* page encoding in LP field */
            rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
            rb |= (va_low & 0xfe);       /* AVAL field */
        }
#endif
    } else {
        /* 4kB page */
        rb |= (va_low & 0x7ff) << 12;   /* remaining 11b of AVA */
    }
    rb |= (v >> 54) & 0x300;            /* B field */
    return rb;
}

static target_ulong h_enter(CPUPPCState *env, sPAPREnvironment *spapr,
                            target_ulong opcode, target_ulong *args)
{
    target_ulong flags = args[0];
    target_ulong pte_index = args[1];
    target_ulong pteh = args[2];
    target_ulong ptel = args[3];
    target_ulong page_shift = 12;
    target_ulong raddr;
    target_ulong i;
    uint8_t *hpte;

    /* only handle 4k and 16M pages for now */
    if (pteh & HPTE_V_LARGE) {
#if 0 /* We don't support 64k pages yet */
        if ((ptel & 0xf000) == 0x1000) {
            /* 64k page */
        } else
#endif
        if ((ptel & 0xff000) == 0) {
            /* 16M page */
            page_shift = 24;
            /* lowest AVA bit must be 0 for 16M pages */
            if (pteh & 0x80) {
                return H_PARAMETER;
            }
        } else {
            return H_PARAMETER;
        }
    }

    raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1);

    if (raddr < spapr->ram_limit) {
        /* Regular RAM - should have WIMG=0010 */
        if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
            return H_PARAMETER;
        }
    } else {
        /* Looks like an IO address */
        /* FIXME: What WIMG combinations could be sensible for IO?
         * For now we allow WIMG=010x, but are there others? */
        /* FIXME: Should we check against registered IO addresses? */
        if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
            return H_PARAMETER;
        }
    }

    pteh &= ~0x60ULL;

    if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
        return H_PARAMETER;
    }
    if (likely((flags & H_EXACT) == 0)) {
        pte_index &= ~7ULL;
        hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
        for (i = 0; ; ++i) {
            if (i == 8) {
                return H_PTEG_FULL;
            }
            if ((ldq_p(hpte) & HPTE_V_VALID) == 0) {
                break;
            }
            hpte += HASH_PTE_SIZE_64;
        }
    } else {
        i = 0;
        hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
        if (ldq_p(hpte) & HPTE_V_VALID) {
            return H_PTEG_FULL;
        }
    }
    stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
    /* eieio();  FIXME: need some sort of barrier for smp? */
    stq_p(hpte, pteh);

    args[0] = pte_index + i;
    return H_SUCCESS;
}

enum {
    REMOVE_SUCCESS = 0,
    REMOVE_NOT_FOUND = 1,
    REMOVE_PARM = 2,
    REMOVE_HW = 3,
};

static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
                                target_ulong avpn,
                                target_ulong flags,
                                target_ulong *vp, target_ulong *rp)
{
    uint8_t *hpte;
    target_ulong v, r, rb;

    if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
        return REMOVE_PARM;
    }

    hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64);

    v = ldq_p(hpte);
    r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));

    if ((v & HPTE_V_VALID) == 0 ||
        ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
        ((flags & H_ANDCOND) && (v & avpn) != 0)) {
        return REMOVE_NOT_FOUND;
    }
    *vp = v;
    *rp = r;
    stq_p(hpte, 0);
    rb = compute_tlbie_rb(v, r, ptex);
    ppc_tlb_invalidate_one(env, rb);
    return REMOVE_SUCCESS;
}

static target_ulong h_remove(CPUPPCState *env, sPAPREnvironment *spapr,
                             target_ulong opcode, target_ulong *args)
{
    target_ulong flags = args[0];
    target_ulong pte_index = args[1];
    target_ulong avpn = args[2];
    int ret;

    ret = remove_hpte(env, pte_index, avpn, flags,
                      &args[0], &args[1]);

    switch (ret) {
    case REMOVE_SUCCESS:
        return H_SUCCESS;

    case REMOVE_NOT_FOUND:
        return H_NOT_FOUND;

    case REMOVE_PARM:
        return H_PARAMETER;

    case REMOVE_HW:
        return H_HARDWARE;
    }

    assert(0);
}

#define H_BULK_REMOVE_TYPE             0xc000000000000000ULL
#define   H_BULK_REMOVE_REQUEST        0x4000000000000000ULL
#define   H_BULK_REMOVE_RESPONSE       0x8000000000000000ULL
#define   H_BULK_REMOVE_END            0xc000000000000000ULL
#define H_BULK_REMOVE_CODE             0x3000000000000000ULL
#define   H_BULK_REMOVE_SUCCESS        0x0000000000000000ULL
#define   H_BULK_REMOVE_NOT_FOUND      0x1000000000000000ULL
#define   H_BULK_REMOVE_PARM           0x2000000000000000ULL
#define   H_BULK_REMOVE_HW             0x3000000000000000ULL
#define H_BULK_REMOVE_RC               0x0c00000000000000ULL
#define H_BULK_REMOVE_FLAGS            0x0300000000000000ULL
#define   H_BULK_REMOVE_ABSOLUTE       0x0000000000000000ULL
#define   H_BULK_REMOVE_ANDCOND        0x0100000000000000ULL
#define   H_BULK_REMOVE_AVPN           0x0200000000000000ULL
#define H_BULK_REMOVE_PTEX             0x00ffffffffffffffULL

#define H_BULK_REMOVE_MAX_BATCH        4

static target_ulong h_bulk_remove(CPUPPCState *env, sPAPREnvironment *spapr,
                                  target_ulong opcode, target_ulong *args)
{
    int i;

    for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
        target_ulong *tsh = &args[i*2];
        target_ulong tsl = args[i*2 + 1];
        target_ulong v, r, ret;

        if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
            break;
        } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
            return H_PARAMETER;
        }

        *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
        *tsh |= H_BULK_REMOVE_RESPONSE;

        if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
            *tsh |= H_BULK_REMOVE_PARM;
            return H_PARAMETER;
        }

        ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl,
                          (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
                          &v, &r);

        *tsh |= ret << 60;

        switch (ret) {
        case REMOVE_SUCCESS:
            *tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43;
            break;

        case REMOVE_PARM:
            return H_PARAMETER;

        case REMOVE_HW:
            return H_HARDWARE;
        }
    }

    return H_SUCCESS;
}

static target_ulong h_protect(CPUPPCState *env, sPAPREnvironment *spapr,
                              target_ulong opcode, target_ulong *args)
{
    target_ulong flags = args[0];
    target_ulong pte_index = args[1];
    target_ulong avpn = args[2];
    uint8_t *hpte;
    target_ulong v, r, rb;

    if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
        return H_PARAMETER;
    }

    hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);

    v = ldq_p(hpte);
    r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));

    if ((v & HPTE_V_VALID) == 0 ||
        ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
        return H_NOT_FOUND;
    }

    r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
           HPTE_R_KEY_HI | HPTE_R_KEY_LO);
    r |= (flags << 55) & HPTE_R_PP0;
    r |= (flags << 48) & HPTE_R_KEY_HI;
    r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
    rb = compute_tlbie_rb(v, r, pte_index);
    stq_p(hpte, v & ~HPTE_V_VALID);
    ppc_tlb_invalidate_one(env, rb);
    stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
    /* Don't need a memory barrier, due to qemu's global lock */
    stq_p(hpte, v);
    return H_SUCCESS;
}

static target_ulong h_set_dabr(CPUPPCState *env, sPAPREnvironment *spapr,
                               target_ulong opcode, target_ulong *args)
{
    /* FIXME: actually implement this */
    return H_HARDWARE;
}

#define FLAGS_REGISTER_VPA         0x0000200000000000ULL
#define FLAGS_REGISTER_DTL         0x0000400000000000ULL
#define FLAGS_REGISTER_SLBSHADOW   0x0000600000000000ULL
#define FLAGS_DEREGISTER_VPA       0x0000a00000000000ULL
#define FLAGS_DEREGISTER_DTL       0x0000c00000000000ULL
#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL

#define VPA_MIN_SIZE           640
#define VPA_SIZE_OFFSET        0x4
#define VPA_SHARED_PROC_OFFSET 0x9
#define VPA_SHARED_PROC_VAL    0x2

static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
{
    uint16_t size;
    uint8_t tmp;

    if (vpa == 0) {
        hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
        return H_HARDWARE;
    }

    if (vpa % env->dcache_line_size) {
        return H_PARAMETER;
    }
    /* FIXME: bounds check the address */

    size = lduw_be_phys(vpa + 0x4);

    if (size < VPA_MIN_SIZE) {
        return H_PARAMETER;
    }

    /* VPA is not allowed to cross a page boundary */
    if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
        return H_PARAMETER;
    }

    env->vpa = vpa;

    tmp = ldub_phys(env->vpa + VPA_SHARED_PROC_OFFSET);
    tmp |= VPA_SHARED_PROC_VAL;
    stb_phys(env->vpa + VPA_SHARED_PROC_OFFSET, tmp);

    return H_SUCCESS;
}

static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
{
    if (env->slb_shadow) {
        return H_RESOURCE;
    }

    if (env->dispatch_trace_log) {
        return H_RESOURCE;
    }

    env->vpa = 0;
    return H_SUCCESS;
}

static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
{
    uint32_t size;

    if (addr == 0) {
        hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
        return H_HARDWARE;
    }

    size = ldl_be_phys(addr + 0x4);
    if (size < 0x8) {
        return H_PARAMETER;
    }

    if ((addr / 4096) != ((addr + size - 1) / 4096)) {
        return H_PARAMETER;
    }

    if (!env->vpa) {
        return H_RESOURCE;
    }

    env->slb_shadow = addr;

    return H_SUCCESS;
}

static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
{
    env->slb_shadow = 0;
    return H_SUCCESS;
}

static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
{
    uint32_t size;

    if (addr == 0) {
        hcall_dprintf("Can't cope with DTL at logical 0\n");
        return H_HARDWARE;
    }

    size = ldl_be_phys(addr + 0x4);

    if (size < 48) {
        return H_PARAMETER;
    }

    if (!env->vpa) {
        return H_RESOURCE;
    }

    env->dispatch_trace_log = addr;
    env->dtl_size = size;

    return H_SUCCESS;
}

static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
{
    env->dispatch_trace_log = 0;
    env->dtl_size = 0;

    return H_SUCCESS;
}

static target_ulong h_register_vpa(CPUPPCState *env, sPAPREnvironment *spapr,
                                   target_ulong opcode, target_ulong *args)
{
    target_ulong flags = args[0];
    target_ulong procno = args[1];
    target_ulong vpa = args[2];
    target_ulong ret = H_PARAMETER;
    CPUPPCState *tenv;

    for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
        if (tenv->cpu_index == procno) {
            break;
        }
    }

    if (!tenv) {
        return H_PARAMETER;
    }

    switch (flags) {
    case FLAGS_REGISTER_VPA:
        ret = register_vpa(tenv, vpa);
        break;

    case FLAGS_DEREGISTER_VPA:
        ret = deregister_vpa(tenv, vpa);
        break;

    case FLAGS_REGISTER_SLBSHADOW:
        ret = register_slb_shadow(tenv, vpa);
        break;

    case FLAGS_DEREGISTER_SLBSHADOW:
        ret = deregister_slb_shadow(tenv, vpa);
        break;

    case FLAGS_REGISTER_DTL:
        ret = register_dtl(tenv, vpa);
        break;

    case FLAGS_DEREGISTER_DTL:
        ret = deregister_dtl(tenv, vpa);
        break;
    }

    return ret;
}

static target_ulong h_cede(CPUPPCState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    env->msr |= (1ULL << MSR_EE);
    hreg_compute_hflags(env);
    if (!cpu_has_work(env)) {
        env->halted = 1;
        env->exception_index = EXCP_HLT;
        env->exit_request = 1;
    }
    return H_SUCCESS;
}

static target_ulong h_rtas(CPUPPCState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong rtas_r3 = args[0];
    uint32_t token = ldl_be_phys(rtas_r3);
    uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
    uint32_t nret = ldl_be_phys(rtas_r3 + 8);

    return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12,
                           nret, rtas_r3 + 12 + 4*nargs);
}

static target_ulong h_logical_load(CPUPPCState *env, sPAPREnvironment *spapr,
                                   target_ulong opcode, target_ulong *args)
{
    target_ulong size = args[0];
    target_ulong addr = args[1];

    switch (size) {
    case 1:
        args[0] = ldub_phys(addr);
        return H_SUCCESS;
    case 2:
        args[0] = lduw_phys(addr);
        return H_SUCCESS;
    case 4:
        args[0] = ldl_phys(addr);
        return H_SUCCESS;
    case 8:
        args[0] = ldq_phys(addr);
        return H_SUCCESS;
    }
    return H_PARAMETER;
}

static target_ulong h_logical_store(CPUPPCState *env, sPAPREnvironment *spapr,
                                    target_ulong opcode, target_ulong *args)
{
    target_ulong size = args[0];
    target_ulong addr = args[1];
    target_ulong val  = args[2];

    switch (size) {
    case 1:
        stb_phys(addr, val);
        return H_SUCCESS;
    case 2:
        stw_phys(addr, val);
        return H_SUCCESS;
    case 4:
        stl_phys(addr, val);
        return H_SUCCESS;
    case 8:
        stq_phys(addr, val);
        return H_SUCCESS;
    }
    return H_PARAMETER;
}

static target_ulong h_logical_memop(CPUPPCState *env, sPAPREnvironment *spapr,
                                    target_ulong opcode, target_ulong *args)
{
    target_ulong dst   = args[0]; /* Destination address */
    target_ulong src   = args[1]; /* Source address */
    target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
    target_ulong count = args[3]; /* Element count */
    target_ulong op    = args[4]; /* 0 = copy, 1 = invert */
    uint64_t tmp;
    unsigned int mask = (1 << esize) - 1;
    int step = 1 << esize;

    if (count > 0x80000000) {
        return H_PARAMETER;
    }

    if ((dst & mask) || (src & mask) || (op > 1)) {
        return H_PARAMETER;
    }

    if (dst >= src && dst < (src + (count << esize))) {
            dst = dst + ((count - 1) << esize);
            src = src + ((count - 1) << esize);
            step = -step;
    }

    while (count--) {
        switch (esize) {
        case 0:
            tmp = ldub_phys(src);
            break;
        case 1:
            tmp = lduw_phys(src);
            break;
        case 2:
            tmp = ldl_phys(src);
            break;
        case 3:
            tmp = ldq_phys(src);
            break;
        default:
            return H_PARAMETER;
        }
        if (op == 1) {
            tmp = ~tmp;
        }
        switch (esize) {
        case 0:
            stb_phys(dst, tmp);
            break;
        case 1:
            stw_phys(dst, tmp);
            break;
        case 2:
            stl_phys(dst, tmp);
            break;
        case 3:
            stq_phys(dst, tmp);
            break;
        }
        dst = dst + step;
        src = src + step;
    }

    return H_SUCCESS;
}

static target_ulong h_logical_icbi(CPUPPCState *env, sPAPREnvironment *spapr,
                                   target_ulong opcode, target_ulong *args)
{
    /* Nothing to do on emulation, KVM will trap this in the kernel */
    return H_SUCCESS;
}

static target_ulong h_logical_dcbf(CPUPPCState *env, sPAPREnvironment *spapr,
                                   target_ulong opcode, target_ulong *args)
{
    /* Nothing to do on emulation, KVM will trap this in the kernel */
    return H_SUCCESS;
}

static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];

void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
{
    spapr_hcall_fn *slot;

    if (opcode <= MAX_HCALL_OPCODE) {
        assert((opcode & 0x3) == 0);

        slot = &papr_hypercall_table[opcode / 4];
    } else {
        assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));


        slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
    }

    assert(!(*slot) || (fn == *slot));
    *slot = fn;
}

target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode,
                             target_ulong *args)
{
    if ((opcode <= MAX_HCALL_OPCODE)
        && ((opcode & 0x3) == 0)) {
        spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];

        if (fn) {
            return fn(env, spapr, opcode, args);
        }
    } else if ((opcode >= KVMPPC_HCALL_BASE) &&
               (opcode <= KVMPPC_HCALL_MAX)) {
        spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];

        if (fn) {
            return fn(env, spapr, opcode, args);
        }
    }

    hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
    return H_FUNCTION;
}

static void hypercall_register_types(void)
{
    /* hcall-pft */
    spapr_register_hypercall(H_ENTER, h_enter);
    spapr_register_hypercall(H_REMOVE, h_remove);
    spapr_register_hypercall(H_PROTECT, h_protect);

    /* hcall-bulk */
    spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);

    /* hcall-dabr */
    spapr_register_hypercall(H_SET_DABR, h_set_dabr);

    /* hcall-splpar */
    spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
    spapr_register_hypercall(H_CEDE, h_cede);

    /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
     * here between the "CI" and the "CACHE" variants, they will use whatever
     * mapping attributes qemu is using. When using KVM, the kernel will
     * enforce the attributes more strongly
     */
    spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
    spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
    spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
    spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
    spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
    spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
    spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);

    /* qemu/KVM-PPC specific hcalls */
    spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
}

type_init(hypercall_register_types)
Commit	Line	Data
9fdf0c29 DG	1	#include "sysemu.h"
	2	#include "cpu.h"
	3	#include "qemu-char.h"
f43e3525 DG	4	#include "sysemu.h"
f43e3525 DG	5	#include "qemu-char.h"
ed120055	6	#include "helper_regs.h"
9fdf0c29 DG	7	#include "hw/spapr.h"
9fdf0c29 DG	8
f43e3525 DG	9	#define HPTES_PER_GROUP 8
	10
	11	#define HPTE_V_SSIZE_SHIFT 62
	12	#define HPTE_V_AVPN_SHIFT 7
	13	#define HPTE_V_AVPN 0x3fffffffffffff80ULL
	14	#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
	15	#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
	16	#define HPTE_V_BOLTED 0x0000000000000010ULL
	17	#define HPTE_V_LOCK 0x0000000000000008ULL
	18	#define HPTE_V_LARGE 0x0000000000000004ULL
	19	#define HPTE_V_SECONDARY 0x0000000000000002ULL
	20	#define HPTE_V_VALID 0x0000000000000001ULL
	21
	22	#define HPTE_R_PP0 0x8000000000000000ULL
	23	#define HPTE_R_TS 0x4000000000000000ULL
	24	#define HPTE_R_KEY_HI 0x3000000000000000ULL
	25	#define HPTE_R_RPN_SHIFT 12
	26	#define HPTE_R_RPN 0x3ffffffffffff000ULL
	27	#define HPTE_R_FLAGS 0x00000000000003ffULL
	28	#define HPTE_R_PP 0x0000000000000003ULL
	29	#define HPTE_R_N 0x0000000000000004ULL
	30	#define HPTE_R_G 0x0000000000000008ULL
	31	#define HPTE_R_M 0x0000000000000010ULL
	32	#define HPTE_R_I 0x0000000000000020ULL
	33	#define HPTE_R_W 0x0000000000000040ULL
	34	#define HPTE_R_WIMG 0x0000000000000078ULL
	35	#define HPTE_R_C 0x0000000000000080ULL
	36	#define HPTE_R_R 0x0000000000000100ULL
	37	#define HPTE_R_KEY_LO 0x0000000000000e00ULL
	38
	39	#define HPTE_V_1TB_SEG 0x4000000000000000ULL
	40	#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
	41
f43e3525 DG	42	static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
	43	target_ulong pte_index)
	44	{
	45	target_ulong rb, va_low;
	46
	47	rb = (v & ~0x7fULL) << 16; /* AVA field */
	48	va_low = pte_index >> 3;
	49	if (v & HPTE_V_SECONDARY) {
	50	va_low = ~va_low;
	51	}
	52	/* xor vsid from AVA */
	53	if (!(v & HPTE_V_1TB_SEG)) {
	54	va_low ^= v >> 12;
	55	} else {
	56	va_low ^= v >> 24;
	57	}
	58	va_low &= 0x7ff;
	59	if (v & HPTE_V_LARGE) {
	60	rb \|= 1; /* L field */
	61	#if 0 /* Disable that P7 specific bit for now */
	62	if (r & 0xff000) {
	63	/* non-16MB large page, must be 64k */
	64	/* (masks depend on page size) */
	65	rb \|= 0x1000; /* page encoding in LP field */
	66	rb \|= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
	67	rb \|= (va_low & 0xfe); /* AVAL field */
	68	}
	69	#endif
	70	} else {
	71	/* 4kB page */
	72	rb \|= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */
	73	}
	74	rb \|= (v >> 54) & 0x300; /* B field */
	75	return rb;
	76	}
	77
e2684c0b	78	static target_ulong h_enter(CPUPPCState env, sPAPREnvironment spapr,
f43e3525 DG	79	target_ulong opcode, target_ulong *args)
	80	{
	81	target_ulong flags = args[0];
	82	target_ulong pte_index = args[1];
	83	target_ulong pteh = args[2];
	84	target_ulong ptel = args[3];
f73a2575 DG	85	target_ulong page_shift = 12;
f73a2575 DG	86	target_ulong raddr;
1235a9cf	87	target_ulong i;
f43e3525 DG	88	uint8_t *hpte;
	89
	90	/* only handle 4k and 16M pages for now */
f43e3525 DG	91	if (pteh & HPTE_V_LARGE) {
	92	#if 0 /* We don't support 64k pages yet */
	93	if ((ptel & 0xf000) == 0x1000) {
	94	/* 64k page */
f43e3525 DG	95	} else
	96	#endif
	97	if ((ptel & 0xff000) == 0) {
	98	/* 16M page */
f73a2575	99	page_shift = 24;
f43e3525 DG	100	/* lowest AVA bit must be 0 for 16M pages */
	101	if (pteh & 0x80) {
	102	return H_PARAMETER;
	103	}
	104	} else {
	105	return H_PARAMETER;
	106	}
	107	}
	108
f73a2575	109	raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1);
f43e3525	110
f73a2575 DG	111	if (raddr < spapr->ram_limit) {
	112	/* Regular RAM - should have WIMG=0010 */
	113	if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
	114	return H_PARAMETER;
	115	}
	116	} else {
	117	/* Looks like an IO address */
	118	/* FIXME: What WIMG combinations could be sensible for IO?
	119	* For now we allow WIMG=010x, but are there others? */
	120	/* FIXME: Should we check against registered IO addresses? */
	121	if ((ptel & (HPTE_R_W \| HPTE_R_I \| HPTE_R_M)) != HPTE_R_I) {
	122	return H_PARAMETER;
	123	}
f43e3525	124	}
f73a2575	125
f43e3525 DG	126	pteh &= ~0x60ULL;
	127
	128	if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
	129	return H_PARAMETER;
	130	}
	131	if (likely((flags & H_EXACT) == 0)) {
	132	pte_index &= ~7ULL;
	133	hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
	134	for (i = 0; ; ++i) {
	135	if (i == 8) {
	136	return H_PTEG_FULL;
	137	}
35f9304d	138	if ((ldq_p(hpte) & HPTE_V_VALID) == 0) {
f43e3525 DG	139	break;
	140	}
	141	hpte += HASH_PTE_SIZE_64;
	142	}
	143	} else {
	144	i = 0;
	145	hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
35f9304d	146	if (ldq_p(hpte) & HPTE_V_VALID) {
f43e3525 DG	147	return H_PTEG_FULL;
	148	}
	149	}
	150	stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
	151	/* eieio(); FIXME: need some sort of barrier for smp? */
	152	stq_p(hpte, pteh);
	153
f43e3525 DG	154	args[0] = pte_index + i;
	155	return H_SUCCESS;
	156	}
	157
a3d0abae DG	158	enum {
	159	REMOVE_SUCCESS = 0,
	160	REMOVE_NOT_FOUND = 1,
	161	REMOVE_PARM = 2,
	162	REMOVE_HW = 3,
	163	};
	164
e2684c0b	165	static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
a3d0abae DG	166	target_ulong avpn,
	167	target_ulong flags,
	168	target_ulong vp, target_ulong rp)
f43e3525	169	{
f43e3525 DG	170	uint8_t *hpte;
	171	target_ulong v, r, rb;
	172
a3d0abae DG	173	if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
a3d0abae DG	174	return REMOVE_PARM;
f43e3525 DG	175	}
f43e3525 DG	176
a3d0abae	177	hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64);
f43e3525 DG	178
	179	v = ldq_p(hpte);
	180	r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
	181
	182	if ((v & HPTE_V_VALID) == 0 \|\|
	183	((flags & H_AVPN) && (v & ~0x7fULL) != avpn) \|\|
	184	((flags & H_ANDCOND) && (v & avpn) != 0)) {
a3d0abae	185	return REMOVE_NOT_FOUND;
f43e3525	186	}
35f9304d	187	*vp = v;
a3d0abae	188	*rp = r;
f43e3525	189	stq_p(hpte, 0);
a3d0abae	190	rb = compute_tlbie_rb(v, r, ptex);
f43e3525	191	ppc_tlb_invalidate_one(env, rb);
a3d0abae DG	192	return REMOVE_SUCCESS;
	193	}
	194
e2684c0b	195	static target_ulong h_remove(CPUPPCState env, sPAPREnvironment spapr,
a3d0abae DG	196	target_ulong opcode, target_ulong *args)
	197	{
	198	target_ulong flags = args[0];
	199	target_ulong pte_index = args[1];
	200	target_ulong avpn = args[2];
	201	int ret;
	202
	203	ret = remove_hpte(env, pte_index, avpn, flags,
	204	&args[0], &args[1]);
	205
	206	switch (ret) {
	207	case REMOVE_SUCCESS:
	208	return H_SUCCESS;
	209
	210	case REMOVE_NOT_FOUND:
	211	return H_NOT_FOUND;
	212
	213	case REMOVE_PARM:
	214	return H_PARAMETER;
	215
	216	case REMOVE_HW:
	217	return H_HARDWARE;
	218	}
	219
	220	assert(0);
	221	}
	222
	223	#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
	224	#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
	225	#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
	226	#define H_BULK_REMOVE_END 0xc000000000000000ULL
	227	#define H_BULK_REMOVE_CODE 0x3000000000000000ULL
	228	#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
	229	#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
	230	#define H_BULK_REMOVE_PARM 0x2000000000000000ULL
	231	#define H_BULK_REMOVE_HW 0x3000000000000000ULL
	232	#define H_BULK_REMOVE_RC 0x0c00000000000000ULL
	233	#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
	234	#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
	235	#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
	236	#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
	237	#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
	238
	239	#define H_BULK_REMOVE_MAX_BATCH 4
	240
e2684c0b	241	static target_ulong h_bulk_remove(CPUPPCState env, sPAPREnvironment spapr,
a3d0abae DG	242	target_ulong opcode, target_ulong *args)
	243	{
	244	int i;
	245
	246	for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
	247	target_ulong tsh = &args[i2];
	248	target_ulong tsl = args[i*2 + 1];
	249	target_ulong v, r, ret;
	250
	251	if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
	252	break;
	253	} else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
	254	return H_PARAMETER;
	255	}
	256
	257	*tsh &= H_BULK_REMOVE_PTEX \| H_BULK_REMOVE_FLAGS;
	258	*tsh \|= H_BULK_REMOVE_RESPONSE;
	259
	260	if ((tsh & H_BULK_REMOVE_ANDCOND) && (tsh & H_BULK_REMOVE_AVPN)) {
	261	*tsh \|= H_BULK_REMOVE_PARM;
	262	return H_PARAMETER;
	263	}
	264
	265	ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl,
	266	(*tsh & H_BULK_REMOVE_FLAGS) >> 26,
	267	&v, &r);
	268
	269	*tsh \|= ret << 60;
	270
	271	switch (ret) {
	272	case REMOVE_SUCCESS:
	273	*tsh \|= (r & (HPTE_R_C \| HPTE_R_R)) << 43;
	274	break;
	275
	276	case REMOVE_PARM:
	277	return H_PARAMETER;
	278
	279	case REMOVE_HW:
	280	return H_HARDWARE;
	281	}
	282	}
	283
f43e3525 DG	284	return H_SUCCESS;
	285	}
	286
e2684c0b	287	static target_ulong h_protect(CPUPPCState env, sPAPREnvironment spapr,
f43e3525 DG	288	target_ulong opcode, target_ulong *args)
	289	{
	290	target_ulong flags = args[0];
	291	target_ulong pte_index = args[1];
	292	target_ulong avpn = args[2];
	293	uint8_t *hpte;
	294	target_ulong v, r, rb;
	295
	296	if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
	297	return H_PARAMETER;
	298	}
	299
	300	hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
f43e3525 DG	301
	302	v = ldq_p(hpte);
	303	r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
	304
	305	if ((v & HPTE_V_VALID) == 0 \|\|
	306	((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
f43e3525 DG	307	return H_NOT_FOUND;
	308	}
	309
	310	r &= ~(HPTE_R_PP0 \| HPTE_R_PP \| HPTE_R_N \|
	311	HPTE_R_KEY_HI \| HPTE_R_KEY_LO);
	312	r \|= (flags << 55) & HPTE_R_PP0;
	313	r \|= (flags << 48) & HPTE_R_KEY_HI;
	314	r \|= flags & (HPTE_R_PP \| HPTE_R_N \| HPTE_R_KEY_LO);
	315	rb = compute_tlbie_rb(v, r, pte_index);
	316	stq_p(hpte, v & ~HPTE_V_VALID);
	317	ppc_tlb_invalidate_one(env, rb);
	318	stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
	319	/* Don't need a memory barrier, due to qemu's global lock */
35f9304d	320	stq_p(hpte, v);
f43e3525 DG	321	return H_SUCCESS;
	322	}
	323
e2684c0b	324	static target_ulong h_set_dabr(CPUPPCState env, sPAPREnvironment spapr,
821303f5 DG	325	target_ulong opcode, target_ulong *args)
	326	{
	327	/* FIXME: actually implement this */
	328	return H_HARDWARE;
	329	}
	330
ed120055 DG	331	#define FLAGS_REGISTER_VPA 0x0000200000000000ULL
	332	#define FLAGS_REGISTER_DTL 0x0000400000000000ULL
	333	#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL
	334	#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL
	335	#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL
	336	#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
	337
	338	#define VPA_MIN_SIZE 640
	339	#define VPA_SIZE_OFFSET 0x4
	340	#define VPA_SHARED_PROC_OFFSET 0x9
	341	#define VPA_SHARED_PROC_VAL 0x2
	342
e2684c0b	343	static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
ed120055 DG	344	{
	345	uint16_t size;
	346	uint8_t tmp;
	347
	348	if (vpa == 0) {
	349	hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
	350	return H_HARDWARE;
	351	}
	352
	353	if (vpa % env->dcache_line_size) {
	354	return H_PARAMETER;
	355	}
	356	/* FIXME: bounds check the address */
	357
06c46bba	358	size = lduw_be_phys(vpa + 0x4);
ed120055 DG	359
	360	if (size < VPA_MIN_SIZE) {
	361	return H_PARAMETER;
	362	}
	363
	364	/* VPA is not allowed to cross a page boundary */
	365	if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
	366	return H_PARAMETER;
	367	}
	368
	369	env->vpa = vpa;
	370
	371	tmp = ldub_phys(env->vpa + VPA_SHARED_PROC_OFFSET);
	372	tmp \|= VPA_SHARED_PROC_VAL;
	373	stb_phys(env->vpa + VPA_SHARED_PROC_OFFSET, tmp);
	374
	375	return H_SUCCESS;
	376	}
	377
e2684c0b	378	static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
ed120055 DG	379	{
	380	if (env->slb_shadow) {
	381	return H_RESOURCE;
	382	}
	383
	384	if (env->dispatch_trace_log) {
	385	return H_RESOURCE;
	386	}
	387
	388	env->vpa = 0;
	389	return H_SUCCESS;
	390	}
	391
e2684c0b	392	static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
ed120055 DG	393	{
	394	uint32_t size;
	395
	396	if (addr == 0) {
	397	hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
	398	return H_HARDWARE;
	399	}
	400
06c46bba	401	size = ldl_be_phys(addr + 0x4);
ed120055 DG	402	if (size < 0x8) {
	403	return H_PARAMETER;
	404	}
	405
	406	if ((addr / 4096) != ((addr + size - 1) / 4096)) {
	407	return H_PARAMETER;
	408	}
	409
	410	if (!env->vpa) {
	411	return H_RESOURCE;
	412	}
	413
	414	env->slb_shadow = addr;
	415
	416	return H_SUCCESS;
	417	}
	418
e2684c0b	419	static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
ed120055 DG	420	{
	421	env->slb_shadow = 0;
	422	return H_SUCCESS;
	423	}
	424
e2684c0b	425	static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
ed120055 DG	426	{
	427	uint32_t size;
	428
	429	if (addr == 0) {
	430	hcall_dprintf("Can't cope with DTL at logical 0\n");
	431	return H_HARDWARE;
	432	}
	433
06c46bba	434	size = ldl_be_phys(addr + 0x4);
ed120055 DG	435
	436	if (size < 48) {
	437	return H_PARAMETER;
	438	}
	439
	440	if (!env->vpa) {
	441	return H_RESOURCE;
	442	}
	443
	444	env->dispatch_trace_log = addr;
	445	env->dtl_size = size;
	446
	447	return H_SUCCESS;
	448	}
	449
73f7821b	450	static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
ed120055 DG	451	{
	452	env->dispatch_trace_log = 0;
	453	env->dtl_size = 0;
	454
	455	return H_SUCCESS;
	456	}
	457
e2684c0b	458	static target_ulong h_register_vpa(CPUPPCState env, sPAPREnvironment spapr,
ed120055 DG	459	target_ulong opcode, target_ulong *args)
	460	{
	461	target_ulong flags = args[0];
	462	target_ulong procno = args[1];
	463	target_ulong vpa = args[2];
	464	target_ulong ret = H_PARAMETER;
e2684c0b	465	CPUPPCState *tenv;
ed120055 DG	466
	467	for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
	468	if (tenv->cpu_index == procno) {
	469	break;
	470	}
	471	}
	472
	473	if (!tenv) {
	474	return H_PARAMETER;
	475	}
	476
	477	switch (flags) {
	478	case FLAGS_REGISTER_VPA:
	479	ret = register_vpa(tenv, vpa);
	480	break;
	481
	482	case FLAGS_DEREGISTER_VPA:
	483	ret = deregister_vpa(tenv, vpa);
	484	break;
	485
	486	case FLAGS_REGISTER_SLBSHADOW:
	487	ret = register_slb_shadow(tenv, vpa);
	488	break;
	489
	490	case FLAGS_DEREGISTER_SLBSHADOW:
	491	ret = deregister_slb_shadow(tenv, vpa);
	492	break;
	493
	494	case FLAGS_REGISTER_DTL:
	495	ret = register_dtl(tenv, vpa);
	496	break;
	497
	498	case FLAGS_DEREGISTER_DTL:
	499	ret = deregister_dtl(tenv, vpa);
	500	break;
	501	}
	502
	503	return ret;
	504	}
	505
e2684c0b	506	static target_ulong h_cede(CPUPPCState env, sPAPREnvironment spapr,
ed120055 DG	507	target_ulong opcode, target_ulong *args)
	508	{
	509	env->msr \|= (1ULL << MSR_EE);
	510	hreg_compute_hflags(env);
	511	if (!cpu_has_work(env)) {
	512	env->halted = 1;
1dd08894 DG	513	env->exception_index = EXCP_HLT;
1dd08894 DG	514	env->exit_request = 1;
ed120055 DG	515	}
	516	return H_SUCCESS;
	517	}
	518
e2684c0b	519	static target_ulong h_rtas(CPUPPCState env, sPAPREnvironment spapr,
39ac8455 DG	520	target_ulong opcode, target_ulong *args)
	521	{
	522	target_ulong rtas_r3 = args[0];
06c46bba AG	523	uint32_t token = ldl_be_phys(rtas_r3);
	524	uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
	525	uint32_t nret = ldl_be_phys(rtas_r3 + 8);
39ac8455 DG	526
	527	return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12,
	528	nret, rtas_r3 + 12 + 4*nargs);
	529	}
	530
e2684c0b	531	static target_ulong h_logical_load(CPUPPCState env, sPAPREnvironment spapr,
827200a2 DG	532	target_ulong opcode, target_ulong *args)
	533	{
	534	target_ulong size = args[0];
	535	target_ulong addr = args[1];
	536
	537	switch (size) {
	538	case 1:
	539	args[0] = ldub_phys(addr);
	540	return H_SUCCESS;
	541	case 2:
	542	args[0] = lduw_phys(addr);
	543	return H_SUCCESS;
	544	case 4:
	545	args[0] = ldl_phys(addr);
	546	return H_SUCCESS;
	547	case 8:
	548	args[0] = ldq_phys(addr);
	549	return H_SUCCESS;
	550	}
	551	return H_PARAMETER;
	552	}
	553
e2684c0b	554	static target_ulong h_logical_store(CPUPPCState env, sPAPREnvironment spapr,
827200a2 DG	555	target_ulong opcode, target_ulong *args)
	556	{
	557	target_ulong size = args[0];
	558	target_ulong addr = args[1];
	559	target_ulong val = args[2];
	560
	561	switch (size) {
	562	case 1:
	563	stb_phys(addr, val);
	564	return H_SUCCESS;
	565	case 2:
	566	stw_phys(addr, val);
	567	return H_SUCCESS;
	568	case 4:
	569	stl_phys(addr, val);
	570	return H_SUCCESS;
	571	case 8:
	572	stq_phys(addr, val);
	573	return H_SUCCESS;
	574	}
	575	return H_PARAMETER;
	576	}
	577
c73e3771 BH	578	static target_ulong h_logical_memop(CPUPPCState env, sPAPREnvironment spapr,
	579	target_ulong opcode, target_ulong *args)
	580	{
	581	target_ulong dst = args[0]; /* Destination address */
	582	target_ulong src = args[1]; /* Source address */
	583	target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
	584	target_ulong count = args[3]; /* Element count */
	585	target_ulong op = args[4]; /* 0 = copy, 1 = invert */
	586	uint64_t tmp;
	587	unsigned int mask = (1 << esize) - 1;
	588	int step = 1 << esize;
	589
	590	if (count > 0x80000000) {
	591	return H_PARAMETER;
	592	}
	593
	594	if ((dst & mask) \|\| (src & mask) \|\| (op > 1)) {
	595	return H_PARAMETER;
	596	}
	597
	598	if (dst >= src && dst < (src + (count << esize))) {
	599	dst = dst + ((count - 1) << esize);
	600	src = src + ((count - 1) << esize);
	601	step = -step;
	602	}
	603
	604	while (count--) {
	605	switch (esize) {
	606	case 0:
	607	tmp = ldub_phys(src);
	608	break;
	609	case 1:
	610	tmp = lduw_phys(src);
	611	break;
	612	case 2:
	613	tmp = ldl_phys(src);
	614	break;
	615	case 3:
	616	tmp = ldq_phys(src);
	617	break;
	618	default:
	619	return H_PARAMETER;
	620	}
	621	if (op == 1) {
	622	tmp = ~tmp;
	623	}
	624	switch (esize) {
	625	case 0:
	626	stb_phys(dst, tmp);
	627	break;
	628	case 1:
	629	stw_phys(dst, tmp);
	630	break;
	631	case 2:
	632	stl_phys(dst, tmp);
	633	break;
	634	case 3:
	635	stq_phys(dst, tmp);
	636	break;
	637	}
	638	dst = dst + step;
	639	src = src + step;
	640	}
	641
642	return H_SUCCESS;
643	}
644
e2684c0b	645	static target_ulong h_logical_icbi(CPUPPCState env, sPAPREnvironment spapr,
827200a2 DG	646	target_ulong opcode, target_ulong *args)
	647	{
	648	/* Nothing to do on emulation, KVM will trap this in the kernel */
	649	return H_SUCCESS;
	650	}
	651
e2684c0b	652	static target_ulong h_logical_dcbf(CPUPPCState env, sPAPREnvironment spapr,
827200a2 DG	653	target_ulong opcode, target_ulong *args)
	654	{
	655	/* Nothing to do on emulation, KVM will trap this in the kernel */
	656	return H_SUCCESS;
	657	}
	658
7d7ba3fe DG	659	static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
7d7ba3fe DG	660	static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
9fdf0c29 DG	661
	662	void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
	663	{
39ac8455 DG	664	spapr_hcall_fn *slot;
	665
	666	if (opcode <= MAX_HCALL_OPCODE) {
	667	assert((opcode & 0x3) == 0);
9fdf0c29	668
39ac8455 DG	669	slot = &papr_hypercall_table[opcode / 4];
	670	} else {
	671	assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
9fdf0c29	672
9fdf0c29	673
39ac8455 DG	674	slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
39ac8455 DG	675	}
9fdf0c29	676
39ac8455 DG	677	assert(!(slot) \|\| (fn == slot));
39ac8455 DG	678	*slot = fn;
9fdf0c29 DG	679	}
9fdf0c29 DG	680
e2684c0b	681	target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode,
9fdf0c29 DG	682	target_ulong *args)
9fdf0c29 DG	683	{
9fdf0c29 DG	684	if ((opcode <= MAX_HCALL_OPCODE)
9fdf0c29 DG	685	&& ((opcode & 0x3) == 0)) {
39ac8455 DG	686	spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
	687
	688	if (fn) {
	689	return fn(env, spapr, opcode, args);
	690	}
	691	} else if ((opcode >= KVMPPC_HCALL_BASE) &&
	692	(opcode <= KVMPPC_HCALL_MAX)) {
	693	spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
9fdf0c29 DG	694
	695	if (fn) {
	696	return fn(env, spapr, opcode, args);
	697	}
	698	}
	699
	700	hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
	701	return H_FUNCTION;
	702	}
f43e3525	703
83f7d43a	704	static void hypercall_register_types(void)
f43e3525 DG	705	{
	706	/* hcall-pft */
	707	spapr_register_hypercall(H_ENTER, h_enter);
	708	spapr_register_hypercall(H_REMOVE, h_remove);
	709	spapr_register_hypercall(H_PROTECT, h_protect);
39ac8455	710
a3d0abae DG	711	/* hcall-bulk */
	712	spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
	713
821303f5 DG	714	/* hcall-dabr */
	715	spapr_register_hypercall(H_SET_DABR, h_set_dabr);
	716
ed120055 DG	717	/* hcall-splpar */
	718	spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
	719	spapr_register_hypercall(H_CEDE, h_cede);
	720
827200a2 DG	721	/* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
	722	* here between the "CI" and the "CACHE" variants, they will use whatever
	723	* mapping attributes qemu is using. When using KVM, the kernel will
	724	* enforce the attributes more strongly
	725	*/
	726	spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
	727	spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
	728	spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
	729	spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
	730	spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
	731	spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
c73e3771	732	spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
827200a2	733
39ac8455 DG	734	/* qemu/KVM-PPC specific hcalls */
39ac8455 DG	735	spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
f43e3525	736	}
83f7d43a AF	737
83f7d43a AF	738	type_init(hypercall_register_types)