[qemu.git] / hw / spapr_hcall.c

#include "sysemu.h"
#include "cpu.h"
#include "qemu-char.h"
#include "sysemu.h"
#include "qemu-char.h"
#include "exec-all.h"
#include "hw/spapr.h"

#define HPTES_PER_GROUP 8

#define HPTE_V_SSIZE_SHIFT      62
#define HPTE_V_AVPN_SHIFT       7
#define HPTE_V_AVPN             0x3fffffffffffff80ULL
#define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
#define HPTE_V_COMPARE(x, y)    (!(((x) ^ (y)) & 0xffffffffffffff80UL))
#define HPTE_V_BOLTED           0x0000000000000010ULL
#define HPTE_V_LOCK             0x0000000000000008ULL
#define HPTE_V_LARGE            0x0000000000000004ULL
#define HPTE_V_SECONDARY        0x0000000000000002ULL
#define HPTE_V_VALID            0x0000000000000001ULL

#define HPTE_R_PP0              0x8000000000000000ULL
#define HPTE_R_TS               0x4000000000000000ULL
#define HPTE_R_KEY_HI           0x3000000000000000ULL
#define HPTE_R_RPN_SHIFT        12
#define HPTE_R_RPN              0x3ffffffffffff000ULL
#define HPTE_R_FLAGS            0x00000000000003ffULL
#define HPTE_R_PP               0x0000000000000003ULL
#define HPTE_R_N                0x0000000000000004ULL
#define HPTE_R_G                0x0000000000000008ULL
#define HPTE_R_M                0x0000000000000010ULL
#define HPTE_R_I                0x0000000000000020ULL
#define HPTE_R_W                0x0000000000000040ULL
#define HPTE_R_WIMG             0x0000000000000078ULL
#define HPTE_R_C                0x0000000000000080ULL
#define HPTE_R_R                0x0000000000000100ULL
#define HPTE_R_KEY_LO           0x0000000000000e00ULL

#define HPTE_V_1TB_SEG          0x4000000000000000ULL
#define HPTE_V_VRMA_MASK        0x4001ffffff000000ULL

#define HPTE_V_HVLOCK           0x40ULL

static inline int lock_hpte(void *hpte, target_ulong bits)
{
    uint64_t pteh;

    pteh = ldq_p(hpte);

    /* We're protected by qemu's global lock here */
    if (pteh & bits) {
        return 0;
    }
    stq_p(hpte, pteh | HPTE_V_HVLOCK);
    return 1;
}

static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
                                     target_ulong pte_index)
{
    target_ulong rb, va_low;

    rb = (v & ~0x7fULL) << 16; /* AVA field */
    va_low = pte_index >> 3;
    if (v & HPTE_V_SECONDARY) {
        va_low = ~va_low;
    }
    /* xor vsid from AVA */
    if (!(v & HPTE_V_1TB_SEG)) {
        va_low ^= v >> 12;
    } else {
        va_low ^= v >> 24;
    }
    va_low &= 0x7ff;
    if (v & HPTE_V_LARGE) {
        rb |= 1;                         /* L field */
#if 0 /* Disable that P7 specific bit for now */
        if (r & 0xff000) {
            /* non-16MB large page, must be 64k */
            /* (masks depend on page size) */
            rb |= 0x1000;                /* page encoding in LP field */
            rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
            rb |= (va_low & 0xfe);       /* AVAL field */
        }
#endif
    } else {
        /* 4kB page */
        rb |= (va_low & 0x7ff) << 12;   /* remaining 11b of AVA */
    }
    rb |= (v >> 54) & 0x300;            /* B field */
    return rb;
}

static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr,
                            target_ulong opcode, target_ulong *args)
{
    target_ulong flags = args[0];
    target_ulong pte_index = args[1];
    target_ulong pteh = args[2];
    target_ulong ptel = args[3];
    target_ulong porder;
    target_ulong i, pa;
    uint8_t *hpte;

    /* only handle 4k and 16M pages for now */
    porder = 12;
    if (pteh & HPTE_V_LARGE) {
#if 0 /* We don't support 64k pages yet */
        if ((ptel & 0xf000) == 0x1000) {
            /* 64k page */
            porder = 16;
        } else
#endif
        if ((ptel & 0xff000) == 0) {
            /* 16M page */
            porder = 24;
            /* lowest AVA bit must be 0 for 16M pages */
            if (pteh & 0x80) {
                return H_PARAMETER;
            }
        } else {
            return H_PARAMETER;
        }
    }

    pa = ptel & HPTE_R_RPN;
    /* FIXME: bounds check the pa? */

    /* Check WIMG */
    if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
        return H_PARAMETER;
    }
    pteh &= ~0x60ULL;

    if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
        return H_PARAMETER;
    }
    if (likely((flags & H_EXACT) == 0)) {
        pte_index &= ~7ULL;
        hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
        for (i = 0; ; ++i) {
            if (i == 8) {
                return H_PTEG_FULL;
            }
            if (((ldq_p(hpte) & HPTE_V_VALID) == 0) &&
                lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
                break;
            }
            hpte += HASH_PTE_SIZE_64;
        }
    } else {
        i = 0;
        hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
        if (!lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
            return H_PTEG_FULL;
        }
    }
    stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
    /* eieio();  FIXME: need some sort of barrier for smp? */
    stq_p(hpte, pteh);

    assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
    args[0] = pte_index + i;
    return H_SUCCESS;
}

static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
                             target_ulong opcode, target_ulong *args)
{
    target_ulong flags = args[0];
    target_ulong pte_index = args[1];
    target_ulong avpn = args[2];
    uint8_t *hpte;
    target_ulong v, r, rb;

    if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
        return H_PARAMETER;
    }

    hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
    while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
        /* We have no real concurrency in qemu soft-emulation, so we
         * will never actually have a contested lock */
        assert(0);
    }

    v = ldq_p(hpte);
    r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));

    if ((v & HPTE_V_VALID) == 0 ||
        ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
        ((flags & H_ANDCOND) && (v & avpn) != 0)) {
        stq_p(hpte, v & ~HPTE_V_HVLOCK);
        assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
        return H_NOT_FOUND;
    }
    args[0] = v & ~HPTE_V_HVLOCK;
    args[1] = r;
    stq_p(hpte, 0);
    rb = compute_tlbie_rb(v, r, pte_index);
    ppc_tlb_invalidate_one(env, rb);
    assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
    return H_SUCCESS;
}

static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
                              target_ulong opcode, target_ulong *args)
{
    target_ulong flags = args[0];
    target_ulong pte_index = args[1];
    target_ulong avpn = args[2];
    uint8_t *hpte;
    target_ulong v, r, rb;

    if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
        return H_PARAMETER;
    }

    hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
    while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
        /* We have no real concurrency in qemu soft-emulation, so we
         * will never actually have a contested lock */
        assert(0);
    }

    v = ldq_p(hpte);
    r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));

    if ((v & HPTE_V_VALID) == 0 ||
        ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
        stq_p(hpte, v & ~HPTE_V_HVLOCK);
        assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
        return H_NOT_FOUND;
    }

    r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
           HPTE_R_KEY_HI | HPTE_R_KEY_LO);
    r |= (flags << 55) & HPTE_R_PP0;
    r |= (flags << 48) & HPTE_R_KEY_HI;
    r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
    rb = compute_tlbie_rb(v, r, pte_index);
    stq_p(hpte, v & ~HPTE_V_VALID);
    ppc_tlb_invalidate_one(env, rb);
    stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
    /* Don't need a memory barrier, due to qemu's global lock */
    stq_p(hpte, v & ~HPTE_V_HVLOCK);
    assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
    return H_SUCCESS;
}

static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong rtas_r3 = args[0];
    uint32_t token = ldl_phys(rtas_r3);
    uint32_t nargs = ldl_phys(rtas_r3 + 4);
    uint32_t nret = ldl_phys(rtas_r3 + 8);

    return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12,
                           nret, rtas_r3 + 12 + 4*nargs);
}

spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE];

void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
{
    spapr_hcall_fn *slot;

    if (opcode <= MAX_HCALL_OPCODE) {
        assert((opcode & 0x3) == 0);

        slot = &papr_hypercall_table[opcode / 4];
    } else {
        assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));


        slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
    }

    assert(!(*slot) || (fn == *slot));
    *slot = fn;
}

target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
                             target_ulong *args)
{
    if (msr_pr) {
        hcall_dprintf("Hypercall made with MSR[PR]=1\n");
        return H_PRIVILEGE;
    }

    if ((opcode <= MAX_HCALL_OPCODE)
        && ((opcode & 0x3) == 0)) {
        spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];

        if (fn) {
            return fn(env, spapr, opcode, args);
        }
    } else if ((opcode >= KVMPPC_HCALL_BASE) &&
               (opcode <= KVMPPC_HCALL_MAX)) {
        spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];

        if (fn) {
            return fn(env, spapr, opcode, args);
        }
    }

    hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
    return H_FUNCTION;
}

static void hypercall_init(void)
{
    /* hcall-pft */
    spapr_register_hypercall(H_ENTER, h_enter);
    spapr_register_hypercall(H_REMOVE, h_remove);
    spapr_register_hypercall(H_PROTECT, h_protect);

    /* qemu/KVM-PPC specific hcalls */
    spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
}
device_init(hypercall_init);
Commit	Line	Data
9fdf0c29 DG	1	#include "sysemu.h"
	2	#include "cpu.h"
	3	#include "qemu-char.h"
f43e3525 DG	4	#include "sysemu.h"
	5	#include "qemu-char.h"
	6	#include "exec-all.h"
9fdf0c29 DG	7	#include "hw/spapr.h"
9fdf0c29 DG	8
f43e3525 DG	9	#define HPTES_PER_GROUP 8
	10
	11	#define HPTE_V_SSIZE_SHIFT 62
	12	#define HPTE_V_AVPN_SHIFT 7
	13	#define HPTE_V_AVPN 0x3fffffffffffff80ULL
	14	#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
	15	#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
	16	#define HPTE_V_BOLTED 0x0000000000000010ULL
	17	#define HPTE_V_LOCK 0x0000000000000008ULL
	18	#define HPTE_V_LARGE 0x0000000000000004ULL
	19	#define HPTE_V_SECONDARY 0x0000000000000002ULL
	20	#define HPTE_V_VALID 0x0000000000000001ULL
	21
	22	#define HPTE_R_PP0 0x8000000000000000ULL
	23	#define HPTE_R_TS 0x4000000000000000ULL
	24	#define HPTE_R_KEY_HI 0x3000000000000000ULL
	25	#define HPTE_R_RPN_SHIFT 12
	26	#define HPTE_R_RPN 0x3ffffffffffff000ULL
	27	#define HPTE_R_FLAGS 0x00000000000003ffULL
	28	#define HPTE_R_PP 0x0000000000000003ULL
	29	#define HPTE_R_N 0x0000000000000004ULL
	30	#define HPTE_R_G 0x0000000000000008ULL
	31	#define HPTE_R_M 0x0000000000000010ULL
	32	#define HPTE_R_I 0x0000000000000020ULL
	33	#define HPTE_R_W 0x0000000000000040ULL
	34	#define HPTE_R_WIMG 0x0000000000000078ULL
	35	#define HPTE_R_C 0x0000000000000080ULL
	36	#define HPTE_R_R 0x0000000000000100ULL
	37	#define HPTE_R_KEY_LO 0x0000000000000e00ULL
	38
	39	#define HPTE_V_1TB_SEG 0x4000000000000000ULL
	40	#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
	41
	42	#define HPTE_V_HVLOCK 0x40ULL
	43
	44	static inline int lock_hpte(void *hpte, target_ulong bits)
	45	{
	46	uint64_t pteh;
	47
	48	pteh = ldq_p(hpte);
	49
	50	/* We're protected by qemu's global lock here */
	51	if (pteh & bits) {
	52	return 0;
	53	}
	54	stq_p(hpte, pteh \| HPTE_V_HVLOCK);
	55	return 1;
	56	}
	57
	58	static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
	59	target_ulong pte_index)
	60	{
	61	target_ulong rb, va_low;
	62
	63	rb = (v & ~0x7fULL) << 16; /* AVA field */
	64	va_low = pte_index >> 3;
	65	if (v & HPTE_V_SECONDARY) {
	66	va_low = ~va_low;
	67	}
	68	/* xor vsid from AVA */
	69	if (!(v & HPTE_V_1TB_SEG)) {
	70	va_low ^= v >> 12;
	71	} else {
	72	va_low ^= v >> 24;
73	}
74	va_low &= 0x7ff;
75	if (v & HPTE_V_LARGE) {
76	rb \|= 1; /* L field */
77	#if 0 /* Disable that P7 specific bit for now */
78	if (r & 0xff000) {
79	/* non-16MB large page, must be 64k */
80	/* (masks depend on page size) */
81	rb \|= 0x1000; /* page encoding in LP field */
82	rb \|= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
83	rb \|= (va_low & 0xfe); /* AVAL field */
84	}
85	#endif
86	} else {
87	/* 4kB page */
88	rb \|= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */
89	}
90	rb \|= (v >> 54) & 0x300; /* B field */
91	return rb;
92	}
93
94	static target_ulong h_enter(CPUState env, sPAPREnvironment spapr,
95	target_ulong opcode, target_ulong *args)
96	{
97	target_ulong flags = args[0];
98	target_ulong pte_index = args[1];
99	target_ulong pteh = args[2];
100	target_ulong ptel = args[3];
101	target_ulong porder;
102	target_ulong i, pa;
103	uint8_t *hpte;
104
105	/* only handle 4k and 16M pages for now */
106	porder = 12;
107	if (pteh & HPTE_V_LARGE) {
108	#if 0 /* We don't support 64k pages yet */
109	if ((ptel & 0xf000) == 0x1000) {
110	/* 64k page */
111	porder = 16;
112	} else
113	#endif
114	if ((ptel & 0xff000) == 0) {
115	/* 16M page */
116	porder = 24;
117	/* lowest AVA bit must be 0 for 16M pages */
118	if (pteh & 0x80) {
119	return H_PARAMETER;
120	}
121	} else {
122	return H_PARAMETER;
123	}
124	}
125
126	pa = ptel & HPTE_R_RPN;
127	/* FIXME: bounds check the pa? */
128
129	/* Check WIMG */
130	if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
131	return H_PARAMETER;
132	}
133	pteh &= ~0x60ULL;
134
135	if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
136	return H_PARAMETER;
137	}
138	if (likely((flags & H_EXACT) == 0)) {
139	pte_index &= ~7ULL;
140	hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
141	for (i = 0; ; ++i) {
142	if (i == 8) {
143	return H_PTEG_FULL;
144	}
145	if (((ldq_p(hpte) & HPTE_V_VALID) == 0) &&
146	lock_hpte(hpte, HPTE_V_HVLOCK \| HPTE_V_VALID)) {
147	break;
148	}
149	hpte += HASH_PTE_SIZE_64;
150	}
151	} else {
152	i = 0;
153	hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
154	if (!lock_hpte(hpte, HPTE_V_HVLOCK \| HPTE_V_VALID)) {
155	return H_PTEG_FULL;
156	}
157	}
158	stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
159	/* eieio(); FIXME: need some sort of barrier for smp? */
160	stq_p(hpte, pteh);
161
162	assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
163	args[0] = pte_index + i;
164	return H_SUCCESS;
165	}
166
167	static target_ulong h_remove(CPUState env, sPAPREnvironment spapr,
168	target_ulong opcode, target_ulong *args)
169	{
170	target_ulong flags = args[0];
171	target_ulong pte_index = args[1];
172	target_ulong avpn = args[2];
173	uint8_t *hpte;
174	target_ulong v, r, rb;
175
176	if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
177	return H_PARAMETER;
178	}
179
180	hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
181	while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
182	/* We have no real concurrency in qemu soft-emulation, so we
183	* will never actually have a contested lock */
184	assert(0);
185	}
186
187	v = ldq_p(hpte);
188	r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
189
190	if ((v & HPTE_V_VALID) == 0 \|\|
191	((flags & H_AVPN) && (v & ~0x7fULL) != avpn) \|\|
192	((flags & H_ANDCOND) && (v & avpn) != 0)) {
193	stq_p(hpte, v & ~HPTE_V_HVLOCK);
194	assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
195	return H_NOT_FOUND;
196	}
197	args[0] = v & ~HPTE_V_HVLOCK;
198	args[1] = r;
199	stq_p(hpte, 0);
200	rb = compute_tlbie_rb(v, r, pte_index);
201	ppc_tlb_invalidate_one(env, rb);
202	assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
203	return H_SUCCESS;
204	}
205
206	static target_ulong h_protect(CPUState env, sPAPREnvironment spapr,
207	target_ulong opcode, target_ulong *args)
208	{
209	target_ulong flags = args[0];
210	target_ulong pte_index = args[1];
211	target_ulong avpn = args[2];
212	uint8_t *hpte;
213	target_ulong v, r, rb;
214
215	if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
216	return H_PARAMETER;
217	}
218
219	hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
220	while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
221	/* We have no real concurrency in qemu soft-emulation, so we
222	* will never actually have a contested lock */
223	assert(0);
224	}
225
226	v = ldq_p(hpte);
227	r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
228
229	if ((v & HPTE_V_VALID) == 0 \|\|
230	((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
231	stq_p(hpte, v & ~HPTE_V_HVLOCK);
232	assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
233	return H_NOT_FOUND;
234	}
235
236	r &= ~(HPTE_R_PP0 \| HPTE_R_PP \| HPTE_R_N \|
237	HPTE_R_KEY_HI \| HPTE_R_KEY_LO);
238	r \|= (flags << 55) & HPTE_R_PP0;
239	r \|= (flags << 48) & HPTE_R_KEY_HI;
240	r \|= flags & (HPTE_R_PP \| HPTE_R_N \| HPTE_R_KEY_LO);
241	rb = compute_tlbie_rb(v, r, pte_index);
242	stq_p(hpte, v & ~HPTE_V_VALID);
243	ppc_tlb_invalidate_one(env, rb);
244	stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
245	/* Don't need a memory barrier, due to qemu's global lock */
246	stq_p(hpte, v & ~HPTE_V_HVLOCK);
247	assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
248	return H_SUCCESS;
249	}
250
39ac8455 DG	251	static target_ulong h_rtas(CPUState env, sPAPREnvironment spapr,
	252	target_ulong opcode, target_ulong *args)
	253	{
	254	target_ulong rtas_r3 = args[0];
	255	uint32_t token = ldl_phys(rtas_r3);
	256	uint32_t nargs = ldl_phys(rtas_r3 + 4);
	257	uint32_t nret = ldl_phys(rtas_r3 + 8);
	258
	259	return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12,
	260	nret, rtas_r3 + 12 + 4*nargs);
	261	}
	262
	263	spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
	264	spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE];
9fdf0c29 DG	265
	266	void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
	267	{
39ac8455 DG	268	spapr_hcall_fn *slot;
	269
	270	if (opcode <= MAX_HCALL_OPCODE) {
	271	assert((opcode & 0x3) == 0);
9fdf0c29	272
39ac8455 DG	273	slot = &papr_hypercall_table[opcode / 4];
	274	} else {
	275	assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
9fdf0c29	276
9fdf0c29	277
39ac8455 DG	278	slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
39ac8455 DG	279	}
9fdf0c29	280
39ac8455 DG	281	assert(!(slot) \|\| (fn == slot));
39ac8455 DG	282	*slot = fn;
9fdf0c29 DG	283	}
	284
	285	target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
	286	target_ulong *args)
	287	{
	288	if (msr_pr) {
	289	hcall_dprintf("Hypercall made with MSR[PR]=1\n");
	290	return H_PRIVILEGE;
	291	}
	292
	293	if ((opcode <= MAX_HCALL_OPCODE)
	294	&& ((opcode & 0x3) == 0)) {
39ac8455 DG	295	spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
	296
	297	if (fn) {
	298	return fn(env, spapr, opcode, args);
	299	}
	300	} else if ((opcode >= KVMPPC_HCALL_BASE) &&
	301	(opcode <= KVMPPC_HCALL_MAX)) {
	302	spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
9fdf0c29 DG	303
	304	if (fn) {
	305	return fn(env, spapr, opcode, args);
	306	}
	307	}
	308
	309	hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
	310	return H_FUNCTION;
	311	}
f43e3525 DG	312
	313	static void hypercall_init(void)
	314	{
	315	/* hcall-pft */
	316	spapr_register_hypercall(H_ENTER, h_enter);
	317	spapr_register_hypercall(H_REMOVE, h_remove);
	318	spapr_register_hypercall(H_PROTECT, h_protect);
39ac8455 DG	319
	320	/* qemu/KVM-PPC specific hcalls */
	321	spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
f43e3525 DG	322	}
f43e3525 DG	323	device_init(hypercall_init);