[qemu.git] / hw / ide / cmd646.c

/*
 * QEMU IDE Emulation: PCI cmd646 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
#include <hw/isa/isa.h>
#include "block/block.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"

#include <hw/ide/pci.h>

/* CMD646 specific */
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define   MRDMODE_BLK_CH0	0x10
#define   MRDMODE_BLK_CH1	0x20
#define UDIDETCR0	0x73
#define UDIDETCR1	0x7B

static void cmd646_update_irq(PCIIDEState *d);

static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (addr != 2 || size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }
    return ide_status_read(cmd646bar->bus, addr + 2);
}

static void cmd646_cmd_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (addr != 2 || size != 1) {
        return;
    }
    ide_cmd_write(cmd646bar->bus, addr + 2, data);
}

static const MemoryRegionOps cmd646_cmd_ops = {
    .read = cmd646_cmd_read,
    .write = cmd646_cmd_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (size == 1) {
        return ide_ioport_read(cmd646bar->bus, addr);
    } else if (addr == 0) {
        if (size == 2) {
            return ide_data_readw(cmd646bar->bus, addr);
        } else {
            return ide_data_readl(cmd646bar->bus, addr);
        }
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void cmd646_data_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (size == 1) {
        ide_ioport_write(cmd646bar->bus, addr, data);
    } else if (addr == 0) {
        if (size == 2) {
            ide_data_writew(cmd646bar->bus, addr, data);
        } else {
            ide_data_writel(cmd646bar->bus, addr, data);
        }
    }
}

static const MemoryRegionOps cmd646_data_ops = {
    .read = cmd646_data_read,
    .write = cmd646_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
{
    IDEBus *bus = &d->bus[bus_num];
    CMD646BAR *bar = &d->cmd646_bar[bus_num];

    bar->bus = bus;
    bar->pci_dev = d;
    memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
                          "cmd646-cmd", 4);
    memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
                          "cmd646-data", 8);
}

static uint64_t bmdma_read(void *opaque, hwaddr addr,
                           unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 1:
        val = pci_dev->config[MRDMODE];
        break;
    case 2:
        val = bm->status;
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            val = pci_dev->config[UDIDETCR0];
        } else {
            val = pci_dev->config[UDIDETCR1];
        }
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
#endif
    return val;
}

static void bmdma_write(void *opaque, hwaddr addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);

    if (size != 1) {
        return;
    }

#ifdef DEBUG_IDE
    printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
#endif
    switch(addr & 3) {
    case 0:
        bmdma_cmd_writeb(bm, val);
        break;
    case 1:
        pci_dev->config[MRDMODE] =
            (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
        cmd646_update_irq(bm->pci_dev);
        break;
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            pci_dev->config[UDIDETCR0] = val;
        } else {
            pci_dev->config[UDIDETCR1] = val;
        }
        break;
    }
}

static const MemoryRegionOps cmd646_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    BMDMAState *bm;
    int i;

    memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
    for(i = 0;i < 2; i++) {
        bm = &d->bmdma[i];
        memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
                              "cmd646-bmdma-bus", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, OBJECT(d),
                              &bmdma_addr_ioport_ops, bm,
                              "cmd646-bmdma-ioport", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

/* XXX: call it also when the MRDMODE is changed from the PCI config
   registers */
static void cmd646_update_irq(PCIIDEState *d)
{
    PCIDevice *pd = PCI_DEVICE(d);
    int pci_level;

    pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
                 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
        ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
         !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
    pci_set_irq(pd, pci_level);
}

/* the PCI irq level is the logical OR of the two channels */
static void cmd646_set_irq(void *opaque, int channel, int level)
{
    PCIIDEState *d = opaque;
    PCIDevice *pd = PCI_DEVICE(d);
    int irq_mask;

    irq_mask = MRDMODE_INTR_CH0 << channel;
    if (level) {
        pd->config[MRDMODE] |= irq_mask;
    } else {
        pd->config[MRDMODE] &= ~irq_mask;
    }
    cmd646_update_irq(d);
}

static void cmd646_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    unsigned int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }
}

/* CMD646 PCI IDE controller */
static int pci_cmd646_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;
    qemu_irq *irq;
    int i;

    pci_conf[PCI_CLASS_PROG] = 0x8f;

    pci_conf[0x51] = 0x04; // enable IDE0
    if (d->secondary) {
        /* XXX: if not enabled, really disable the seconday IDE controller */
        pci_conf[0x51] |= 0x08; /* enable IDE1 */
    }

    setup_cmd646_bar(d, 0);
    setup_cmd646_bar(d, 1);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    /* TODO: RST# value should be 0 */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
        ide_init2(&d->bus[i], irq[i]);

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
    qemu_register_reset(cmd646_reset, d);
    return 0;
}

static void pci_cmd646_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_destroy(&d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
        memory_region_destroy(&d->bmdma[i].addr_ioport);
        memory_region_destroy(&d->cmd646_bar[i].cmd);
        memory_region_destroy(&d->cmd646_bar[i].data);
    }
    memory_region_destroy(&d->bmdma_bar);
}

void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
                         int secondary_ide_enabled)
{
    PCIDevice *dev;

    dev = pci_create(bus, -1, "cmd646-ide");
    qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
    qdev_init_nofail(&dev->qdev);

    pci_ide_create_devs(dev, hd_table);
}

static Property cmd646_ide_properties[] = {
    DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void cmd646_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pci_cmd646_ide_initfn;
    k->exit = pci_cmd646_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_CMD;
    k->device_id = PCI_DEVICE_ID_CMD_646;
    k->revision = 0x07;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    dc->props = cmd646_ide_properties;
}

static const TypeInfo cmd646_ide_info = {
    .name          = "cmd646-ide",
    .parent        = TYPE_PCI_IDE,
    .class_init    = cmd646_ide_class_init,
};

static void cmd646_ide_register_types(void)
{
    type_register_static(&cmd646_ide_info);
}

type_init(cmd646_ide_register_types)
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI cmd646 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include <hw/hw.h>
0d09e41a	26	#include <hw/i386/pc.h>
a2cb15b0	27	#include <hw/pci/pci.h>
0d09e41a	28	#include <hw/isa/isa.h>
737e150e	29	#include "block/block.h"
9c17d615 PB	30	#include "sysemu/sysemu.h"
9c17d615 PB	31	#include "sysemu/dma.h"
4c3df0ec JQ	32
	33	#include <hw/ide/pci.h>
	34
	35	/* CMD646 specific */
	36	#define MRDMODE 0x71
	37	#define MRDMODE_INTR_CH0 0x04
	38	#define MRDMODE_INTR_CH1 0x08
	39	#define MRDMODE_BLK_CH0 0x10
	40	#define MRDMODE_BLK_CH1 0x20
	41	#define UDIDETCR0 0x73
	42	#define UDIDETCR1 0x7B
	43
	44	static void cmd646_update_irq(PCIIDEState *d);
	45
a8170e5e	46	static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
a9deb8c6	47	unsigned size)
4c3df0ec	48	{
a9deb8c6 AK	49	CMD646BAR *cmd646bar = opaque;
	50
	51	if (addr != 2 \|\| size != 1) {
	52	return ((uint64_t)1 << (size * 8)) - 1;
	53	}
	54	return ide_status_read(cmd646bar->bus, addr + 2);
	55	}
	56
a8170e5e	57	static void cmd646_cmd_write(void *opaque, hwaddr addr,
a9deb8c6 AK	58	uint64_t data, unsigned size)
	59	{
	60	CMD646BAR *cmd646bar = opaque;
	61
	62	if (addr != 2 \|\| size != 1) {
	63	return;
	64	}
	65	ide_cmd_write(cmd646bar->bus, addr + 2, data);
	66	}
	67
a348f108	68	static const MemoryRegionOps cmd646_cmd_ops = {
a9deb8c6 AK	69	.read = cmd646_cmd_read,
	70	.write = cmd646_cmd_write,
	71	.endianness = DEVICE_LITTLE_ENDIAN,
	72	};
	73
a8170e5e	74	static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
a9deb8c6 AK	75	unsigned size)
	76	{
	77	CMD646BAR *cmd646bar = opaque;
	78
	79	if (size == 1) {
	80	return ide_ioport_read(cmd646bar->bus, addr);
	81	} else if (addr == 0) {
	82	if (size == 2) {
	83	return ide_data_readw(cmd646bar->bus, addr);
4c3df0ec	84	} else {
a9deb8c6	85	return ide_data_readl(cmd646bar->bus, addr);
4c3df0ec JQ	86	}
4c3df0ec JQ	87	}
a9deb8c6	88	return ((uint64_t)1 << (size * 8)) - 1;
4c3df0ec JQ	89	}
4c3df0ec JQ	90
a8170e5e	91	static void cmd646_data_write(void *opaque, hwaddr addr,
a9deb8c6	92	uint64_t data, unsigned size)
61f58e59	93	{
a9deb8c6 AK	94	CMD646BAR *cmd646bar = opaque;
	95
	96	if (size == 1) {
0ed8b6f6	97	ide_ioport_write(cmd646bar->bus, addr, data);
a9deb8c6 AK	98	} else if (addr == 0) {
a9deb8c6 AK	99	if (size == 2) {
0ed8b6f6	100	ide_data_writew(cmd646bar->bus, addr, data);
a9deb8c6	101	} else {
0ed8b6f6	102	ide_data_writel(cmd646bar->bus, addr, data);
a9deb8c6 AK	103	}
	104	}
	105	}
	106
a348f108	107	static const MemoryRegionOps cmd646_data_ops = {
a9deb8c6 AK	108	.read = cmd646_data_read,
	109	.write = cmd646_data_write,
	110	.endianness = DEVICE_LITTLE_ENDIAN,
	111	};
	112
	113	static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
	114	{
	115	IDEBus *bus = &d->bus[bus_num];
	116	CMD646BAR *bar = &d->cmd646_bar[bus_num];
	117
	118	bar->bus = bus;
	119	bar->pci_dev = d;
1437c94b PB	120	memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
	121	"cmd646-cmd", 4);
	122	memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
	123	"cmd646-data", 8);
a9deb8c6 AK	124	}
a9deb8c6 AK	125
a8170e5e	126	static uint64_t bmdma_read(void *opaque, hwaddr addr,
a9deb8c6 AK	127	unsigned size)
	128	{
	129	BMDMAState *bm = opaque;
f6c11d56	130	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
4c3df0ec JQ	131	uint32_t val;
4c3df0ec JQ	132
a9deb8c6 AK	133	if (size != 1) {
	134	return ((uint64_t)1 << (size * 8)) - 1;
	135	}
	136
4c3df0ec JQ	137	switch(addr & 3) {
	138	case 0:
	139	val = bm->cmd;
	140	break;
	141	case 1:
f6c11d56	142	val = pci_dev->config[MRDMODE];
4c3df0ec JQ	143	break;
	144	case 2:
	145	val = bm->status;
	146	break;
	147	case 3:
f6c11d56 AF	148	if (bm == &bm->pci_dev->bmdma[0]) {
f6c11d56 AF	149	val = pci_dev->config[UDIDETCR0];
4c3df0ec	150	} else {
f6c11d56	151	val = pci_dev->config[UDIDETCR1];
4c3df0ec JQ	152	}
	153	break;
	154	default:
	155	val = 0xff;
	156	break;
	157	}
	158	#ifdef DEBUG_IDE
721da65c	159	printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
4c3df0ec JQ	160	#endif
	161	return val;
	162	}
	163
a8170e5e	164	static void bmdma_write(void *opaque, hwaddr addr,
a9deb8c6	165	uint64_t val, unsigned size)
70ae65f5	166	{
a9deb8c6	167	BMDMAState *bm = opaque;
f6c11d56	168	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
70ae65f5	169
a9deb8c6 AK	170	if (size != 1) {
	171	return;
	172	}
70ae65f5	173
4c3df0ec	174	#ifdef DEBUG_IDE
721da65c	175	printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
4c3df0ec JQ	176	#endif
4c3df0ec JQ	177	switch(addr & 3) {
50a48094	178	case 0:
a9deb8c6	179	bmdma_cmd_writeb(bm, val);
50a48094	180	break;
4c3df0ec	181	case 1:
f6c11d56 AF	182	pci_dev->config[MRDMODE] =
	183	(pci_dev->config[MRDMODE] & ~0x30) \| (val & 0x30);
	184	cmd646_update_irq(bm->pci_dev);
4c3df0ec JQ	185	break;
	186	case 2:
	187	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	188	break;
	189	case 3:
f6c11d56 AF	190	if (bm == &bm->pci_dev->bmdma[0]) {
	191	pci_dev->config[UDIDETCR0] = val;
	192	} else {
	193	pci_dev->config[UDIDETCR1] = val;
	194	}
4c3df0ec JQ	195	break;
	196	}
	197	}
	198
a348f108	199	static const MemoryRegionOps cmd646_bmdma_ops = {
a9deb8c6 AK	200	.read = bmdma_read,
	201	.write = bmdma_write,
	202	};
70ae65f5	203
a9deb8c6	204	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	205	{
a9deb8c6	206	BMDMAState *bm;
4c3df0ec JQ	207	int i;
4c3df0ec JQ	208
1437c94b	209	memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
4c3df0ec	210	for(i = 0;i < 2; i++) {
a9deb8c6	211	bm = &d->bmdma[i];
1437c94b	212	memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
a9deb8c6 AK	213	"cmd646-bmdma-bus", 4);
a9deb8c6 AK	214	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
1437c94b PB	215	memory_region_init_io(&bm->addr_ioport, OBJECT(d),
1437c94b PB	216	&bmdma_addr_ioport_ops, bm,
a9deb8c6 AK	217	"cmd646-bmdma-ioport", 4);
a9deb8c6 AK	218	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	219	}
	220	}
	221
	222	/* XXX: call it also when the MRDMODE is changed from the PCI config
	223	registers */
	224	static void cmd646_update_irq(PCIIDEState *d)
	225	{
f6c11d56	226	PCIDevice *pd = PCI_DEVICE(d);
4c3df0ec	227	int pci_level;
f6c11d56 AF	228
	229	pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
	230	!(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) \|\|
	231	((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
	232	!(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
9e64f8a3	233	pci_set_irq(pd, pci_level);
4c3df0ec JQ	234	}
	235
	236	/* the PCI irq level is the logical OR of the two channels */
	237	static void cmd646_set_irq(void *opaque, int channel, int level)
	238	{
	239	PCIIDEState *d = opaque;
f6c11d56	240	PCIDevice *pd = PCI_DEVICE(d);
4c3df0ec JQ	241	int irq_mask;
	242
	243	irq_mask = MRDMODE_INTR_CH0 << channel;
f6c11d56 AF	244	if (level) {
	245	pd->config[MRDMODE] \|= irq_mask;
	246	} else {
	247	pd->config[MRDMODE] &= ~irq_mask;
	248	}
4c3df0ec JQ	249	cmd646_update_irq(d);
	250	}
	251
	252	static void cmd646_reset(void *opaque)
	253	{
	254	PCIIDEState *d = opaque;
	255	unsigned int i;
	256
4a643563 BS	257	for (i = 0; i < 2; i++) {
4a643563 BS	258	ide_bus_reset(&d->bus[i]);
4a643563	259	}
4c3df0ec JQ	260	}
	261
	262	/* CMD646 PCI IDE controller */
	263	static int pci_cmd646_ide_initfn(PCIDevice *dev)
	264	{
f6c11d56 AF	265	PCIIDEState *d = PCI_IDE(dev);
f6c11d56 AF	266	uint8_t *pci_conf = dev->config;
4c3df0ec	267	qemu_irq *irq;
61d9d6b0	268	int i;
4c3df0ec	269
409570a7	270	pci_conf[PCI_CLASS_PROG] = 0x8f;
4c3df0ec	271
4c3df0ec JQ	272	pci_conf[0x51] = 0x04; // enable IDE0
	273	if (d->secondary) {
	274	/* XXX: if not enabled, really disable the seconday IDE controller */
	275	pci_conf[0x51] \|= 0x08; /* enable IDE1 */
	276	}
	277
a9deb8c6 AK	278	setup_cmd646_bar(d, 0);
a9deb8c6 AK	279	setup_cmd646_bar(d, 1);
e824b2cc AK	280	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
	281	pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
	282	pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
	283	pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
a9deb8c6	284	bmdma_setup_bar(d);
e824b2cc	285	pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	286
409570a7 MT	287	/* TODO: RST# value should be 0 */
409570a7 MT	288	pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
4c3df0ec JQ	289
4c3df0ec JQ	290	irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
61d9d6b0	291	for (i = 0; i < 2; i++) {
c6baf942	292	ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
61d9d6b0 SH	293	ide_init2(&d->bus[i], irq[i]);
61d9d6b0 SH	294
a9deb8c6	295	bmdma_init(&d->bus[i], &d->bmdma[i], d);
f56b18c0	296	d->bmdma[i].bus = &d->bus[i];
61d9d6b0	297	qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
f56b18c0	298	&d->bmdma[i].dma);
61d9d6b0	299	}
4c3df0ec	300
f6c11d56	301	vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
4c3df0ec	302	qemu_register_reset(cmd646_reset, d);
4c3df0ec JQ	303	return 0;
	304	}
	305
f90c2bcd	306	static void pci_cmd646_ide_exitfn(PCIDevice *dev)
a9deb8c6	307	{
f6c11d56	308	PCIIDEState *d = PCI_IDE(dev);
a9deb8c6 AK	309	unsigned i;
	310
	311	for (i = 0; i < 2; ++i) {
	312	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
	313	memory_region_destroy(&d->bmdma[i].extra_io);
	314	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
	315	memory_region_destroy(&d->bmdma[i].addr_ioport);
	316	memory_region_destroy(&d->cmd646_bar[i].cmd);
	317	memory_region_destroy(&d->cmd646_bar[i].data);
	318	}
	319	memory_region_destroy(&d->bmdma_bar);
a9deb8c6 AK	320	}
a9deb8c6 AK	321
4c3df0ec JQ	322	void pci_cmd646_ide_init(PCIBus bus, DriveInfo *hd_table,
	323	int secondary_ide_enabled)
	324	{
	325	PCIDevice *dev;
	326
556cd098	327	dev = pci_create(bus, -1, "cmd646-ide");
4c3df0ec JQ	328	qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
	329	qdev_init_nofail(&dev->qdev);
	330
	331	pci_ide_create_devs(dev, hd_table);
	332	}
	333
40021f08 AL	334	static Property cmd646_ide_properties[] = {
	335	DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
	336	DEFINE_PROP_END_OF_LIST(),
	337	};
	338
	339	static void cmd646_ide_class_init(ObjectClass klass, void data)
	340	{
39bffca2	341	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	342	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	343
	344	k->init = pci_cmd646_ide_initfn;
	345	k->exit = pci_cmd646_ide_exitfn;
	346	k->vendor_id = PCI_VENDOR_ID_CMD;
	347	k->device_id = PCI_DEVICE_ID_CMD_646;
	348	k->revision = 0x07;
	349	k->class_id = PCI_CLASS_STORAGE_IDE;
39bffca2	350	dc->props = cmd646_ide_properties;
40021f08 AL	351	}
40021f08 AL	352
8c43a6f0	353	static const TypeInfo cmd646_ide_info = {
39bffca2	354	.name = "cmd646-ide",
f6c11d56	355	.parent = TYPE_PCI_IDE,
39bffca2	356	.class_init = cmd646_ide_class_init,
4c3df0ec JQ	357	};
4c3df0ec JQ	358
83f7d43a	359	static void cmd646_ide_register_types(void)
4c3df0ec	360	{
39bffca2	361	type_register_static(&cmd646_ide_info);
4c3df0ec	362	}
83f7d43a AF	363
83f7d43a AF	364	type_init(cmd646_ide_register_types)