[qemu.git] / hw / ide / cmd646.c

/*
 * QEMU IDE Emulation: PCI cmd646 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
#include "sysemu/block-backend.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"

#include "hw/ide/pci.h"

/* CMD646 specific */
#define CFR		0x50
#define   CFR_INTR_CH0	0x04
#define CNTRL		0x51
#define   CNTRL_EN_CH0	0x04
#define   CNTRL_EN_CH1	0x08
#define ARTTIM23	0x57
#define    ARTTIM23_INTR_CH1	0x10
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define   MRDMODE_BLK_CH0	0x10
#define   MRDMODE_BLK_CH1	0x20
#define UDIDETCR0	0x73
#define UDIDETCR1	0x7B

static void cmd646_update_irq(PCIDevice *pd);

static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (addr != 2 || size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }
    return ide_status_read(cmd646bar->bus, addr + 2);
}

static void cmd646_cmd_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (addr != 2 || size != 1) {
        return;
    }
    ide_cmd_write(cmd646bar->bus, addr + 2, data);
}

static const MemoryRegionOps cmd646_cmd_ops = {
    .read = cmd646_cmd_read,
    .write = cmd646_cmd_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (size == 1) {
        return ide_ioport_read(cmd646bar->bus, addr);
    } else if (addr == 0) {
        if (size == 2) {
            return ide_data_readw(cmd646bar->bus, addr);
        } else {
            return ide_data_readl(cmd646bar->bus, addr);
        }
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void cmd646_data_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (size == 1) {
        ide_ioport_write(cmd646bar->bus, addr, data);
    } else if (addr == 0) {
        if (size == 2) {
            ide_data_writew(cmd646bar->bus, addr, data);
        } else {
            ide_data_writel(cmd646bar->bus, addr, data);
        }
    }
}

static const MemoryRegionOps cmd646_data_ops = {
    .read = cmd646_data_read,
    .write = cmd646_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
{
    IDEBus *bus = &d->bus[bus_num];
    CMD646BAR *bar = &d->cmd646_bar[bus_num];

    bar->bus = bus;
    bar->pci_dev = d;
    memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
                          "cmd646-cmd", 4);
    memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
                          "cmd646-data", 8);
}

static void cmd646_update_dma_interrupts(PCIDevice *pd)
{
    /* Sync DMA interrupt status from UDMA interrupt status */
    if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
        pd->config[CFR] |= CFR_INTR_CH0;
    } else {
        pd->config[CFR] &= ~CFR_INTR_CH0;
    }

    if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
        pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
    } else {
        pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
    }
}

static void cmd646_update_udma_interrupts(PCIDevice *pd)
{
    /* Sync UDMA interrupt status from DMA interrupt status */
    if (pd->config[CFR] & CFR_INTR_CH0) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
    }

    if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
    }
}

static uint64_t bmdma_read(void *opaque, hwaddr addr,
                           unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 1:
        val = pci_dev->config[MRDMODE];
        break;
    case 2:
        val = bm->status;
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            val = pci_dev->config[UDIDETCR0];
        } else {
            val = pci_dev->config[UDIDETCR1];
        }
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
#endif
    return val;
}

static void bmdma_write(void *opaque, hwaddr addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);

    if (size != 1) {
        return;
    }

#ifdef DEBUG_IDE
    printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
#endif
    switch(addr & 3) {
    case 0:
        bmdma_cmd_writeb(bm, val);
        break;
    case 1:
        pci_dev->config[MRDMODE] =
            (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
        cmd646_update_dma_interrupts(pci_dev);
        cmd646_update_irq(pci_dev);
        break;
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            pci_dev->config[UDIDETCR0] = val;
        } else {
            pci_dev->config[UDIDETCR1] = val;
        }
        break;
    }
}

static const MemoryRegionOps cmd646_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    BMDMAState *bm;
    int i;

    memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
    for(i = 0;i < 2; i++) {
        bm = &d->bmdma[i];
        memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
                              "cmd646-bmdma-bus", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, OBJECT(d),
                              &bmdma_addr_ioport_ops, bm,
                              "cmd646-bmdma-ioport", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void cmd646_update_irq(PCIDevice *pd)
{
    int pci_level;

    pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
                 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
        ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
         !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
    pci_set_irq(pd, pci_level);
}

/* the PCI irq level is the logical OR of the two channels */
static void cmd646_set_irq(void *opaque, int channel, int level)
{
    PCIIDEState *d = opaque;
    PCIDevice *pd = PCI_DEVICE(d);
    int irq_mask;

    irq_mask = MRDMODE_INTR_CH0 << channel;
    if (level) {
        pd->config[MRDMODE] |= irq_mask;
    } else {
        pd->config[MRDMODE] &= ~irq_mask;
    }
    cmd646_update_dma_interrupts(pd);
    cmd646_update_irq(pd);
}

static void cmd646_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    unsigned int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }
}

static uint32_t cmd646_pci_config_read(PCIDevice *d,
                                       uint32_t address, int len)
{
    return pci_default_read_config(d, address, len);
}

static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
                                    int l)
{
    uint32_t i;

    pci_default_write_config(d, addr, val, l);

    for (i = addr; i < addr + l; i++) {
        switch (i) {
        case CFR:
        case ARTTIM23:
            cmd646_update_udma_interrupts(d);
            break;
        case MRDMODE:
            cmd646_update_dma_interrupts(d);
            break;
        }
    }

    cmd646_update_irq(d);
}

/* CMD646 PCI IDE controller */
static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;
    qemu_irq *irq;
    int i;

    pci_conf[PCI_CLASS_PROG] = 0x8f;

    pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
    if (d->secondary) {
        /* XXX: if not enabled, really disable the seconday IDE controller */
        pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
    }

    /* Set write-to-clear interrupt bits */
    dev->wmask[CFR] = 0x0;
    dev->w1cmask[CFR] = CFR_INTR_CH0;
    dev->wmask[ARTTIM23] = 0x0;
    dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
    dev->wmask[MRDMODE] = 0x0;
    dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;

    setup_cmd646_bar(d, 0);
    setup_cmd646_bar(d, 1);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    /* TODO: RST# value should be 0 */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
        ide_init2(&d->bus[i], irq[i]);

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        ide_register_restart_cb(&d->bus[i]);
    }

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
    qemu_register_reset(cmd646_reset, d);
}

static void pci_cmd646_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
    }
}

void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
                         int secondary_ide_enabled)
{
    PCIDevice *dev;

    dev = pci_create(bus, -1, "cmd646-ide");
    qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
    qdev_init_nofail(&dev->qdev);

    pci_ide_create_devs(dev, hd_table);
}

static Property cmd646_ide_properties[] = {
    DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void cmd646_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_cmd646_ide_realize;
    k->exit = pci_cmd646_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_CMD;
    k->device_id = PCI_DEVICE_ID_CMD_646;
    k->revision = 0x07;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    k->config_read = cmd646_pci_config_read;
    k->config_write = cmd646_pci_config_write;
    dc->props = cmd646_ide_properties;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}

static const TypeInfo cmd646_ide_info = {
    .name          = "cmd646-ide",
    .parent        = TYPE_PCI_IDE,
    .class_init    = cmd646_ide_class_init,
};

static void cmd646_ide_register_types(void)
{
    type_register_static(&cmd646_ide_info);
}

type_init(cmd646_ide_register_types)
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI cmd646 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
53239262	25	#include "qemu/osdep.h"
a9c94277 MA	26	#include "hw/hw.h"
	27	#include "hw/i386/pc.h"
	28	#include "hw/pci/pci.h"
	29	#include "hw/isa/isa.h"
4be74634	30	#include "sysemu/block-backend.h"
9c17d615 PB	31	#include "sysemu/sysemu.h"
9c17d615 PB	32	#include "sysemu/dma.h"
4c3df0ec	33
a9c94277	34	#include "hw/ide/pci.h"
4c3df0ec JQ	35
4c3df0ec JQ	36	/* CMD646 specific */
5bbc0a70 MCA	37	#define CFR 0x50
5bbc0a70 MCA	38	#define CFR_INTR_CH0 0x04
58f16a7b MCA	39	#define CNTRL 0x51
	40	#define CNTRL_EN_CH0 0x04
	41	#define CNTRL_EN_CH1 0x08
5bbc0a70 MCA	42	#define ARTTIM23 0x57
5bbc0a70 MCA	43	#define ARTTIM23_INTR_CH1 0x10
4c3df0ec JQ	44	#define MRDMODE 0x71
	45	#define MRDMODE_INTR_CH0 0x04
	46	#define MRDMODE_INTR_CH1 0x08
	47	#define MRDMODE_BLK_CH0 0x10
	48	#define MRDMODE_BLK_CH1 0x20
	49	#define UDIDETCR0 0x73
	50	#define UDIDETCR1 0x7B
	51
dab91a1e	52	static void cmd646_update_irq(PCIDevice *pd);
4c3df0ec	53
a8170e5e	54	static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
a9deb8c6	55	unsigned size)
4c3df0ec	56	{
a9deb8c6 AK	57	CMD646BAR *cmd646bar = opaque;
	58
	59	if (addr != 2 \|\| size != 1) {
	60	return ((uint64_t)1 << (size * 8)) - 1;
	61	}
	62	return ide_status_read(cmd646bar->bus, addr + 2);
	63	}
	64
a8170e5e	65	static void cmd646_cmd_write(void *opaque, hwaddr addr,
a9deb8c6 AK	66	uint64_t data, unsigned size)
	67	{
	68	CMD646BAR *cmd646bar = opaque;
	69
	70	if (addr != 2 \|\| size != 1) {
	71	return;
	72	}
	73	ide_cmd_write(cmd646bar->bus, addr + 2, data);
	74	}
	75
a348f108	76	static const MemoryRegionOps cmd646_cmd_ops = {
a9deb8c6 AK	77	.read = cmd646_cmd_read,
	78	.write = cmd646_cmd_write,
	79	.endianness = DEVICE_LITTLE_ENDIAN,
	80	};
	81
a8170e5e	82	static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
a9deb8c6 AK	83	unsigned size)
	84	{
	85	CMD646BAR *cmd646bar = opaque;
	86
	87	if (size == 1) {
	88	return ide_ioport_read(cmd646bar->bus, addr);
	89	} else if (addr == 0) {
	90	if (size == 2) {
	91	return ide_data_readw(cmd646bar->bus, addr);
4c3df0ec	92	} else {
a9deb8c6	93	return ide_data_readl(cmd646bar->bus, addr);
4c3df0ec JQ	94	}
4c3df0ec JQ	95	}
a9deb8c6	96	return ((uint64_t)1 << (size * 8)) - 1;
4c3df0ec JQ	97	}
4c3df0ec JQ	98
a8170e5e	99	static void cmd646_data_write(void *opaque, hwaddr addr,
a9deb8c6	100	uint64_t data, unsigned size)
61f58e59	101	{
a9deb8c6 AK	102	CMD646BAR *cmd646bar = opaque;
	103
	104	if (size == 1) {
0ed8b6f6	105	ide_ioport_write(cmd646bar->bus, addr, data);
a9deb8c6 AK	106	} else if (addr == 0) {
a9deb8c6 AK	107	if (size == 2) {
0ed8b6f6	108	ide_data_writew(cmd646bar->bus, addr, data);
a9deb8c6	109	} else {
0ed8b6f6	110	ide_data_writel(cmd646bar->bus, addr, data);
a9deb8c6 AK	111	}
	112	}
	113	}
	114
a348f108	115	static const MemoryRegionOps cmd646_data_ops = {
a9deb8c6 AK	116	.read = cmd646_data_read,
	117	.write = cmd646_data_write,
	118	.endianness = DEVICE_LITTLE_ENDIAN,
	119	};
	120
	121	static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
	122	{
	123	IDEBus *bus = &d->bus[bus_num];
	124	CMD646BAR *bar = &d->cmd646_bar[bus_num];
	125
	126	bar->bus = bus;
	127	bar->pci_dev = d;
1437c94b PB	128	memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
	129	"cmd646-cmd", 4);
	130	memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
	131	"cmd646-data", 8);
a9deb8c6 AK	132	}
a9deb8c6 AK	133
5bbc0a70 MCA	134	static void cmd646_update_dma_interrupts(PCIDevice *pd)
	135	{
	136	/* Sync DMA interrupt status from UDMA interrupt status */
	137	if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
	138	pd->config[CFR] \|= CFR_INTR_CH0;
	139	} else {
	140	pd->config[CFR] &= ~CFR_INTR_CH0;
	141	}
	142
	143	if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
	144	pd->config[ARTTIM23] \|= ARTTIM23_INTR_CH1;
	145	} else {
	146	pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
	147	}
	148	}
	149
271dddd1 MCA	150	static void cmd646_update_udma_interrupts(PCIDevice *pd)
	151	{
	152	/* Sync UDMA interrupt status from DMA interrupt status */
	153	if (pd->config[CFR] & CFR_INTR_CH0) {
	154	pd->config[MRDMODE] \|= MRDMODE_INTR_CH0;
	155	} else {
	156	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
	157	}
	158
	159	if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
	160	pd->config[MRDMODE] \|= MRDMODE_INTR_CH1;
	161	} else {
	162	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
	163	}
	164	}
	165
a8170e5e	166	static uint64_t bmdma_read(void *opaque, hwaddr addr,
a9deb8c6 AK	167	unsigned size)
	168	{
	169	BMDMAState *bm = opaque;
f6c11d56	170	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
4c3df0ec JQ	171	uint32_t val;
4c3df0ec JQ	172
a9deb8c6 AK	173	if (size != 1) {
	174	return ((uint64_t)1 << (size * 8)) - 1;
	175	}
	176
4c3df0ec JQ	177	switch(addr & 3) {
	178	case 0:
	179	val = bm->cmd;
	180	break;
	181	case 1:
f6c11d56	182	val = pci_dev->config[MRDMODE];
4c3df0ec JQ	183	break;
	184	case 2:
	185	val = bm->status;
	186	break;
	187	case 3:
f6c11d56 AF	188	if (bm == &bm->pci_dev->bmdma[0]) {
f6c11d56 AF	189	val = pci_dev->config[UDIDETCR0];
4c3df0ec	190	} else {
f6c11d56	191	val = pci_dev->config[UDIDETCR1];
4c3df0ec JQ	192	}
	193	break;
	194	default:
	195	val = 0xff;
	196	break;
	197	}
	198	#ifdef DEBUG_IDE
721da65c	199	printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
4c3df0ec JQ	200	#endif
	201	return val;
	202	}
	203
a8170e5e	204	static void bmdma_write(void *opaque, hwaddr addr,
a9deb8c6	205	uint64_t val, unsigned size)
70ae65f5	206	{
a9deb8c6	207	BMDMAState *bm = opaque;
f6c11d56	208	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
70ae65f5	209
a9deb8c6 AK	210	if (size != 1) {
	211	return;
	212	}
70ae65f5	213
4c3df0ec	214	#ifdef DEBUG_IDE
721da65c	215	printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
4c3df0ec JQ	216	#endif
4c3df0ec JQ	217	switch(addr & 3) {
50a48094	218	case 0:
a9deb8c6	219	bmdma_cmd_writeb(bm, val);
50a48094	220	break;
4c3df0ec	221	case 1:
f6c11d56 AF	222	pci_dev->config[MRDMODE] =
f6c11d56 AF	223	(pci_dev->config[MRDMODE] & ~0x30) \| (val & 0x30);
5bbc0a70	224	cmd646_update_dma_interrupts(pci_dev);
dab91a1e	225	cmd646_update_irq(pci_dev);
4c3df0ec JQ	226	break;
	227	case 2:
	228	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	229	break;
	230	case 3:
f6c11d56 AF	231	if (bm == &bm->pci_dev->bmdma[0]) {
	232	pci_dev->config[UDIDETCR0] = val;
	233	} else {
	234	pci_dev->config[UDIDETCR1] = val;
	235	}
4c3df0ec JQ	236	break;
	237	}
	238	}
	239
a348f108	240	static const MemoryRegionOps cmd646_bmdma_ops = {
a9deb8c6 AK	241	.read = bmdma_read,
	242	.write = bmdma_write,
	243	};
70ae65f5	244
a9deb8c6	245	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	246	{
a9deb8c6	247	BMDMAState *bm;
4c3df0ec JQ	248	int i;
4c3df0ec JQ	249
1437c94b	250	memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
4c3df0ec	251	for(i = 0;i < 2; i++) {
a9deb8c6	252	bm = &d->bmdma[i];
1437c94b	253	memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
a9deb8c6 AK	254	"cmd646-bmdma-bus", 4);
a9deb8c6 AK	255	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
1437c94b PB	256	memory_region_init_io(&bm->addr_ioport, OBJECT(d),
1437c94b PB	257	&bmdma_addr_ioport_ops, bm,
a9deb8c6 AK	258	"cmd646-bmdma-ioport", 4);
a9deb8c6 AK	259	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	260	}
	261	}
	262
dab91a1e	263	static void cmd646_update_irq(PCIDevice *pd)
4c3df0ec JQ	264	{
4c3df0ec JQ	265	int pci_level;
f6c11d56 AF	266
	267	pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
	268	!(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) \|\|
	269	((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
	270	!(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
9e64f8a3	271	pci_set_irq(pd, pci_level);
4c3df0ec JQ	272	}
	273
	274	/* the PCI irq level is the logical OR of the two channels */
	275	static void cmd646_set_irq(void *opaque, int channel, int level)
	276	{
	277	PCIIDEState *d = opaque;
f6c11d56	278	PCIDevice *pd = PCI_DEVICE(d);
4c3df0ec JQ	279	int irq_mask;
	280
	281	irq_mask = MRDMODE_INTR_CH0 << channel;
f6c11d56 AF	282	if (level) {
	283	pd->config[MRDMODE] \|= irq_mask;
	284	} else {
	285	pd->config[MRDMODE] &= ~irq_mask;
	286	}
5bbc0a70	287	cmd646_update_dma_interrupts(pd);
dab91a1e	288	cmd646_update_irq(pd);
4c3df0ec JQ	289	}
	290
	291	static void cmd646_reset(void *opaque)
	292	{
	293	PCIIDEState *d = opaque;
	294	unsigned int i;
	295
4a643563 BS	296	for (i = 0; i < 2; i++) {
4a643563 BS	297	ide_bus_reset(&d->bus[i]);
4a643563	298	}
4c3df0ec JQ	299	}
4c3df0ec JQ	300
1d113ef8 MCA	301	static uint32_t cmd646_pci_config_read(PCIDevice *d,
	302	uint32_t address, int len)
	303	{
	304	return pci_default_read_config(d, address, len);
	305	}
	306
	307	static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
	308	int l)
	309	{
	310	uint32_t i;
	311
	312	pci_default_write_config(d, addr, val, l);
	313
	314	for (i = addr; i < addr + l; i++) {
	315	switch (i) {
271dddd1 MCA	316	case CFR:
	317	case ARTTIM23:
	318	cmd646_update_udma_interrupts(d);
	319	break;
1d113ef8 MCA	320	case MRDMODE:
	321	cmd646_update_dma_interrupts(d);
	322	break;
	323	}
	324	}
	325
	326	cmd646_update_irq(d);
	327	}
	328
4c3df0ec	329	/* CMD646 PCI IDE controller */
9af21dbe	330	static void pci_cmd646_ide_realize(PCIDevice dev, Error *errp)
4c3df0ec	331	{
f6c11d56 AF	332	PCIIDEState *d = PCI_IDE(dev);
f6c11d56 AF	333	uint8_t *pci_conf = dev->config;
4c3df0ec	334	qemu_irq *irq;
61d9d6b0	335	int i;
4c3df0ec	336
409570a7	337	pci_conf[PCI_CLASS_PROG] = 0x8f;
4c3df0ec	338
58f16a7b	339	pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
4c3df0ec JQ	340	if (d->secondary) {
4c3df0ec JQ	341	/* XXX: if not enabled, really disable the seconday IDE controller */
58f16a7b	342	pci_conf[CNTRL] \|= CNTRL_EN_CH1; /* enable IDE1 */
4c3df0ec JQ	343	}
4c3df0ec JQ	344
1d113ef8	345	/* Set write-to-clear interrupt bits */
271dddd1 MCA	346	dev->wmask[CFR] = 0x0;
	347	dev->w1cmask[CFR] = CFR_INTR_CH0;
	348	dev->wmask[ARTTIM23] = 0x0;
	349	dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
1d113ef8 MCA	350	dev->wmask[MRDMODE] = 0x0;
	351	dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1;
	352
a9deb8c6 AK	353	setup_cmd646_bar(d, 0);
a9deb8c6 AK	354	setup_cmd646_bar(d, 1);
e824b2cc AK	355	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
	356	pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
	357	pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
	358	pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
a9deb8c6	359	bmdma_setup_bar(d);
e824b2cc	360	pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	361
409570a7 MT	362	/* TODO: RST# value should be 0 */
409570a7 MT	363	pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
4c3df0ec JQ	364
4c3df0ec JQ	365	irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
61d9d6b0	366	for (i = 0; i < 2; i++) {
c6baf942	367	ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
61d9d6b0 SH	368	ide_init2(&d->bus[i], irq[i]);
61d9d6b0 SH	369
a9deb8c6	370	bmdma_init(&d->bus[i], &d->bmdma[i], d);
f56b18c0	371	d->bmdma[i].bus = &d->bus[i];
f878c916	372	ide_register_restart_cb(&d->bus[i]);
61d9d6b0	373	}
4c3df0ec	374
f6c11d56	375	vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
4c3df0ec	376	qemu_register_reset(cmd646_reset, d);
4c3df0ec JQ	377	}
4c3df0ec JQ	378
f90c2bcd	379	static void pci_cmd646_ide_exitfn(PCIDevice *dev)
a9deb8c6	380	{
f6c11d56	381	PCIIDEState *d = PCI_IDE(dev);
a9deb8c6 AK	382	unsigned i;
	383
	384	for (i = 0; i < 2; ++i) {
	385	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
a9deb8c6	386	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
a9deb8c6	387	}
a9deb8c6 AK	388	}
a9deb8c6 AK	389
4c3df0ec JQ	390	void pci_cmd646_ide_init(PCIBus bus, DriveInfo *hd_table,
	391	int secondary_ide_enabled)
	392	{
	393	PCIDevice *dev;
	394
556cd098	395	dev = pci_create(bus, -1, "cmd646-ide");
4c3df0ec JQ	396	qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
	397	qdev_init_nofail(&dev->qdev);
	398
	399	pci_ide_create_devs(dev, hd_table);
	400	}
	401
40021f08 AL	402	static Property cmd646_ide_properties[] = {
	403	DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
	404	DEFINE_PROP_END_OF_LIST(),
	405	};
	406
	407	static void cmd646_ide_class_init(ObjectClass klass, void data)
	408	{
39bffca2	409	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	410	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	411
9af21dbe	412	k->realize = pci_cmd646_ide_realize;
40021f08 AL	413	k->exit = pci_cmd646_ide_exitfn;
	414	k->vendor_id = PCI_VENDOR_ID_CMD;
	415	k->device_id = PCI_DEVICE_ID_CMD_646;
	416	k->revision = 0x07;
	417	k->class_id = PCI_CLASS_STORAGE_IDE;
1d113ef8 MCA	418	k->config_read = cmd646_pci_config_read;
1d113ef8 MCA	419	k->config_write = cmd646_pci_config_write;
39bffca2	420	dc->props = cmd646_ide_properties;
74623e73	421	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
40021f08 AL	422	}
40021f08 AL	423
8c43a6f0	424	static const TypeInfo cmd646_ide_info = {
39bffca2	425	.name = "cmd646-ide",
f6c11d56	426	.parent = TYPE_PCI_IDE,
39bffca2	427	.class_init = cmd646_ide_class_init,
4c3df0ec JQ	428	};
4c3df0ec JQ	429
83f7d43a	430	static void cmd646_ide_register_types(void)
4c3df0ec	431	{
39bffca2	432	type_register_static(&cmd646_ide_info);
4c3df0ec	433	}
83f7d43a AF	434
83f7d43a AF	435	type_init(cmd646_ide_register_types)