[qemu.git] / hw / sun4m_iommu.c

/*
 * QEMU Sun4m iommu emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sun4m.h"
#include "sysbus.h"

/* debug iommu */
//#define DEBUG_IOMMU

#ifdef DEBUG_IOMMU
#define DPRINTF(fmt, ...)                                       \
    do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

/*
 * I/O MMU used by Sun4m systems
 *
 * Chipset docs:
 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
 */

#define IOMMU_NREGS         (4*4096/4)
#define IOMMU_CTRL          (0x0000 >> 2)
#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK     0x0000001d

#define IOMMU_BASE          (0x0004 >> 2)
#define IOMMU_BASE_MASK     0x07fffc00

#define IOMMU_TLBFLUSH      (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff

#define IOMMU_PGFLUSH       (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK  0xffffffff

#define IOMMU_AFSR          (0x1000 >> 2)
#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
                                          transaction */
#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
                                          12.8 us. */
#define IOMMU_AFSR_BE       0x10000000 /* Write access received error
                                          acknowledge */
#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
                                          hardware */
#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_AFSR_MASK     0xff0fffff

#define IOMMU_AFAR          (0x1004 >> 2)

#define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
#define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
#define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
#define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
#define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
#define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
#define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
#define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
#define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
#define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
#define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
#define IOMMU_AER_MASK      0x801f000f

#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
                                          bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
                                          produced by this device as pure
                                          physical. */
#define IOMMU_SBCFG_MASK    0x00010003

#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK    0x001f0000
#define IOMMU_MID           0x00000008

#define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
#define IOMMU_MASK_ID_MASK  0x00ffffff

#define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
#define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
                                          Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writeable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define IOMMU_PAGE_SHIFT    12
#define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
#define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)

typedef struct IOMMUState {
    SysBusDevice busdev;
    uint32_t regs[IOMMU_NREGS];
    target_phys_addr_t iostart;
    uint32_t version;
    qemu_irq irq;
} IOMMUState;

static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;
    uint32_t ret;

    saddr = addr >> 2;
    switch (saddr) {
    default:
        ret = s->regs[saddr];
        break;
    case IOMMU_AFAR:
    case IOMMU_AFSR:
        ret = s->regs[saddr];
        qemu_irq_lower(s->irq);
        break;
    }
    DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
    return ret;
}

static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;

    saddr = addr >> 2;
    DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
    switch (saddr) {
    case IOMMU_CTRL:
        switch (val & IOMMU_CTRL_RNGE) {
        case IOMMU_RNGE_16MB:
            s->iostart = 0xffffffffff000000ULL;
            break;
        case IOMMU_RNGE_32MB:
            s->iostart = 0xfffffffffe000000ULL;
            break;
        case IOMMU_RNGE_64MB:
            s->iostart = 0xfffffffffc000000ULL;
            break;
        case IOMMU_RNGE_128MB:
            s->iostart = 0xfffffffff8000000ULL;
            break;
        case IOMMU_RNGE_256MB:
            s->iostart = 0xfffffffff0000000ULL;
            break;
        case IOMMU_RNGE_512MB:
            s->iostart = 0xffffffffe0000000ULL;
            break;
        case IOMMU_RNGE_1GB:
            s->iostart = 0xffffffffc0000000ULL;
            break;
        default:
        case IOMMU_RNGE_2GB:
            s->iostart = 0xffffffff80000000ULL;
            break;
        }
        DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
        break;
    case IOMMU_BASE:
        s->regs[saddr] = val & IOMMU_BASE_MASK;
        break;
    case IOMMU_TLBFLUSH:
        DPRINTF("tlb flush %x\n", val);
        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
        break;
    case IOMMU_PGFLUSH:
        DPRINTF("page flush %x\n", val);
        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
        break;
    case IOMMU_AFAR:
        s->regs[saddr] = val;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_AER:
        s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
        break;
    case IOMMU_AFSR:
        s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_SBCFG0:
    case IOMMU_SBCFG1:
    case IOMMU_SBCFG2:
    case IOMMU_SBCFG3:
        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
        break;
    case IOMMU_ARBEN:
        // XXX implement SBus probing: fault when reading unmapped
        // addresses, fault cause and address stored to MMU/IOMMU
        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
        break;
    case IOMMU_MASK_ID:
        s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
        break;
    default:
        s->regs[saddr] = val;
        break;
    }
}

static CPUReadMemoryFunc * const iommu_mem_read[3] = {
    NULL,
    NULL,
    iommu_mem_readl,
};

static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
    NULL,
    NULL,
    iommu_mem_writel,
};

static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{
    uint32_t ret;
    target_phys_addr_t iopte;
#ifdef DEBUG_IOMMU
    target_phys_addr_t pa = addr;
#endif

    iopte = s->regs[IOMMU_BASE] << 4;
    addr &= ~s->iostart;
    iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
    cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
    tswap32s(&ret);
    DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
            ", *pte = %x\n", pa, iopte, ret);

    return ret;
}

static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
                                             uint32_t pte)
{
    target_phys_addr_t pa;

    pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
    DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
            " (iopte = %x)\n", addr, pa, pte);

    return pa;
}

static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
                           int is_write)
{
    DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
        IOMMU_AFSR_FAV;
    if (!is_write)
        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
    s->regs[IOMMU_AFAR] = addr;
    qemu_irq_raise(s->irq);
}

void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
                           uint8_t *buf, int len, int is_write)
{
    int l;
    uint32_t flags;
    target_phys_addr_t page, phys_addr;

    while (len > 0) {
        page = addr & IOMMU_PAGE_MASK;
        l = (page + IOMMU_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = iommu_page_get_flags(opaque, page);
        if (!(flags & IOPTE_VALID)) {
            iommu_bad_addr(opaque, page, is_write);
            return;
        }
        phys_addr = iommu_translate_pa(addr, flags);
        if (is_write) {
            if (!(flags & IOPTE_WRITE)) {
                iommu_bad_addr(opaque, page, is_write);
                return;
            }
            cpu_physical_memory_write(phys_addr, buf, l);
        } else {
            cpu_physical_memory_read(phys_addr, buf, l);
        }
        len -= l;
        buf += l;
        addr += l;
    }
}

static const VMStateDescription vmstate_iommu = {
    .name ="iommu",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
        VMSTATE_UINT64(iostart, IOMMUState),
        VMSTATE_END_OF_LIST()
    }
};

static void iommu_reset(DeviceState *d)
{
    IOMMUState *s = container_of(d, IOMMUState, busdev.qdev);

    memset(s->regs, 0, IOMMU_NREGS * 4);
    s->iostart = 0;
    s->regs[IOMMU_CTRL] = s->version;
    s->regs[IOMMU_ARBEN] = IOMMU_MID;
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
    s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
    s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
}

static int iommu_init1(SysBusDevice *dev)
{
    IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
    int io;

    sysbus_init_irq(dev, &s->irq);

    io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s);
    sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);

    return 0;
}

static SysBusDeviceInfo iommu_info = {
    .init = iommu_init1,
    .qdev.name  = "iommu",
    .qdev.size  = sizeof(IOMMUState),
    .qdev.vmsd  = &vmstate_iommu,
    .qdev.reset = iommu_reset,
    .qdev.props = (Property[]) {
        DEFINE_PROP_HEX32("version", IOMMUState, version, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void iommu_register_devices(void)
{
    sysbus_register_withprop(&iommu_info);
}

device_init(iommu_register_devices)
Commit	Line	Data
420557e8	1	/*
93c5a32f	2	* QEMU Sun4m iommu emulation
420557e8	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
5f750b2e	24
87ecb68b	25	#include "sun4m.h"
5f750b2e	26	#include "sysbus.h"
420557e8 FB	27
	28	/* debug iommu */
	29	//#define DEBUG_IOMMU
	30
66321a11	31	#ifdef DEBUG_IOMMU
001faf32 BS	32	#define DPRINTF(fmt, ...) \
001faf32 BS	33	do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
66321a11	34	#else
001faf32	35	#define DPRINTF(fmt, ...)
66321a11	36	#endif
420557e8	37
93c5a32f BS	38	/*
	39	* I/O MMU used by Sun4m systems
	40	*
	41	* Chipset docs:
	42	* "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
	43	* http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
	44	*/
	45
e5e38121	46	#define IOMMU_NREGS (4*4096/4)
4e3b1ea1	47	#define IOMMU_CTRL (0x0000 >> 2)
420557e8 FB	48	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
	49	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
	50	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	51	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	52	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	53	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	54	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	55	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	56	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	57	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	58	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	59	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
4e3b1ea1 FB	60	#define IOMMU_CTRL_MASK 0x0000001d
	61
	62	#define IOMMU_BASE (0x0004 >> 2)
	63	#define IOMMU_BASE_MASK 0x07fffc00
	64
	65	#define IOMMU_TLBFLUSH (0x0014 >> 2)
	66	#define IOMMU_TLBFLUSH_MASK 0xffffffff
	67
	68	#define IOMMU_PGFLUSH (0x0018 >> 2)
	69	#define IOMMU_PGFLUSH_MASK 0xffffffff
	70
225d4be7 BS	71	#define IOMMU_AFSR (0x1000 >> 2)
225d4be7 BS	72	#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
5ad6bb97 BS	73	#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
	74	transaction */
	75	#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
	76	12.8 us. */
	77	#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
	78	acknowledge */
225d4be7 BS	79	#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
225d4be7 BS	80	#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
5ad6bb97 BS	81	#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
5ad6bb97 BS	82	hardware */
225d4be7 BS	83	#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
	84	#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
	85	#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
c52428fc	86	#define IOMMU_AFSR_MASK 0xff0fffff
225d4be7 BS	87
	88	#define IOMMU_AFAR (0x1004 >> 2)
	89
7b169687 BS	90	#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
	91	#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
	92	#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
	93	#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
	94	#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
	95	#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
	96	#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
	97	#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
	98	#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
	99	#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
	100	#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
	101	#define IOMMU_AER_MASK 0x801f000f
	102
4e3b1ea1 FB	103	#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
	104	#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
	105	#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
	106	#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
5ad6bb97 BS	107	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
5ad6bb97 BS	108	bypass enabled */
4e3b1ea1 FB	109	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
	110	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
	111	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
f930d07e	112	produced by this device as pure
4e3b1ea1 FB	113	physical. */
	114	#define IOMMU_SBCFG_MASK 0x00010003
	115
	116	#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
	117	#define IOMMU_ARBEN_MASK 0x001f0000
	118	#define IOMMU_MID 0x00000008
420557e8	119
e5e38121 BS	120	#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
	121	#define IOMMU_MASK_ID_MASK 0x00ffffff
	122
	123	#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
	124	#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
	125
420557e8	126	/* The format of an iopte in the page tables */
498fbd8a	127	#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
5ad6bb97 BS	128	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
5ad6bb97 BS	129	Viking/MXCC) */
420557e8 FB	130	#define IOPTE_WRITE 0x00000004 /* Writeable */
	131	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
	132	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
	133
8b0de438 BS	134	#define IOMMU_PAGE_SHIFT 12
	135	#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
	136	#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
420557e8 FB	137
420557e8 FB	138	typedef struct IOMMUState {
5f750b2e	139	SysBusDevice busdev;
66321a11	140	uint32_t regs[IOMMU_NREGS];
c227f099	141	target_phys_addr_t iostart;
7fbfb139	142	uint32_t version;
ff403da6	143	qemu_irq irq;
420557e8 FB	144	} IOMMUState;
420557e8 FB	145
c227f099	146	static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
420557e8 FB	147	{
420557e8 FB	148	IOMMUState *s = opaque;
c227f099	149	target_phys_addr_t saddr;
ff403da6	150	uint32_t ret;
420557e8	151
8da3ff18	152	saddr = addr >> 2;
420557e8 FB	153	switch (saddr) {
420557e8 FB	154	default:
ff403da6 BS	155	ret = s->regs[saddr];
	156	break;
	157	case IOMMU_AFAR:
	158	case IOMMU_AFSR:
	159	ret = s->regs[saddr];
	160	qemu_irq_lower(s->irq);
f930d07e	161	break;
420557e8	162	}
ff403da6 BS	163	DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
ff403da6 BS	164	return ret;
420557e8 FB	165	}
420557e8 FB	166
c227f099	167	static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
5ad6bb97	168	uint32_t val)
420557e8 FB	169	{
420557e8 FB	170	IOMMUState *s = opaque;
c227f099	171	target_phys_addr_t saddr;
420557e8	172
8da3ff18	173	saddr = addr >> 2;
981a2e99	174	DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
420557e8	175	switch (saddr) {
4e3b1ea1	176	case IOMMU_CTRL:
f930d07e BS	177	switch (val & IOMMU_CTRL_RNGE) {
	178	case IOMMU_RNGE_16MB:
	179	s->iostart = 0xffffffffff000000ULL;
	180	break;
	181	case IOMMU_RNGE_32MB:
	182	s->iostart = 0xfffffffffe000000ULL;
	183	break;
	184	case IOMMU_RNGE_64MB:
	185	s->iostart = 0xfffffffffc000000ULL;
	186	break;
	187	case IOMMU_RNGE_128MB:
	188	s->iostart = 0xfffffffff8000000ULL;
	189	break;
	190	case IOMMU_RNGE_256MB:
	191	s->iostart = 0xfffffffff0000000ULL;
	192	break;
	193	case IOMMU_RNGE_512MB:
	194	s->iostart = 0xffffffffe0000000ULL;
	195	break;
	196	case IOMMU_RNGE_1GB:
	197	s->iostart = 0xffffffffc0000000ULL;
	198	break;
	199	default:
	200	case IOMMU_RNGE_2GB:
	201	s->iostart = 0xffffffff80000000ULL;
	202	break;
	203	}
	204	DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
7fbfb139	205	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) \| s->version);
f930d07e	206	break;
4e3b1ea1	207	case IOMMU_BASE:
f930d07e BS	208	s->regs[saddr] = val & IOMMU_BASE_MASK;
f930d07e BS	209	break;
4e3b1ea1	210	case IOMMU_TLBFLUSH:
f930d07e BS	211	DPRINTF("tlb flush %x\n", val);
	212	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
	213	break;
4e3b1ea1	214	case IOMMU_PGFLUSH:
f930d07e BS	215	DPRINTF("page flush %x\n", val);
	216	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
	217	break;
ff403da6 BS	218	case IOMMU_AFAR:
	219	s->regs[saddr] = val;
	220	qemu_irq_lower(s->irq);
	221	break;
7b169687 BS	222	case IOMMU_AER:
	223	s->regs[saddr] = (val & IOMMU_AER_MASK) \| IOMMU_AER_EN_P0_ARB;
	224	break;
c52428fc BS	225	case IOMMU_AFSR:
c52428fc BS	226	s->regs[saddr] = (val & IOMMU_AFSR_MASK) \| IOMMU_AFSR_RESV;
ff403da6	227	qemu_irq_lower(s->irq);
c52428fc	228	break;
4e3b1ea1 FB	229	case IOMMU_SBCFG0:
	230	case IOMMU_SBCFG1:
	231	case IOMMU_SBCFG2:
	232	case IOMMU_SBCFG3:
f930d07e BS	233	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
f930d07e BS	234	break;
4e3b1ea1 FB	235	case IOMMU_ARBEN:
	236	// XXX implement SBus probing: fault when reading unmapped
	237	// addresses, fault cause and address stored to MMU/IOMMU
f930d07e BS	238	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) \| IOMMU_MID;
f930d07e BS	239	break;
e5e38121 BS	240	case IOMMU_MASK_ID:
	241	s->regs[saddr] \|= val & IOMMU_MASK_ID_MASK;
	242	break;
420557e8	243	default:
f930d07e BS	244	s->regs[saddr] = val;
f930d07e BS	245	break;
420557e8 FB	246	}
	247	}
	248
d60efc6b	249	static CPUReadMemoryFunc * const iommu_mem_read[3] = {
7c560456 BS	250	NULL,
	251	NULL,
	252	iommu_mem_readl,
420557e8 FB	253	};
420557e8 FB	254
d60efc6b	255	static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
7c560456 BS	256	NULL,
	257	NULL,
	258	iommu_mem_writel,
420557e8 FB	259	};
420557e8 FB	260
c227f099	261	static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
420557e8	262	{
5e3b100b	263	uint32_t ret;
c227f099	264	target_phys_addr_t iopte;
981a2e99	265	#ifdef DEBUG_IOMMU
c227f099	266	target_phys_addr_t pa = addr;
981a2e99	267	#endif
420557e8	268
981a2e99	269	iopte = s->regs[IOMMU_BASE] << 4;
66321a11	270	addr &= ~s->iostart;
8b0de438	271	iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
5e3b100b	272	cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
748e4993	273	tswap32s(&ret);
5e3b100b BS	274	DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
5e3b100b BS	275	", *pte = %x\n", pa, iopte, ret);
981a2e99 BS	276
981a2e99 BS	277	return ret;
a917d384 PB	278	}
a917d384 PB	279
c227f099	280	static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
5dcb6b91	281	uint32_t pte)
a917d384	282	{
c227f099	283	target_phys_addr_t pa;
5dcb6b91	284
8b0de438	285	pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
5dcb6b91	286	DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
f368a3ce	287	" (iopte = %x)\n", addr, pa, pte);
a917d384	288
66321a11	289	return pa;
420557e8 FB	290	}
420557e8 FB	291
c227f099	292	static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
5ad6bb97	293	int is_write)
225d4be7 BS	294	{
225d4be7 BS	295	DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
5ad6bb97	296	s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR \| IOMMU_AFSR_LE \| IOMMU_AFSR_RESV \|
225d4be7 BS	297	IOMMU_AFSR_FAV;
	298	if (!is_write)
	299	s->regs[IOMMU_AFSR] \|= IOMMU_AFSR_RD;
	300	s->regs[IOMMU_AFAR] = addr;
ff403da6	301	qemu_irq_raise(s->irq);
225d4be7 BS	302	}
225d4be7 BS	303
c227f099	304	void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
67e999be	305	uint8_t *buf, int len, int is_write)
a917d384	306	{
5dcb6b91 BS	307	int l;
5dcb6b91 BS	308	uint32_t flags;
c227f099	309	target_phys_addr_t page, phys_addr;
a917d384 PB	310
a917d384 PB	311	while (len > 0) {
8b0de438 BS	312	page = addr & IOMMU_PAGE_MASK;
8b0de438 BS	313	l = (page + IOMMU_PAGE_SIZE) - addr;
a917d384 PB	314	if (l > len)
	315	l = len;
	316	flags = iommu_page_get_flags(opaque, page);
225d4be7 BS	317	if (!(flags & IOPTE_VALID)) {
225d4be7 BS	318	iommu_bad_addr(opaque, page, is_write);
a917d384	319	return;
225d4be7	320	}
22548760	321	phys_addr = iommu_translate_pa(addr, flags);
a917d384	322	if (is_write) {
225d4be7 BS	323	if (!(flags & IOPTE_WRITE)) {
225d4be7 BS	324	iommu_bad_addr(opaque, page, is_write);
a917d384	325	return;
225d4be7	326	}
a5cdf952	327	cpu_physical_memory_write(phys_addr, buf, l);
a917d384	328	} else {
a5cdf952	329	cpu_physical_memory_read(phys_addr, buf, l);
a917d384 PB	330	}
	331	len -= l;
	332	buf += l;
	333	addr += l;
	334	}
	335	}
	336
db3c9e08 BS	337	static const VMStateDescription vmstate_iommu = {
	338	.name ="iommu",
	339	.version_id = 2,
	340	.minimum_version_id = 2,
	341	.minimum_version_id_old = 2,
	342	.fields = (VMStateField []) {
	343	VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
	344	VMSTATE_UINT64(iostart, IOMMUState),
	345	VMSTATE_END_OF_LIST()
	346	}
	347	};
e80cfcfc	348
1a522e8a	349	static void iommu_reset(DeviceState *d)
e80cfcfc	350	{
1a522e8a	351	IOMMUState *s = container_of(d, IOMMUState, busdev.qdev);
e80cfcfc	352
66321a11	353	memset(s->regs, 0, IOMMU_NREGS * 4);
e80cfcfc	354	s->iostart = 0;
7fbfb139 BS	355	s->regs[IOMMU_CTRL] = s->version;
7fbfb139 BS	356	s->regs[IOMMU_ARBEN] = IOMMU_MID;
5ad6bb97	357	s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
7b169687	358	s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB \| IOMMU_AER_EN_P1_ARB;
e5e38121	359	s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
e80cfcfc FB	360	}
e80cfcfc FB	361
81a322d4	362	static int iommu_init1(SysBusDevice *dev)
5f750b2e BS	363	{
	364	IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
	365	int io;
420557e8	366
5f750b2e	367	sysbus_init_irq(dev, &s->irq);
420557e8	368
5f750b2e BS	369	io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s);
5f750b2e BS	370	sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);
3b46e624	371
81a322d4	372	return 0;
420557e8	373	}
5f750b2e BS	374
	375	static SysBusDeviceInfo iommu_info = {
	376	.init = iommu_init1,
	377	.qdev.name = "iommu",
	378	.qdev.size = sizeof(IOMMUState),
1a522e8a BS	379	.qdev.vmsd = &vmstate_iommu,
1a522e8a BS	380	.qdev.reset = iommu_reset,
ee6847d1	381	.qdev.props = (Property[]) {
668724a7 GH	382	DEFINE_PROP_HEX32("version", IOMMUState, version, 0),
668724a7 GH	383	DEFINE_PROP_END_OF_LIST(),
5f750b2e BS	384	}
	385	};
	386
	387	static void iommu_register_devices(void)
	388	{
	389	sysbus_register_withprop(&iommu_info);
	390	}
	391
	392	device_init(iommu_register_devices)