]>
Commit | Line | Data |
---|---|---|
8f2e8c07 KB |
1 | /* |
2 | * Optimizations for Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2010 Samsung Electronics. | |
5 | * Contributed by Kirill Batuzov <[email protected]> | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
757e725b | 26 | #include "qemu/osdep.h" |
dcb32f1d | 27 | #include "tcg/tcg-op.h" |
90163900 | 28 | #include "tcg-internal.h" |
8f2e8c07 | 29 | |
8f2e8c07 KB |
30 | #define CASE_OP_32_64(x) \ |
31 | glue(glue(case INDEX_op_, x), _i32): \ | |
32 | glue(glue(case INDEX_op_, x), _i64) | |
8f2e8c07 | 33 | |
170ba88f RH |
34 | #define CASE_OP_32_64_VEC(x) \ |
35 | glue(glue(case INDEX_op_, x), _i32): \ | |
36 | glue(glue(case INDEX_op_, x), _i64): \ | |
37 | glue(glue(case INDEX_op_, x), _vec) | |
38 | ||
6fcb98ed | 39 | typedef struct TempOptInfo { |
b41059dd | 40 | bool is_const; |
6349039d RH |
41 | TCGTemp *prev_copy; |
42 | TCGTemp *next_copy; | |
54795544 | 43 | uint64_t val; |
b1fde411 | 44 | uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */ |
6fcb98ed | 45 | } TempOptInfo; |
22613af4 | 46 | |
3b3f847d | 47 | typedef struct OptContext { |
dc84988a | 48 | TCGContext *tcg; |
d0ed5151 | 49 | TCGOp *prev_mb; |
3b3f847d | 50 | TCGTempSet temps_used; |
137f1f44 RH |
51 | |
52 | /* In flight values from optimization. */ | |
53 | uint64_t z_mask; | |
3b3f847d RH |
54 | } OptContext; |
55 | ||
6fcb98ed | 56 | static inline TempOptInfo *ts_info(TCGTemp *ts) |
d9c769c6 | 57 | { |
6349039d | 58 | return ts->state_ptr; |
d9c769c6 AJ |
59 | } |
60 | ||
6fcb98ed | 61 | static inline TempOptInfo *arg_info(TCGArg arg) |
d9c769c6 | 62 | { |
6349039d RH |
63 | return ts_info(arg_temp(arg)); |
64 | } | |
65 | ||
66 | static inline bool ts_is_const(TCGTemp *ts) | |
67 | { | |
68 | return ts_info(ts)->is_const; | |
69 | } | |
70 | ||
71 | static inline bool arg_is_const(TCGArg arg) | |
72 | { | |
73 | return ts_is_const(arg_temp(arg)); | |
74 | } | |
75 | ||
76 | static inline bool ts_is_copy(TCGTemp *ts) | |
77 | { | |
78 | return ts_info(ts)->next_copy != ts; | |
d9c769c6 AJ |
79 | } |
80 | ||
b41059dd | 81 | /* Reset TEMP's state, possibly removing the temp for the list of copies. */ |
6349039d RH |
82 | static void reset_ts(TCGTemp *ts) |
83 | { | |
6fcb98ed RH |
84 | TempOptInfo *ti = ts_info(ts); |
85 | TempOptInfo *pi = ts_info(ti->prev_copy); | |
86 | TempOptInfo *ni = ts_info(ti->next_copy); | |
6349039d RH |
87 | |
88 | ni->prev_copy = ti->prev_copy; | |
89 | pi->next_copy = ti->next_copy; | |
90 | ti->next_copy = ts; | |
91 | ti->prev_copy = ts; | |
92 | ti->is_const = false; | |
b1fde411 | 93 | ti->z_mask = -1; |
6349039d RH |
94 | } |
95 | ||
96 | static void reset_temp(TCGArg arg) | |
22613af4 | 97 | { |
6349039d | 98 | reset_ts(arg_temp(arg)); |
22613af4 KB |
99 | } |
100 | ||
1208d7dd | 101 | /* Initialize and activate a temporary. */ |
3b3f847d | 102 | static void init_ts_info(OptContext *ctx, TCGTemp *ts) |
1208d7dd | 103 | { |
6349039d | 104 | size_t idx = temp_idx(ts); |
8f17a975 | 105 | TempOptInfo *ti; |
6349039d | 106 | |
3b3f847d | 107 | if (test_bit(idx, ctx->temps_used.l)) { |
8f17a975 RH |
108 | return; |
109 | } | |
3b3f847d | 110 | set_bit(idx, ctx->temps_used.l); |
8f17a975 RH |
111 | |
112 | ti = ts->state_ptr; | |
113 | if (ti == NULL) { | |
114 | ti = tcg_malloc(sizeof(TempOptInfo)); | |
6349039d | 115 | ts->state_ptr = ti; |
8f17a975 RH |
116 | } |
117 | ||
118 | ti->next_copy = ts; | |
119 | ti->prev_copy = ts; | |
120 | if (ts->kind == TEMP_CONST) { | |
121 | ti->is_const = true; | |
122 | ti->val = ts->val; | |
b1fde411 | 123 | ti->z_mask = ts->val; |
8f17a975 RH |
124 | if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { |
125 | /* High bits of a 32-bit quantity are garbage. */ | |
b1fde411 | 126 | ti->z_mask |= ~0xffffffffull; |
c0522136 | 127 | } |
8f17a975 RH |
128 | } else { |
129 | ti->is_const = false; | |
b1fde411 | 130 | ti->z_mask = -1; |
1208d7dd AJ |
131 | } |
132 | } | |
133 | ||
6349039d | 134 | static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) |
e590d4e6 | 135 | { |
4c868ce6 | 136 | TCGTemp *i, *g, *l; |
e590d4e6 | 137 | |
4c868ce6 RH |
138 | /* If this is already readonly, we can't do better. */ |
139 | if (temp_readonly(ts)) { | |
6349039d | 140 | return ts; |
e590d4e6 AJ |
141 | } |
142 | ||
4c868ce6 | 143 | g = l = NULL; |
6349039d | 144 | for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { |
4c868ce6 | 145 | if (temp_readonly(i)) { |
e590d4e6 | 146 | return i; |
4c868ce6 RH |
147 | } else if (i->kind > ts->kind) { |
148 | if (i->kind == TEMP_GLOBAL) { | |
149 | g = i; | |
150 | } else if (i->kind == TEMP_LOCAL) { | |
151 | l = i; | |
e590d4e6 AJ |
152 | } |
153 | } | |
154 | } | |
155 | ||
4c868ce6 RH |
156 | /* If we didn't find a better representation, return the same temp. */ |
157 | return g ? g : l ? l : ts; | |
e590d4e6 AJ |
158 | } |
159 | ||
6349039d | 160 | static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) |
e590d4e6 | 161 | { |
6349039d | 162 | TCGTemp *i; |
e590d4e6 | 163 | |
6349039d | 164 | if (ts1 == ts2) { |
e590d4e6 AJ |
165 | return true; |
166 | } | |
167 | ||
6349039d | 168 | if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) { |
e590d4e6 AJ |
169 | return false; |
170 | } | |
171 | ||
6349039d RH |
172 | for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) { |
173 | if (i == ts2) { | |
e590d4e6 AJ |
174 | return true; |
175 | } | |
176 | } | |
177 | ||
178 | return false; | |
179 | } | |
180 | ||
6349039d RH |
181 | static bool args_are_copies(TCGArg arg1, TCGArg arg2) |
182 | { | |
183 | return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); | |
184 | } | |
185 | ||
6b99d5bf | 186 | static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) |
22613af4 | 187 | { |
6349039d RH |
188 | TCGTemp *dst_ts = arg_temp(dst); |
189 | TCGTemp *src_ts = arg_temp(src); | |
170ba88f | 190 | const TCGOpDef *def; |
6fcb98ed RH |
191 | TempOptInfo *di; |
192 | TempOptInfo *si; | |
b1fde411 | 193 | uint64_t z_mask; |
6349039d RH |
194 | TCGOpcode new_op; |
195 | ||
196 | if (ts_are_copies(dst_ts, src_ts)) { | |
dc84988a | 197 | tcg_op_remove(ctx->tcg, op); |
6b99d5bf | 198 | return true; |
5365718a AJ |
199 | } |
200 | ||
6349039d RH |
201 | reset_ts(dst_ts); |
202 | di = ts_info(dst_ts); | |
203 | si = ts_info(src_ts); | |
170ba88f RH |
204 | def = &tcg_op_defs[op->opc]; |
205 | if (def->flags & TCG_OPF_VECTOR) { | |
206 | new_op = INDEX_op_mov_vec; | |
207 | } else if (def->flags & TCG_OPF_64BIT) { | |
208 | new_op = INDEX_op_mov_i64; | |
209 | } else { | |
210 | new_op = INDEX_op_mov_i32; | |
211 | } | |
c45cb8bb | 212 | op->opc = new_op; |
170ba88f | 213 | /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ |
6349039d RH |
214 | op->args[0] = dst; |
215 | op->args[1] = src; | |
a62f6f56 | 216 | |
b1fde411 | 217 | z_mask = si->z_mask; |
24666baf RH |
218 | if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { |
219 | /* High bits of the destination are now garbage. */ | |
b1fde411 | 220 | z_mask |= ~0xffffffffull; |
24666baf | 221 | } |
b1fde411 | 222 | di->z_mask = z_mask; |
e590d4e6 | 223 | |
6349039d | 224 | if (src_ts->type == dst_ts->type) { |
6fcb98ed | 225 | TempOptInfo *ni = ts_info(si->next_copy); |
6349039d RH |
226 | |
227 | di->next_copy = si->next_copy; | |
228 | di->prev_copy = src_ts; | |
229 | ni->prev_copy = dst_ts; | |
230 | si->next_copy = dst_ts; | |
231 | di->is_const = si->is_const; | |
232 | di->val = si->val; | |
233 | } | |
6b99d5bf | 234 | return true; |
22613af4 KB |
235 | } |
236 | ||
6b99d5bf | 237 | static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, |
dc84988a | 238 | TCGArg dst, uint64_t val) |
8fe35e04 RH |
239 | { |
240 | const TCGOpDef *def = &tcg_op_defs[op->opc]; | |
241 | TCGType type; | |
242 | TCGTemp *tv; | |
243 | ||
244 | if (def->flags & TCG_OPF_VECTOR) { | |
245 | type = TCGOP_VECL(op) + TCG_TYPE_V64; | |
246 | } else if (def->flags & TCG_OPF_64BIT) { | |
247 | type = TCG_TYPE_I64; | |
248 | } else { | |
249 | type = TCG_TYPE_I32; | |
250 | } | |
251 | ||
252 | /* Convert movi to mov with constant temp. */ | |
253 | tv = tcg_constant_internal(type, val); | |
3b3f847d | 254 | init_ts_info(ctx, tv); |
6b99d5bf | 255 | return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); |
8fe35e04 RH |
256 | } |
257 | ||
54795544 | 258 | static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) |
53108fb5 | 259 | { |
03271524 RH |
260 | uint64_t l64, h64; |
261 | ||
53108fb5 KB |
262 | switch (op) { |
263 | CASE_OP_32_64(add): | |
264 | return x + y; | |
265 | ||
266 | CASE_OP_32_64(sub): | |
267 | return x - y; | |
268 | ||
269 | CASE_OP_32_64(mul): | |
270 | return x * y; | |
271 | ||
9a81090b KB |
272 | CASE_OP_32_64(and): |
273 | return x & y; | |
274 | ||
275 | CASE_OP_32_64(or): | |
276 | return x | y; | |
277 | ||
278 | CASE_OP_32_64(xor): | |
279 | return x ^ y; | |
280 | ||
55c0975c | 281 | case INDEX_op_shl_i32: |
50c5c4d1 | 282 | return (uint32_t)x << (y & 31); |
55c0975c | 283 | |
55c0975c | 284 | case INDEX_op_shl_i64: |
50c5c4d1 | 285 | return (uint64_t)x << (y & 63); |
55c0975c KB |
286 | |
287 | case INDEX_op_shr_i32: | |
50c5c4d1 | 288 | return (uint32_t)x >> (y & 31); |
55c0975c | 289 | |
55c0975c | 290 | case INDEX_op_shr_i64: |
50c5c4d1 | 291 | return (uint64_t)x >> (y & 63); |
55c0975c KB |
292 | |
293 | case INDEX_op_sar_i32: | |
50c5c4d1 | 294 | return (int32_t)x >> (y & 31); |
55c0975c | 295 | |
55c0975c | 296 | case INDEX_op_sar_i64: |
50c5c4d1 | 297 | return (int64_t)x >> (y & 63); |
55c0975c KB |
298 | |
299 | case INDEX_op_rotr_i32: | |
50c5c4d1 | 300 | return ror32(x, y & 31); |
55c0975c | 301 | |
55c0975c | 302 | case INDEX_op_rotr_i64: |
50c5c4d1 | 303 | return ror64(x, y & 63); |
55c0975c KB |
304 | |
305 | case INDEX_op_rotl_i32: | |
50c5c4d1 | 306 | return rol32(x, y & 31); |
55c0975c | 307 | |
55c0975c | 308 | case INDEX_op_rotl_i64: |
50c5c4d1 | 309 | return rol64(x, y & 63); |
25c4d9cc RH |
310 | |
311 | CASE_OP_32_64(not): | |
a640f031 | 312 | return ~x; |
25c4d9cc | 313 | |
cb25c80a RH |
314 | CASE_OP_32_64(neg): |
315 | return -x; | |
316 | ||
317 | CASE_OP_32_64(andc): | |
318 | return x & ~y; | |
319 | ||
320 | CASE_OP_32_64(orc): | |
321 | return x | ~y; | |
322 | ||
323 | CASE_OP_32_64(eqv): | |
324 | return ~(x ^ y); | |
325 | ||
326 | CASE_OP_32_64(nand): | |
327 | return ~(x & y); | |
328 | ||
329 | CASE_OP_32_64(nor): | |
330 | return ~(x | y); | |
331 | ||
0e28d006 RH |
332 | case INDEX_op_clz_i32: |
333 | return (uint32_t)x ? clz32(x) : y; | |
334 | ||
335 | case INDEX_op_clz_i64: | |
336 | return x ? clz64(x) : y; | |
337 | ||
338 | case INDEX_op_ctz_i32: | |
339 | return (uint32_t)x ? ctz32(x) : y; | |
340 | ||
341 | case INDEX_op_ctz_i64: | |
342 | return x ? ctz64(x) : y; | |
343 | ||
a768e4e9 RH |
344 | case INDEX_op_ctpop_i32: |
345 | return ctpop32(x); | |
346 | ||
347 | case INDEX_op_ctpop_i64: | |
348 | return ctpop64(x); | |
349 | ||
25c4d9cc | 350 | CASE_OP_32_64(ext8s): |
a640f031 | 351 | return (int8_t)x; |
25c4d9cc RH |
352 | |
353 | CASE_OP_32_64(ext16s): | |
a640f031 | 354 | return (int16_t)x; |
25c4d9cc RH |
355 | |
356 | CASE_OP_32_64(ext8u): | |
a640f031 | 357 | return (uint8_t)x; |
25c4d9cc RH |
358 | |
359 | CASE_OP_32_64(ext16u): | |
a640f031 KB |
360 | return (uint16_t)x; |
361 | ||
6498594c | 362 | CASE_OP_32_64(bswap16): |
0b76ff8f RH |
363 | x = bswap16(x); |
364 | return y & TCG_BSWAP_OS ? (int16_t)x : x; | |
6498594c RH |
365 | |
366 | CASE_OP_32_64(bswap32): | |
0b76ff8f RH |
367 | x = bswap32(x); |
368 | return y & TCG_BSWAP_OS ? (int32_t)x : x; | |
6498594c RH |
369 | |
370 | case INDEX_op_bswap64_i64: | |
371 | return bswap64(x); | |
372 | ||
8bcb5c8f | 373 | case INDEX_op_ext_i32_i64: |
a640f031 KB |
374 | case INDEX_op_ext32s_i64: |
375 | return (int32_t)x; | |
376 | ||
8bcb5c8f | 377 | case INDEX_op_extu_i32_i64: |
609ad705 | 378 | case INDEX_op_extrl_i64_i32: |
a640f031 KB |
379 | case INDEX_op_ext32u_i64: |
380 | return (uint32_t)x; | |
a640f031 | 381 | |
609ad705 RH |
382 | case INDEX_op_extrh_i64_i32: |
383 | return (uint64_t)x >> 32; | |
384 | ||
03271524 RH |
385 | case INDEX_op_muluh_i32: |
386 | return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32; | |
387 | case INDEX_op_mulsh_i32: | |
388 | return ((int64_t)(int32_t)x * (int32_t)y) >> 32; | |
389 | ||
390 | case INDEX_op_muluh_i64: | |
391 | mulu64(&l64, &h64, x, y); | |
392 | return h64; | |
393 | case INDEX_op_mulsh_i64: | |
394 | muls64(&l64, &h64, x, y); | |
395 | return h64; | |
396 | ||
01547f7f RH |
397 | case INDEX_op_div_i32: |
398 | /* Avoid crashing on divide by zero, otherwise undefined. */ | |
399 | return (int32_t)x / ((int32_t)y ? : 1); | |
400 | case INDEX_op_divu_i32: | |
401 | return (uint32_t)x / ((uint32_t)y ? : 1); | |
402 | case INDEX_op_div_i64: | |
403 | return (int64_t)x / ((int64_t)y ? : 1); | |
404 | case INDEX_op_divu_i64: | |
405 | return (uint64_t)x / ((uint64_t)y ? : 1); | |
406 | ||
407 | case INDEX_op_rem_i32: | |
408 | return (int32_t)x % ((int32_t)y ? : 1); | |
409 | case INDEX_op_remu_i32: | |
410 | return (uint32_t)x % ((uint32_t)y ? : 1); | |
411 | case INDEX_op_rem_i64: | |
412 | return (int64_t)x % ((int64_t)y ? : 1); | |
413 | case INDEX_op_remu_i64: | |
414 | return (uint64_t)x % ((uint64_t)y ? : 1); | |
415 | ||
53108fb5 KB |
416 | default: |
417 | fprintf(stderr, | |
418 | "Unrecognized operation %d in do_constant_folding.\n", op); | |
419 | tcg_abort(); | |
420 | } | |
421 | } | |
422 | ||
54795544 | 423 | static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y) |
53108fb5 | 424 | { |
170ba88f | 425 | const TCGOpDef *def = &tcg_op_defs[op]; |
54795544 | 426 | uint64_t res = do_constant_folding_2(op, x, y); |
170ba88f | 427 | if (!(def->flags & TCG_OPF_64BIT)) { |
29f3ff8d | 428 | res = (int32_t)res; |
53108fb5 | 429 | } |
53108fb5 KB |
430 | return res; |
431 | } | |
432 | ||
9519da7e RH |
433 | static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c) |
434 | { | |
435 | switch (c) { | |
436 | case TCG_COND_EQ: | |
437 | return x == y; | |
438 | case TCG_COND_NE: | |
439 | return x != y; | |
440 | case TCG_COND_LT: | |
441 | return (int32_t)x < (int32_t)y; | |
442 | case TCG_COND_GE: | |
443 | return (int32_t)x >= (int32_t)y; | |
444 | case TCG_COND_LE: | |
445 | return (int32_t)x <= (int32_t)y; | |
446 | case TCG_COND_GT: | |
447 | return (int32_t)x > (int32_t)y; | |
448 | case TCG_COND_LTU: | |
449 | return x < y; | |
450 | case TCG_COND_GEU: | |
451 | return x >= y; | |
452 | case TCG_COND_LEU: | |
453 | return x <= y; | |
454 | case TCG_COND_GTU: | |
455 | return x > y; | |
456 | default: | |
457 | tcg_abort(); | |
458 | } | |
459 | } | |
460 | ||
461 | static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c) | |
462 | { | |
463 | switch (c) { | |
464 | case TCG_COND_EQ: | |
465 | return x == y; | |
466 | case TCG_COND_NE: | |
467 | return x != y; | |
468 | case TCG_COND_LT: | |
469 | return (int64_t)x < (int64_t)y; | |
470 | case TCG_COND_GE: | |
471 | return (int64_t)x >= (int64_t)y; | |
472 | case TCG_COND_LE: | |
473 | return (int64_t)x <= (int64_t)y; | |
474 | case TCG_COND_GT: | |
475 | return (int64_t)x > (int64_t)y; | |
476 | case TCG_COND_LTU: | |
477 | return x < y; | |
478 | case TCG_COND_GEU: | |
479 | return x >= y; | |
480 | case TCG_COND_LEU: | |
481 | return x <= y; | |
482 | case TCG_COND_GTU: | |
483 | return x > y; | |
484 | default: | |
485 | tcg_abort(); | |
486 | } | |
487 | } | |
488 | ||
489 | static bool do_constant_folding_cond_eq(TCGCond c) | |
490 | { | |
491 | switch (c) { | |
492 | case TCG_COND_GT: | |
493 | case TCG_COND_LTU: | |
494 | case TCG_COND_LT: | |
495 | case TCG_COND_GTU: | |
496 | case TCG_COND_NE: | |
497 | return 0; | |
498 | case TCG_COND_GE: | |
499 | case TCG_COND_GEU: | |
500 | case TCG_COND_LE: | |
501 | case TCG_COND_LEU: | |
502 | case TCG_COND_EQ: | |
503 | return 1; | |
504 | default: | |
505 | tcg_abort(); | |
506 | } | |
507 | } | |
508 | ||
8d57bf1e RH |
509 | /* |
510 | * Return -1 if the condition can't be simplified, | |
511 | * and the result of the condition (0 or 1) if it can. | |
512 | */ | |
513 | static int do_constant_folding_cond(TCGOpcode op, TCGArg x, | |
514 | TCGArg y, TCGCond c) | |
f8dd19e5 | 515 | { |
54795544 RH |
516 | uint64_t xv = arg_info(x)->val; |
517 | uint64_t yv = arg_info(y)->val; | |
518 | ||
6349039d | 519 | if (arg_is_const(x) && arg_is_const(y)) { |
170ba88f RH |
520 | const TCGOpDef *def = &tcg_op_defs[op]; |
521 | tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR)); | |
522 | if (def->flags & TCG_OPF_64BIT) { | |
6349039d | 523 | return do_constant_folding_cond_64(xv, yv, c); |
170ba88f RH |
524 | } else { |
525 | return do_constant_folding_cond_32(xv, yv, c); | |
b336ceb6 | 526 | } |
6349039d | 527 | } else if (args_are_copies(x, y)) { |
9519da7e | 528 | return do_constant_folding_cond_eq(c); |
6349039d | 529 | } else if (arg_is_const(y) && yv == 0) { |
b336ceb6 | 530 | switch (c) { |
f8dd19e5 | 531 | case TCG_COND_LTU: |
b336ceb6 | 532 | return 0; |
f8dd19e5 | 533 | case TCG_COND_GEU: |
b336ceb6 AJ |
534 | return 1; |
535 | default: | |
8d57bf1e | 536 | return -1; |
f8dd19e5 | 537 | } |
f8dd19e5 | 538 | } |
8d57bf1e | 539 | return -1; |
f8dd19e5 AJ |
540 | } |
541 | ||
8d57bf1e RH |
542 | /* |
543 | * Return -1 if the condition can't be simplified, | |
544 | * and the result of the condition (0 or 1) if it can. | |
545 | */ | |
546 | static int do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) | |
6c4382f8 RH |
547 | { |
548 | TCGArg al = p1[0], ah = p1[1]; | |
549 | TCGArg bl = p2[0], bh = p2[1]; | |
550 | ||
6349039d RH |
551 | if (arg_is_const(bl) && arg_is_const(bh)) { |
552 | tcg_target_ulong blv = arg_info(bl)->val; | |
553 | tcg_target_ulong bhv = arg_info(bh)->val; | |
554 | uint64_t b = deposit64(blv, 32, 32, bhv); | |
6c4382f8 | 555 | |
6349039d RH |
556 | if (arg_is_const(al) && arg_is_const(ah)) { |
557 | tcg_target_ulong alv = arg_info(al)->val; | |
558 | tcg_target_ulong ahv = arg_info(ah)->val; | |
559 | uint64_t a = deposit64(alv, 32, 32, ahv); | |
6c4382f8 RH |
560 | return do_constant_folding_cond_64(a, b, c); |
561 | } | |
562 | if (b == 0) { | |
563 | switch (c) { | |
564 | case TCG_COND_LTU: | |
565 | return 0; | |
566 | case TCG_COND_GEU: | |
567 | return 1; | |
568 | default: | |
569 | break; | |
570 | } | |
571 | } | |
572 | } | |
6349039d | 573 | if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { |
6c4382f8 RH |
574 | return do_constant_folding_cond_eq(c); |
575 | } | |
8d57bf1e | 576 | return -1; |
6c4382f8 RH |
577 | } |
578 | ||
24c9ae4e RH |
579 | static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) |
580 | { | |
581 | TCGArg a1 = *p1, a2 = *p2; | |
582 | int sum = 0; | |
6349039d RH |
583 | sum += arg_is_const(a1); |
584 | sum -= arg_is_const(a2); | |
24c9ae4e RH |
585 | |
586 | /* Prefer the constant in second argument, and then the form | |
587 | op a, a, b, which is better handled on non-RISC hosts. */ | |
588 | if (sum > 0 || (sum == 0 && dest == a2)) { | |
589 | *p1 = a2; | |
590 | *p2 = a1; | |
591 | return true; | |
592 | } | |
593 | return false; | |
594 | } | |
595 | ||
0bfcb865 RH |
596 | static bool swap_commutative2(TCGArg *p1, TCGArg *p2) |
597 | { | |
598 | int sum = 0; | |
6349039d RH |
599 | sum += arg_is_const(p1[0]); |
600 | sum += arg_is_const(p1[1]); | |
601 | sum -= arg_is_const(p2[0]); | |
602 | sum -= arg_is_const(p2[1]); | |
0bfcb865 RH |
603 | if (sum > 0) { |
604 | TCGArg t; | |
605 | t = p1[0], p1[0] = p2[0], p2[0] = t; | |
606 | t = p1[1], p1[1] = p2[1], p2[1] = t; | |
607 | return true; | |
608 | } | |
609 | return false; | |
610 | } | |
611 | ||
e2577ea2 RH |
612 | static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args) |
613 | { | |
614 | for (int i = 0; i < nb_args; i++) { | |
615 | TCGTemp *ts = arg_temp(op->args[i]); | |
616 | if (ts) { | |
617 | init_ts_info(ctx, ts); | |
618 | } | |
619 | } | |
620 | } | |
621 | ||
8774dded RH |
622 | static void copy_propagate(OptContext *ctx, TCGOp *op, |
623 | int nb_oargs, int nb_iargs) | |
624 | { | |
625 | TCGContext *s = ctx->tcg; | |
626 | ||
627 | for (int i = nb_oargs; i < nb_oargs + nb_iargs; i++) { | |
628 | TCGTemp *ts = arg_temp(op->args[i]); | |
629 | if (ts && ts_is_copy(ts)) { | |
630 | op->args[i] = temp_arg(find_better_copy(s, ts)); | |
631 | } | |
632 | } | |
633 | } | |
634 | ||
137f1f44 RH |
635 | static void finish_folding(OptContext *ctx, TCGOp *op) |
636 | { | |
637 | const TCGOpDef *def = &tcg_op_defs[op->opc]; | |
638 | int i, nb_oargs; | |
639 | ||
640 | /* | |
641 | * For an opcode that ends a BB, reset all temp data. | |
642 | * We do no cross-BB optimization. | |
643 | */ | |
644 | if (def->flags & TCG_OPF_BB_END) { | |
645 | memset(&ctx->temps_used, 0, sizeof(ctx->temps_used)); | |
646 | ctx->prev_mb = NULL; | |
647 | return; | |
648 | } | |
649 | ||
650 | nb_oargs = def->nb_oargs; | |
651 | for (i = 0; i < nb_oargs; i++) { | |
652 | reset_temp(op->args[i]); | |
653 | /* | |
654 | * Save the corresponding known-zero bits mask for the | |
655 | * first output argument (only one supported so far). | |
656 | */ | |
657 | if (i == 0) { | |
658 | arg_info(op->args[i])->z_mask = ctx->z_mask; | |
659 | } | |
660 | } | |
661 | } | |
662 | ||
5cf32be7 RH |
663 | static bool fold_call(OptContext *ctx, TCGOp *op) |
664 | { | |
665 | TCGContext *s = ctx->tcg; | |
666 | int nb_oargs = TCGOP_CALLO(op); | |
667 | int nb_iargs = TCGOP_CALLI(op); | |
668 | int flags, i; | |
669 | ||
670 | init_arguments(ctx, op, nb_oargs + nb_iargs); | |
671 | copy_propagate(ctx, op, nb_oargs, nb_iargs); | |
672 | ||
673 | /* If the function reads or writes globals, reset temp data. */ | |
674 | flags = tcg_call_flags(op); | |
675 | if (!(flags & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { | |
676 | int nb_globals = s->nb_globals; | |
677 | ||
678 | for (i = 0; i < nb_globals; i++) { | |
679 | if (test_bit(i, ctx->temps_used.l)) { | |
680 | reset_ts(&ctx->tcg->temps[i]); | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | /* Reset temp data for outputs. */ | |
686 | for (i = 0; i < nb_oargs; i++) { | |
687 | reset_temp(op->args[i]); | |
688 | } | |
689 | ||
690 | /* Stop optimizing MB across calls. */ | |
691 | ctx->prev_mb = NULL; | |
692 | return true; | |
693 | } | |
694 | ||
22613af4 | 695 | /* Propagate constants and copies, fold constant expressions. */ |
36e60ef6 | 696 | void tcg_optimize(TCGContext *s) |
8f2e8c07 | 697 | { |
5cf32be7 | 698 | int nb_temps, i; |
d0ed5151 | 699 | TCGOp *op, *op_next; |
dc84988a | 700 | OptContext ctx = { .tcg = s }; |
5d8f5363 | 701 | |
22613af4 KB |
702 | /* Array VALS has an element for each temp. |
703 | If this temp holds a constant then its value is kept in VALS' element. | |
e590d4e6 AJ |
704 | If this temp is a copy of other ones then the other copies are |
705 | available through the doubly linked circular list. */ | |
8f2e8c07 KB |
706 | |
707 | nb_temps = s->nb_temps; | |
8f17a975 RH |
708 | for (i = 0; i < nb_temps; ++i) { |
709 | s->temps[i].state_ptr = NULL; | |
710 | } | |
8f2e8c07 | 711 | |
15fa08f8 | 712 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { |
b1fde411 | 713 | uint64_t z_mask, partmask, affected, tmp; |
c45cb8bb | 714 | TCGOpcode opc = op->opc; |
5cf32be7 | 715 | const TCGOpDef *def; |
c45cb8bb | 716 | |
5cf32be7 | 717 | /* Calls are special. */ |
c45cb8bb | 718 | if (opc == INDEX_op_call) { |
5cf32be7 RH |
719 | fold_call(&ctx, op); |
720 | continue; | |
cf066674 | 721 | } |
5cf32be7 RH |
722 | |
723 | def = &tcg_op_defs[opc]; | |
ec5d4cbe RH |
724 | init_arguments(&ctx, op, def->nb_oargs + def->nb_iargs); |
725 | copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs); | |
22613af4 | 726 | |
53108fb5 | 727 | /* For commutative operations make constant second argument */ |
c45cb8bb | 728 | switch (opc) { |
170ba88f RH |
729 | CASE_OP_32_64_VEC(add): |
730 | CASE_OP_32_64_VEC(mul): | |
731 | CASE_OP_32_64_VEC(and): | |
732 | CASE_OP_32_64_VEC(or): | |
733 | CASE_OP_32_64_VEC(xor): | |
cb25c80a RH |
734 | CASE_OP_32_64(eqv): |
735 | CASE_OP_32_64(nand): | |
736 | CASE_OP_32_64(nor): | |
03271524 RH |
737 | CASE_OP_32_64(muluh): |
738 | CASE_OP_32_64(mulsh): | |
acd93701 | 739 | swap_commutative(op->args[0], &op->args[1], &op->args[2]); |
53108fb5 | 740 | break; |
65a7cce1 | 741 | CASE_OP_32_64(brcond): |
acd93701 RH |
742 | if (swap_commutative(-1, &op->args[0], &op->args[1])) { |
743 | op->args[2] = tcg_swap_cond(op->args[2]); | |
65a7cce1 AJ |
744 | } |
745 | break; | |
746 | CASE_OP_32_64(setcond): | |
acd93701 RH |
747 | if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { |
748 | op->args[3] = tcg_swap_cond(op->args[3]); | |
65a7cce1 AJ |
749 | } |
750 | break; | |
fa01a208 | 751 | CASE_OP_32_64(movcond): |
acd93701 RH |
752 | if (swap_commutative(-1, &op->args[1], &op->args[2])) { |
753 | op->args[5] = tcg_swap_cond(op->args[5]); | |
5d8f5363 RH |
754 | } |
755 | /* For movcond, we canonicalize the "false" input reg to match | |
756 | the destination reg so that the tcg backend can implement | |
757 | a "move if true" operation. */ | |
acd93701 RH |
758 | if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { |
759 | op->args[5] = tcg_invert_cond(op->args[5]); | |
fa01a208 | 760 | } |
1e484e61 | 761 | break; |
d7156f7c | 762 | CASE_OP_32_64(add2): |
acd93701 RH |
763 | swap_commutative(op->args[0], &op->args[2], &op->args[4]); |
764 | swap_commutative(op->args[1], &op->args[3], &op->args[5]); | |
1e484e61 | 765 | break; |
d7156f7c | 766 | CASE_OP_32_64(mulu2): |
4d3203fd | 767 | CASE_OP_32_64(muls2): |
acd93701 | 768 | swap_commutative(op->args[0], &op->args[2], &op->args[3]); |
1414968a | 769 | break; |
0bfcb865 | 770 | case INDEX_op_brcond2_i32: |
acd93701 RH |
771 | if (swap_commutative2(&op->args[0], &op->args[2])) { |
772 | op->args[4] = tcg_swap_cond(op->args[4]); | |
0bfcb865 RH |
773 | } |
774 | break; | |
775 | case INDEX_op_setcond2_i32: | |
acd93701 RH |
776 | if (swap_commutative2(&op->args[1], &op->args[3])) { |
777 | op->args[5] = tcg_swap_cond(op->args[5]); | |
0bfcb865 RH |
778 | } |
779 | break; | |
53108fb5 KB |
780 | default: |
781 | break; | |
782 | } | |
783 | ||
2d497542 RH |
784 | /* Simplify expressions for "shift/rot r, 0, a => movi r, 0", |
785 | and "sub r, 0, a => neg r, a" case. */ | |
c45cb8bb | 786 | switch (opc) { |
01ee5282 AJ |
787 | CASE_OP_32_64(shl): |
788 | CASE_OP_32_64(shr): | |
789 | CASE_OP_32_64(sar): | |
790 | CASE_OP_32_64(rotl): | |
791 | CASE_OP_32_64(rotr): | |
6349039d RH |
792 | if (arg_is_const(op->args[1]) |
793 | && arg_info(op->args[1])->val == 0) { | |
dc84988a | 794 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
01ee5282 AJ |
795 | continue; |
796 | } | |
797 | break; | |
170ba88f | 798 | CASE_OP_32_64_VEC(sub): |
2d497542 RH |
799 | { |
800 | TCGOpcode neg_op; | |
801 | bool have_neg; | |
802 | ||
6349039d | 803 | if (arg_is_const(op->args[2])) { |
2d497542 RH |
804 | /* Proceed with possible constant folding. */ |
805 | break; | |
806 | } | |
c45cb8bb | 807 | if (opc == INDEX_op_sub_i32) { |
2d497542 RH |
808 | neg_op = INDEX_op_neg_i32; |
809 | have_neg = TCG_TARGET_HAS_neg_i32; | |
170ba88f | 810 | } else if (opc == INDEX_op_sub_i64) { |
2d497542 RH |
811 | neg_op = INDEX_op_neg_i64; |
812 | have_neg = TCG_TARGET_HAS_neg_i64; | |
ac383dde RH |
813 | } else if (TCG_TARGET_HAS_neg_vec) { |
814 | TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64; | |
815 | unsigned vece = TCGOP_VECE(op); | |
170ba88f | 816 | neg_op = INDEX_op_neg_vec; |
ac383dde RH |
817 | have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0; |
818 | } else { | |
819 | break; | |
2d497542 RH |
820 | } |
821 | if (!have_neg) { | |
822 | break; | |
823 | } | |
6349039d RH |
824 | if (arg_is_const(op->args[1]) |
825 | && arg_info(op->args[1])->val == 0) { | |
c45cb8bb | 826 | op->opc = neg_op; |
acd93701 RH |
827 | reset_temp(op->args[0]); |
828 | op->args[1] = op->args[2]; | |
2d497542 RH |
829 | continue; |
830 | } | |
831 | } | |
832 | break; | |
170ba88f | 833 | CASE_OP_32_64_VEC(xor): |
e201b564 | 834 | CASE_OP_32_64(nand): |
6349039d RH |
835 | if (!arg_is_const(op->args[1]) |
836 | && arg_is_const(op->args[2]) | |
837 | && arg_info(op->args[2])->val == -1) { | |
e201b564 RH |
838 | i = 1; |
839 | goto try_not; | |
840 | } | |
841 | break; | |
842 | CASE_OP_32_64(nor): | |
6349039d RH |
843 | if (!arg_is_const(op->args[1]) |
844 | && arg_is_const(op->args[2]) | |
845 | && arg_info(op->args[2])->val == 0) { | |
e201b564 RH |
846 | i = 1; |
847 | goto try_not; | |
848 | } | |
849 | break; | |
170ba88f | 850 | CASE_OP_32_64_VEC(andc): |
6349039d RH |
851 | if (!arg_is_const(op->args[2]) |
852 | && arg_is_const(op->args[1]) | |
853 | && arg_info(op->args[1])->val == -1) { | |
e201b564 RH |
854 | i = 2; |
855 | goto try_not; | |
856 | } | |
857 | break; | |
170ba88f | 858 | CASE_OP_32_64_VEC(orc): |
e201b564 | 859 | CASE_OP_32_64(eqv): |
6349039d RH |
860 | if (!arg_is_const(op->args[2]) |
861 | && arg_is_const(op->args[1]) | |
862 | && arg_info(op->args[1])->val == 0) { | |
e201b564 RH |
863 | i = 2; |
864 | goto try_not; | |
865 | } | |
866 | break; | |
867 | try_not: | |
868 | { | |
869 | TCGOpcode not_op; | |
870 | bool have_not; | |
871 | ||
170ba88f RH |
872 | if (def->flags & TCG_OPF_VECTOR) { |
873 | not_op = INDEX_op_not_vec; | |
874 | have_not = TCG_TARGET_HAS_not_vec; | |
875 | } else if (def->flags & TCG_OPF_64BIT) { | |
e201b564 RH |
876 | not_op = INDEX_op_not_i64; |
877 | have_not = TCG_TARGET_HAS_not_i64; | |
878 | } else { | |
879 | not_op = INDEX_op_not_i32; | |
880 | have_not = TCG_TARGET_HAS_not_i32; | |
881 | } | |
882 | if (!have_not) { | |
883 | break; | |
884 | } | |
c45cb8bb | 885 | op->opc = not_op; |
acd93701 RH |
886 | reset_temp(op->args[0]); |
887 | op->args[1] = op->args[i]; | |
e201b564 RH |
888 | continue; |
889 | } | |
01ee5282 AJ |
890 | default: |
891 | break; | |
892 | } | |
893 | ||
464a1441 | 894 | /* Simplify expression for "op r, a, const => mov r, a" cases */ |
c45cb8bb | 895 | switch (opc) { |
170ba88f RH |
896 | CASE_OP_32_64_VEC(add): |
897 | CASE_OP_32_64_VEC(sub): | |
898 | CASE_OP_32_64_VEC(or): | |
899 | CASE_OP_32_64_VEC(xor): | |
900 | CASE_OP_32_64_VEC(andc): | |
55c0975c KB |
901 | CASE_OP_32_64(shl): |
902 | CASE_OP_32_64(shr): | |
903 | CASE_OP_32_64(sar): | |
25c4d9cc RH |
904 | CASE_OP_32_64(rotl): |
905 | CASE_OP_32_64(rotr): | |
6349039d RH |
906 | if (!arg_is_const(op->args[1]) |
907 | && arg_is_const(op->args[2]) | |
908 | && arg_info(op->args[2])->val == 0) { | |
dc84988a | 909 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
97a79eb7 | 910 | continue; |
53108fb5 KB |
911 | } |
912 | break; | |
170ba88f RH |
913 | CASE_OP_32_64_VEC(and): |
914 | CASE_OP_32_64_VEC(orc): | |
464a1441 | 915 | CASE_OP_32_64(eqv): |
6349039d RH |
916 | if (!arg_is_const(op->args[1]) |
917 | && arg_is_const(op->args[2]) | |
918 | && arg_info(op->args[2])->val == -1) { | |
dc84988a | 919 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
97a79eb7 | 920 | continue; |
464a1441 RH |
921 | } |
922 | break; | |
56e49438 AJ |
923 | default: |
924 | break; | |
925 | } | |
926 | ||
3031244b AJ |
927 | /* Simplify using known-zero bits. Currently only ops with a single |
928 | output argument is supported. */ | |
b1fde411 | 929 | z_mask = -1; |
633f6502 | 930 | affected = -1; |
c45cb8bb | 931 | switch (opc) { |
3a9d8b17 | 932 | CASE_OP_32_64(ext8s): |
b1fde411 | 933 | if ((arg_info(op->args[1])->z_mask & 0x80) != 0) { |
3a9d8b17 PB |
934 | break; |
935 | } | |
d84568b7 | 936 | QEMU_FALLTHROUGH; |
3a9d8b17 | 937 | CASE_OP_32_64(ext8u): |
b1fde411 | 938 | z_mask = 0xff; |
3a9d8b17 PB |
939 | goto and_const; |
940 | CASE_OP_32_64(ext16s): | |
b1fde411 | 941 | if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) { |
3a9d8b17 PB |
942 | break; |
943 | } | |
d84568b7 | 944 | QEMU_FALLTHROUGH; |
3a9d8b17 | 945 | CASE_OP_32_64(ext16u): |
b1fde411 | 946 | z_mask = 0xffff; |
3a9d8b17 PB |
947 | goto and_const; |
948 | case INDEX_op_ext32s_i64: | |
b1fde411 | 949 | if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { |
3a9d8b17 PB |
950 | break; |
951 | } | |
d84568b7 | 952 | QEMU_FALLTHROUGH; |
3a9d8b17 | 953 | case INDEX_op_ext32u_i64: |
b1fde411 | 954 | z_mask = 0xffffffffU; |
3a9d8b17 PB |
955 | goto and_const; |
956 | ||
957 | CASE_OP_32_64(and): | |
b1fde411 | 958 | z_mask = arg_info(op->args[2])->z_mask; |
6349039d | 959 | if (arg_is_const(op->args[2])) { |
3a9d8b17 | 960 | and_const: |
b1fde411 | 961 | affected = arg_info(op->args[1])->z_mask & ~z_mask; |
3a9d8b17 | 962 | } |
b1fde411 | 963 | z_mask = arg_info(op->args[1])->z_mask & z_mask; |
3a9d8b17 PB |
964 | break; |
965 | ||
8bcb5c8f | 966 | case INDEX_op_ext_i32_i64: |
b1fde411 | 967 | if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { |
8bcb5c8f AJ |
968 | break; |
969 | } | |
d84568b7 | 970 | QEMU_FALLTHROUGH; |
8bcb5c8f AJ |
971 | case INDEX_op_extu_i32_i64: |
972 | /* We do not compute affected as it is a size changing op. */ | |
b1fde411 | 973 | z_mask = (uint32_t)arg_info(op->args[1])->z_mask; |
8bcb5c8f AJ |
974 | break; |
975 | ||
23ec69ed RH |
976 | CASE_OP_32_64(andc): |
977 | /* Known-zeros does not imply known-ones. Therefore unless | |
acd93701 | 978 | op->args[2] is constant, we can't infer anything from it. */ |
6349039d | 979 | if (arg_is_const(op->args[2])) { |
b1fde411 | 980 | z_mask = ~arg_info(op->args[2])->z_mask; |
23ec69ed RH |
981 | goto and_const; |
982 | } | |
6349039d | 983 | /* But we certainly know nothing outside args[1] may be set. */ |
b1fde411 | 984 | z_mask = arg_info(op->args[1])->z_mask; |
23ec69ed RH |
985 | break; |
986 | ||
e46b225a | 987 | case INDEX_op_sar_i32: |
6349039d RH |
988 | if (arg_is_const(op->args[2])) { |
989 | tmp = arg_info(op->args[2])->val & 31; | |
b1fde411 | 990 | z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp; |
e46b225a AJ |
991 | } |
992 | break; | |
993 | case INDEX_op_sar_i64: | |
6349039d RH |
994 | if (arg_is_const(op->args[2])) { |
995 | tmp = arg_info(op->args[2])->val & 63; | |
b1fde411 | 996 | z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp; |
3a9d8b17 PB |
997 | } |
998 | break; | |
999 | ||
e46b225a | 1000 | case INDEX_op_shr_i32: |
6349039d RH |
1001 | if (arg_is_const(op->args[2])) { |
1002 | tmp = arg_info(op->args[2])->val & 31; | |
b1fde411 | 1003 | z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp; |
e46b225a AJ |
1004 | } |
1005 | break; | |
1006 | case INDEX_op_shr_i64: | |
6349039d RH |
1007 | if (arg_is_const(op->args[2])) { |
1008 | tmp = arg_info(op->args[2])->val & 63; | |
b1fde411 | 1009 | z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp; |
3a9d8b17 PB |
1010 | } |
1011 | break; | |
1012 | ||
609ad705 | 1013 | case INDEX_op_extrl_i64_i32: |
b1fde411 | 1014 | z_mask = (uint32_t)arg_info(op->args[1])->z_mask; |
609ad705 RH |
1015 | break; |
1016 | case INDEX_op_extrh_i64_i32: | |
b1fde411 | 1017 | z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32; |
4bb7a41e RH |
1018 | break; |
1019 | ||
3a9d8b17 | 1020 | CASE_OP_32_64(shl): |
6349039d RH |
1021 | if (arg_is_const(op->args[2])) { |
1022 | tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1); | |
b1fde411 | 1023 | z_mask = arg_info(op->args[1])->z_mask << tmp; |
3a9d8b17 PB |
1024 | } |
1025 | break; | |
1026 | ||
1027 | CASE_OP_32_64(neg): | |
1028 | /* Set to 1 all bits to the left of the rightmost. */ | |
b1fde411 RH |
1029 | z_mask = -(arg_info(op->args[1])->z_mask |
1030 | & -arg_info(op->args[1])->z_mask); | |
3a9d8b17 PB |
1031 | break; |
1032 | ||
1033 | CASE_OP_32_64(deposit): | |
b1fde411 RH |
1034 | z_mask = deposit64(arg_info(op->args[1])->z_mask, |
1035 | op->args[3], op->args[4], | |
1036 | arg_info(op->args[2])->z_mask); | |
3a9d8b17 PB |
1037 | break; |
1038 | ||
7ec8bab3 | 1039 | CASE_OP_32_64(extract): |
b1fde411 RH |
1040 | z_mask = extract64(arg_info(op->args[1])->z_mask, |
1041 | op->args[2], op->args[3]); | |
acd93701 | 1042 | if (op->args[2] == 0) { |
b1fde411 | 1043 | affected = arg_info(op->args[1])->z_mask & ~z_mask; |
7ec8bab3 RH |
1044 | } |
1045 | break; | |
1046 | CASE_OP_32_64(sextract): | |
b1fde411 RH |
1047 | z_mask = sextract64(arg_info(op->args[1])->z_mask, |
1048 | op->args[2], op->args[3]); | |
1049 | if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) { | |
1050 | affected = arg_info(op->args[1])->z_mask & ~z_mask; | |
7ec8bab3 RH |
1051 | } |
1052 | break; | |
1053 | ||
3a9d8b17 PB |
1054 | CASE_OP_32_64(or): |
1055 | CASE_OP_32_64(xor): | |
b1fde411 RH |
1056 | z_mask = arg_info(op->args[1])->z_mask |
1057 | | arg_info(op->args[2])->z_mask; | |
3a9d8b17 PB |
1058 | break; |
1059 | ||
0e28d006 RH |
1060 | case INDEX_op_clz_i32: |
1061 | case INDEX_op_ctz_i32: | |
b1fde411 | 1062 | z_mask = arg_info(op->args[2])->z_mask | 31; |
0e28d006 RH |
1063 | break; |
1064 | ||
1065 | case INDEX_op_clz_i64: | |
1066 | case INDEX_op_ctz_i64: | |
b1fde411 | 1067 | z_mask = arg_info(op->args[2])->z_mask | 63; |
0e28d006 RH |
1068 | break; |
1069 | ||
a768e4e9 | 1070 | case INDEX_op_ctpop_i32: |
b1fde411 | 1071 | z_mask = 32 | 31; |
a768e4e9 RH |
1072 | break; |
1073 | case INDEX_op_ctpop_i64: | |
b1fde411 | 1074 | z_mask = 64 | 63; |
a768e4e9 RH |
1075 | break; |
1076 | ||
3a9d8b17 | 1077 | CASE_OP_32_64(setcond): |
a763551a | 1078 | case INDEX_op_setcond2_i32: |
b1fde411 | 1079 | z_mask = 1; |
3a9d8b17 PB |
1080 | break; |
1081 | ||
1082 | CASE_OP_32_64(movcond): | |
b1fde411 RH |
1083 | z_mask = arg_info(op->args[3])->z_mask |
1084 | | arg_info(op->args[4])->z_mask; | |
3a9d8b17 PB |
1085 | break; |
1086 | ||
c8d70272 | 1087 | CASE_OP_32_64(ld8u): |
b1fde411 | 1088 | z_mask = 0xff; |
c8d70272 AJ |
1089 | break; |
1090 | CASE_OP_32_64(ld16u): | |
b1fde411 | 1091 | z_mask = 0xffff; |
c8d70272 AJ |
1092 | break; |
1093 | case INDEX_op_ld32u_i64: | |
b1fde411 | 1094 | z_mask = 0xffffffffu; |
c8d70272 AJ |
1095 | break; |
1096 | ||
1097 | CASE_OP_32_64(qemu_ld): | |
1098 | { | |
ec5d4cbe | 1099 | MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs]; |
14776ab5 | 1100 | MemOp mop = get_memop(oi); |
c8d70272 | 1101 | if (!(mop & MO_SIGN)) { |
b1fde411 | 1102 | z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; |
c8d70272 AJ |
1103 | } |
1104 | } | |
1105 | break; | |
1106 | ||
0b76ff8f | 1107 | CASE_OP_32_64(bswap16): |
b1fde411 RH |
1108 | z_mask = arg_info(op->args[1])->z_mask; |
1109 | if (z_mask <= 0xffff) { | |
0b76ff8f RH |
1110 | op->args[2] |= TCG_BSWAP_IZ; |
1111 | } | |
b1fde411 | 1112 | z_mask = bswap16(z_mask); |
0b76ff8f RH |
1113 | switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { |
1114 | case TCG_BSWAP_OZ: | |
1115 | break; | |
1116 | case TCG_BSWAP_OS: | |
b1fde411 | 1117 | z_mask = (int16_t)z_mask; |
0b76ff8f RH |
1118 | break; |
1119 | default: /* undefined high bits */ | |
b1fde411 | 1120 | z_mask |= MAKE_64BIT_MASK(16, 48); |
0b76ff8f RH |
1121 | break; |
1122 | } | |
1123 | break; | |
1124 | ||
1125 | case INDEX_op_bswap32_i64: | |
b1fde411 RH |
1126 | z_mask = arg_info(op->args[1])->z_mask; |
1127 | if (z_mask <= 0xffffffffu) { | |
0b76ff8f RH |
1128 | op->args[2] |= TCG_BSWAP_IZ; |
1129 | } | |
b1fde411 | 1130 | z_mask = bswap32(z_mask); |
0b76ff8f RH |
1131 | switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { |
1132 | case TCG_BSWAP_OZ: | |
1133 | break; | |
1134 | case TCG_BSWAP_OS: | |
b1fde411 | 1135 | z_mask = (int32_t)z_mask; |
0b76ff8f RH |
1136 | break; |
1137 | default: /* undefined high bits */ | |
b1fde411 | 1138 | z_mask |= MAKE_64BIT_MASK(32, 32); |
0b76ff8f RH |
1139 | break; |
1140 | } | |
1141 | break; | |
1142 | ||
3a9d8b17 PB |
1143 | default: |
1144 | break; | |
1145 | } | |
1146 | ||
bc8d688f RH |
1147 | /* 32-bit ops generate 32-bit results. For the result is zero test |
1148 | below, we can ignore high bits, but for further optimizations we | |
1149 | need to record that the high bits contain garbage. */ | |
b1fde411 | 1150 | partmask = z_mask; |
bc8d688f | 1151 | if (!(def->flags & TCG_OPF_64BIT)) { |
b1fde411 | 1152 | z_mask |= ~(tcg_target_ulong)0xffffffffu; |
24666baf RH |
1153 | partmask &= 0xffffffffu; |
1154 | affected &= 0xffffffffu; | |
f096dc96 | 1155 | } |
137f1f44 | 1156 | ctx.z_mask = z_mask; |
f096dc96 | 1157 | |
24666baf | 1158 | if (partmask == 0) { |
dc84988a | 1159 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
633f6502 PB |
1160 | continue; |
1161 | } | |
1162 | if (affected == 0) { | |
dc84988a | 1163 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
633f6502 PB |
1164 | continue; |
1165 | } | |
1166 | ||
56e49438 | 1167 | /* Simplify expression for "op r, a, 0 => movi r, 0" cases */ |
c45cb8bb | 1168 | switch (opc) { |
170ba88f RH |
1169 | CASE_OP_32_64_VEC(and): |
1170 | CASE_OP_32_64_VEC(mul): | |
03271524 RH |
1171 | CASE_OP_32_64(muluh): |
1172 | CASE_OP_32_64(mulsh): | |
6349039d RH |
1173 | if (arg_is_const(op->args[2]) |
1174 | && arg_info(op->args[2])->val == 0) { | |
dc84988a | 1175 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
53108fb5 KB |
1176 | continue; |
1177 | } | |
1178 | break; | |
56e49438 AJ |
1179 | default: |
1180 | break; | |
1181 | } | |
1182 | ||
1183 | /* Simplify expression for "op r, a, a => mov r, a" cases */ | |
c45cb8bb | 1184 | switch (opc) { |
170ba88f RH |
1185 | CASE_OP_32_64_VEC(or): |
1186 | CASE_OP_32_64_VEC(and): | |
6349039d | 1187 | if (args_are_copies(op->args[1], op->args[2])) { |
dc84988a | 1188 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
9a81090b KB |
1189 | continue; |
1190 | } | |
1191 | break; | |
fe0de7aa BS |
1192 | default: |
1193 | break; | |
53108fb5 KB |
1194 | } |
1195 | ||
3c94193e | 1196 | /* Simplify expression for "op r, a, a => movi r, 0" cases */ |
c45cb8bb | 1197 | switch (opc) { |
170ba88f RH |
1198 | CASE_OP_32_64_VEC(andc): |
1199 | CASE_OP_32_64_VEC(sub): | |
1200 | CASE_OP_32_64_VEC(xor): | |
6349039d | 1201 | if (args_are_copies(op->args[1], op->args[2])) { |
dc84988a | 1202 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
3c94193e AJ |
1203 | continue; |
1204 | } | |
1205 | break; | |
1206 | default: | |
1207 | break; | |
1208 | } | |
1209 | ||
22613af4 KB |
1210 | /* Propagate constants through copy operations and do constant |
1211 | folding. Constants will be substituted to arguments by register | |
1212 | allocator where needed and possible. Also detect copies. */ | |
c45cb8bb | 1213 | switch (opc) { |
170ba88f | 1214 | CASE_OP_32_64_VEC(mov): |
dc84988a | 1215 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
b10f3833 | 1216 | continue; |
6e14e91b | 1217 | |
170ba88f RH |
1218 | case INDEX_op_dup_vec: |
1219 | if (arg_is_const(op->args[1])) { | |
1220 | tmp = arg_info(op->args[1])->val; | |
1221 | tmp = dup_const(TCGOP_VECE(op), tmp); | |
dc84988a | 1222 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1223 | continue; |
170ba88f | 1224 | } |
b10f3833 | 1225 | break; |
170ba88f | 1226 | |
1dc4fe70 RH |
1227 | case INDEX_op_dup2_vec: |
1228 | assert(TCG_TARGET_REG_BITS == 32); | |
1229 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | |
dc84988a | 1230 | tcg_opt_gen_movi(&ctx, op, op->args[0], |
0b4286dd RH |
1231 | deposit64(arg_info(op->args[1])->val, 32, 32, |
1232 | arg_info(op->args[2])->val)); | |
b10f3833 | 1233 | continue; |
1dc4fe70 RH |
1234 | } else if (args_are_copies(op->args[1], op->args[2])) { |
1235 | op->opc = INDEX_op_dup_vec; | |
1236 | TCGOP_VECE(op) = MO_32; | |
1dc4fe70 | 1237 | } |
b10f3833 | 1238 | break; |
1dc4fe70 | 1239 | |
a640f031 | 1240 | CASE_OP_32_64(not): |
cb25c80a | 1241 | CASE_OP_32_64(neg): |
25c4d9cc RH |
1242 | CASE_OP_32_64(ext8s): |
1243 | CASE_OP_32_64(ext8u): | |
1244 | CASE_OP_32_64(ext16s): | |
1245 | CASE_OP_32_64(ext16u): | |
a768e4e9 | 1246 | CASE_OP_32_64(ctpop): |
a640f031 KB |
1247 | case INDEX_op_ext32s_i64: |
1248 | case INDEX_op_ext32u_i64: | |
8bcb5c8f AJ |
1249 | case INDEX_op_ext_i32_i64: |
1250 | case INDEX_op_extu_i32_i64: | |
609ad705 RH |
1251 | case INDEX_op_extrl_i64_i32: |
1252 | case INDEX_op_extrh_i64_i32: | |
6349039d RH |
1253 | if (arg_is_const(op->args[1])) { |
1254 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); | |
dc84988a | 1255 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1256 | continue; |
a640f031 | 1257 | } |
b10f3833 | 1258 | break; |
6e14e91b | 1259 | |
0b76ff8f RH |
1260 | CASE_OP_32_64(bswap16): |
1261 | CASE_OP_32_64(bswap32): | |
1262 | case INDEX_op_bswap64_i64: | |
1263 | if (arg_is_const(op->args[1])) { | |
1264 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, | |
1265 | op->args[2]); | |
dc84988a | 1266 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1267 | continue; |
0b76ff8f | 1268 | } |
b10f3833 | 1269 | break; |
0b76ff8f | 1270 | |
53108fb5 KB |
1271 | CASE_OP_32_64(add): |
1272 | CASE_OP_32_64(sub): | |
1273 | CASE_OP_32_64(mul): | |
9a81090b KB |
1274 | CASE_OP_32_64(or): |
1275 | CASE_OP_32_64(and): | |
1276 | CASE_OP_32_64(xor): | |
55c0975c KB |
1277 | CASE_OP_32_64(shl): |
1278 | CASE_OP_32_64(shr): | |
1279 | CASE_OP_32_64(sar): | |
25c4d9cc RH |
1280 | CASE_OP_32_64(rotl): |
1281 | CASE_OP_32_64(rotr): | |
cb25c80a RH |
1282 | CASE_OP_32_64(andc): |
1283 | CASE_OP_32_64(orc): | |
1284 | CASE_OP_32_64(eqv): | |
1285 | CASE_OP_32_64(nand): | |
1286 | CASE_OP_32_64(nor): | |
03271524 RH |
1287 | CASE_OP_32_64(muluh): |
1288 | CASE_OP_32_64(mulsh): | |
01547f7f RH |
1289 | CASE_OP_32_64(div): |
1290 | CASE_OP_32_64(divu): | |
1291 | CASE_OP_32_64(rem): | |
1292 | CASE_OP_32_64(remu): | |
6349039d RH |
1293 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { |
1294 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, | |
1295 | arg_info(op->args[2])->val); | |
dc84988a | 1296 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1297 | continue; |
53108fb5 | 1298 | } |
b10f3833 | 1299 | break; |
6e14e91b | 1300 | |
0e28d006 RH |
1301 | CASE_OP_32_64(clz): |
1302 | CASE_OP_32_64(ctz): | |
6349039d RH |
1303 | if (arg_is_const(op->args[1])) { |
1304 | TCGArg v = arg_info(op->args[1])->val; | |
0e28d006 RH |
1305 | if (v != 0) { |
1306 | tmp = do_constant_folding(opc, v, 0); | |
dc84988a | 1307 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
0e28d006 | 1308 | } else { |
dc84988a | 1309 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]); |
0e28d006 | 1310 | } |
b10f3833 | 1311 | continue; |
0e28d006 | 1312 | } |
b10f3833 | 1313 | break; |
0e28d006 | 1314 | |
7ef55fc9 | 1315 | CASE_OP_32_64(deposit): |
6349039d RH |
1316 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { |
1317 | tmp = deposit64(arg_info(op->args[1])->val, | |
1318 | op->args[3], op->args[4], | |
1319 | arg_info(op->args[2])->val); | |
dc84988a | 1320 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1321 | continue; |
7ef55fc9 | 1322 | } |
b10f3833 | 1323 | break; |
6e14e91b | 1324 | |
7ec8bab3 | 1325 | CASE_OP_32_64(extract): |
6349039d RH |
1326 | if (arg_is_const(op->args[1])) { |
1327 | tmp = extract64(arg_info(op->args[1])->val, | |
acd93701 | 1328 | op->args[2], op->args[3]); |
dc84988a | 1329 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1330 | continue; |
7ec8bab3 | 1331 | } |
b10f3833 | 1332 | break; |
7ec8bab3 RH |
1333 | |
1334 | CASE_OP_32_64(sextract): | |
6349039d RH |
1335 | if (arg_is_const(op->args[1])) { |
1336 | tmp = sextract64(arg_info(op->args[1])->val, | |
acd93701 | 1337 | op->args[2], op->args[3]); |
dc84988a | 1338 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1339 | continue; |
7ec8bab3 | 1340 | } |
b10f3833 | 1341 | break; |
7ec8bab3 | 1342 | |
fce1296f RH |
1343 | CASE_OP_32_64(extract2): |
1344 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | |
54795544 RH |
1345 | uint64_t v1 = arg_info(op->args[1])->val; |
1346 | uint64_t v2 = arg_info(op->args[2])->val; | |
1347 | int shr = op->args[3]; | |
fce1296f RH |
1348 | |
1349 | if (opc == INDEX_op_extract2_i64) { | |
54795544 | 1350 | tmp = (v1 >> shr) | (v2 << (64 - shr)); |
fce1296f | 1351 | } else { |
54795544 RH |
1352 | tmp = (int32_t)(((uint32_t)v1 >> shr) | |
1353 | ((uint32_t)v2 << (32 - shr))); | |
fce1296f | 1354 | } |
dc84988a | 1355 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1356 | continue; |
fce1296f | 1357 | } |
b10f3833 | 1358 | break; |
fce1296f | 1359 | |
f8dd19e5 | 1360 | CASE_OP_32_64(setcond): |
8d57bf1e RH |
1361 | i = do_constant_folding_cond(opc, op->args[1], |
1362 | op->args[2], op->args[3]); | |
1363 | if (i >= 0) { | |
1364 | tcg_opt_gen_movi(&ctx, op, op->args[0], i); | |
b10f3833 | 1365 | continue; |
f8dd19e5 | 1366 | } |
b10f3833 | 1367 | break; |
6e14e91b | 1368 | |
fbeaa26c | 1369 | CASE_OP_32_64(brcond): |
8d57bf1e RH |
1370 | i = do_constant_folding_cond(opc, op->args[0], |
1371 | op->args[1], op->args[2]); | |
1372 | if (i == 0) { | |
b10f3833 RH |
1373 | tcg_op_remove(s, op); |
1374 | continue; | |
8d57bf1e | 1375 | } else if (i > 0) { |
b10f3833 RH |
1376 | memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); |
1377 | op->opc = opc = INDEX_op_br; | |
1378 | op->args[0] = op->args[3]; | |
6e14e91b | 1379 | break; |
fbeaa26c | 1380 | } |
b10f3833 | 1381 | break; |
6e14e91b | 1382 | |
fa01a208 | 1383 | CASE_OP_32_64(movcond): |
8d57bf1e RH |
1384 | i = do_constant_folding_cond(opc, op->args[1], |
1385 | op->args[2], op->args[5]); | |
1386 | if (i >= 0) { | |
1387 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4 - i]); | |
b10f3833 | 1388 | continue; |
fa01a208 | 1389 | } |
6349039d | 1390 | if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { |
54795544 RH |
1391 | uint64_t tv = arg_info(op->args[3])->val; |
1392 | uint64_t fv = arg_info(op->args[4])->val; | |
acd93701 | 1393 | TCGCond cond = op->args[5]; |
54795544 | 1394 | |
333b21b8 RH |
1395 | if (fv == 1 && tv == 0) { |
1396 | cond = tcg_invert_cond(cond); | |
1397 | } else if (!(tv == 1 && fv == 0)) { | |
b10f3833 | 1398 | break; |
333b21b8 | 1399 | } |
acd93701 | 1400 | op->args[3] = cond; |
333b21b8 RH |
1401 | op->opc = opc = (opc == INDEX_op_movcond_i32 |
1402 | ? INDEX_op_setcond_i32 | |
1403 | : INDEX_op_setcond_i64); | |
333b21b8 | 1404 | } |
b10f3833 | 1405 | break; |
212c328d RH |
1406 | |
1407 | case INDEX_op_add2_i32: | |
1408 | case INDEX_op_sub2_i32: | |
6349039d RH |
1409 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) |
1410 | && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) { | |
1411 | uint32_t al = arg_info(op->args[2])->val; | |
1412 | uint32_t ah = arg_info(op->args[3])->val; | |
1413 | uint32_t bl = arg_info(op->args[4])->val; | |
1414 | uint32_t bh = arg_info(op->args[5])->val; | |
212c328d RH |
1415 | uint64_t a = ((uint64_t)ah << 32) | al; |
1416 | uint64_t b = ((uint64_t)bh << 32) | bl; | |
1417 | TCGArg rl, rh; | |
8fe35e04 | 1418 | TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); |
212c328d | 1419 | |
c45cb8bb | 1420 | if (opc == INDEX_op_add2_i32) { |
212c328d RH |
1421 | a += b; |
1422 | } else { | |
1423 | a -= b; | |
1424 | } | |
1425 | ||
acd93701 RH |
1426 | rl = op->args[0]; |
1427 | rh = op->args[1]; | |
dc84988a RH |
1428 | tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a); |
1429 | tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32)); | |
b10f3833 | 1430 | continue; |
212c328d | 1431 | } |
b10f3833 | 1432 | break; |
1414968a RH |
1433 | |
1434 | case INDEX_op_mulu2_i32: | |
6349039d RH |
1435 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { |
1436 | uint32_t a = arg_info(op->args[2])->val; | |
1437 | uint32_t b = arg_info(op->args[3])->val; | |
1414968a RH |
1438 | uint64_t r = (uint64_t)a * b; |
1439 | TCGArg rl, rh; | |
8fe35e04 | 1440 | TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); |
1414968a | 1441 | |
acd93701 RH |
1442 | rl = op->args[0]; |
1443 | rh = op->args[1]; | |
dc84988a RH |
1444 | tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r); |
1445 | tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32)); | |
b10f3833 | 1446 | continue; |
1414968a | 1447 | } |
b10f3833 | 1448 | break; |
6e14e91b | 1449 | |
bc1473ef | 1450 | case INDEX_op_brcond2_i32: |
8d57bf1e RH |
1451 | i = do_constant_folding_cond2(&op->args[0], &op->args[2], |
1452 | op->args[4]); | |
1453 | if (i == 0) { | |
a763551a | 1454 | do_brcond_false: |
b10f3833 RH |
1455 | tcg_op_remove(s, op); |
1456 | continue; | |
1457 | } | |
8d57bf1e | 1458 | if (i > 0) { |
b10f3833 RH |
1459 | do_brcond_true: |
1460 | op->opc = opc = INDEX_op_br; | |
1461 | op->args[0] = op->args[5]; | |
1462 | break; | |
1463 | } | |
1464 | if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE) | |
1465 | && arg_is_const(op->args[2]) | |
1466 | && arg_info(op->args[2])->val == 0 | |
1467 | && arg_is_const(op->args[3]) | |
1468 | && arg_info(op->args[3])->val == 0) { | |
6c4382f8 RH |
1469 | /* Simplify LT/GE comparisons vs zero to a single compare |
1470 | vs the high word of the input. */ | |
a763551a | 1471 | do_brcond_high: |
b10f3833 | 1472 | op->opc = opc = INDEX_op_brcond_i32; |
acd93701 RH |
1473 | op->args[0] = op->args[1]; |
1474 | op->args[1] = op->args[3]; | |
1475 | op->args[2] = op->args[4]; | |
1476 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1477 | break; |
1478 | } | |
1479 | if (op->args[4] == TCG_COND_EQ) { | |
a763551a RH |
1480 | /* Simplify EQ comparisons where one of the pairs |
1481 | can be simplified. */ | |
8d57bf1e RH |
1482 | i = do_constant_folding_cond(INDEX_op_brcond_i32, |
1483 | op->args[0], op->args[2], | |
1484 | TCG_COND_EQ); | |
1485 | if (i == 0) { | |
a763551a | 1486 | goto do_brcond_false; |
8d57bf1e | 1487 | } else if (i > 0) { |
a763551a RH |
1488 | goto do_brcond_high; |
1489 | } | |
8d57bf1e RH |
1490 | i = do_constant_folding_cond(INDEX_op_brcond_i32, |
1491 | op->args[1], op->args[3], | |
1492 | TCG_COND_EQ); | |
1493 | if (i == 0) { | |
a763551a | 1494 | goto do_brcond_false; |
8d57bf1e | 1495 | } else if (i < 0) { |
b10f3833 | 1496 | break; |
a763551a RH |
1497 | } |
1498 | do_brcond_low: | |
3b3f847d | 1499 | memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); |
c45cb8bb | 1500 | op->opc = INDEX_op_brcond_i32; |
acd93701 RH |
1501 | op->args[1] = op->args[2]; |
1502 | op->args[2] = op->args[4]; | |
1503 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1504 | break; |
1505 | } | |
1506 | if (op->args[4] == TCG_COND_NE) { | |
a763551a RH |
1507 | /* Simplify NE comparisons where one of the pairs |
1508 | can be simplified. */ | |
8d57bf1e RH |
1509 | i = do_constant_folding_cond(INDEX_op_brcond_i32, |
1510 | op->args[0], op->args[2], | |
1511 | TCG_COND_NE); | |
1512 | if (i == 0) { | |
a763551a | 1513 | goto do_brcond_high; |
8d57bf1e | 1514 | } else if (i > 0) { |
a763551a RH |
1515 | goto do_brcond_true; |
1516 | } | |
8d57bf1e RH |
1517 | i = do_constant_folding_cond(INDEX_op_brcond_i32, |
1518 | op->args[1], op->args[3], | |
1519 | TCG_COND_NE); | |
1520 | if (i == 0) { | |
a763551a | 1521 | goto do_brcond_low; |
8d57bf1e | 1522 | } else if (i > 0) { |
a763551a RH |
1523 | goto do_brcond_true; |
1524 | } | |
bc1473ef | 1525 | } |
6c4382f8 | 1526 | break; |
bc1473ef RH |
1527 | |
1528 | case INDEX_op_setcond2_i32: | |
8d57bf1e RH |
1529 | i = do_constant_folding_cond2(&op->args[1], &op->args[3], |
1530 | op->args[5]); | |
1531 | if (i >= 0) { | |
a763551a | 1532 | do_setcond_const: |
8d57bf1e | 1533 | tcg_opt_gen_movi(&ctx, op, op->args[0], i); |
b10f3833 RH |
1534 | continue; |
1535 | } | |
1536 | if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) | |
1537 | && arg_is_const(op->args[3]) | |
1538 | && arg_info(op->args[3])->val == 0 | |
1539 | && arg_is_const(op->args[4]) | |
1540 | && arg_info(op->args[4])->val == 0) { | |
6c4382f8 RH |
1541 | /* Simplify LT/GE comparisons vs zero to a single compare |
1542 | vs the high word of the input. */ | |
a763551a | 1543 | do_setcond_high: |
acd93701 | 1544 | reset_temp(op->args[0]); |
b1fde411 | 1545 | arg_info(op->args[0])->z_mask = 1; |
c45cb8bb | 1546 | op->opc = INDEX_op_setcond_i32; |
acd93701 RH |
1547 | op->args[1] = op->args[2]; |
1548 | op->args[2] = op->args[4]; | |
1549 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1550 | break; |
1551 | } | |
1552 | if (op->args[5] == TCG_COND_EQ) { | |
a763551a RH |
1553 | /* Simplify EQ comparisons where one of the pairs |
1554 | can be simplified. */ | |
8d57bf1e RH |
1555 | i = do_constant_folding_cond(INDEX_op_setcond_i32, |
1556 | op->args[1], op->args[3], | |
1557 | TCG_COND_EQ); | |
1558 | if (i == 0) { | |
a763551a | 1559 | goto do_setcond_const; |
8d57bf1e | 1560 | } else if (i > 0) { |
a763551a RH |
1561 | goto do_setcond_high; |
1562 | } | |
8d57bf1e RH |
1563 | i = do_constant_folding_cond(INDEX_op_setcond_i32, |
1564 | op->args[2], op->args[4], | |
1565 | TCG_COND_EQ); | |
1566 | if (i == 0) { | |
a763551a | 1567 | goto do_setcond_high; |
8d57bf1e | 1568 | } else if (i < 0) { |
b10f3833 | 1569 | break; |
a763551a RH |
1570 | } |
1571 | do_setcond_low: | |
acd93701 | 1572 | reset_temp(op->args[0]); |
b1fde411 | 1573 | arg_info(op->args[0])->z_mask = 1; |
c45cb8bb | 1574 | op->opc = INDEX_op_setcond_i32; |
acd93701 RH |
1575 | op->args[2] = op->args[3]; |
1576 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1577 | break; |
1578 | } | |
1579 | if (op->args[5] == TCG_COND_NE) { | |
a763551a RH |
1580 | /* Simplify NE comparisons where one of the pairs |
1581 | can be simplified. */ | |
8d57bf1e RH |
1582 | i = do_constant_folding_cond(INDEX_op_setcond_i32, |
1583 | op->args[1], op->args[3], | |
1584 | TCG_COND_NE); | |
1585 | if (i == 0) { | |
a763551a | 1586 | goto do_setcond_high; |
8d57bf1e | 1587 | } else if (i > 0) { |
a763551a RH |
1588 | goto do_setcond_const; |
1589 | } | |
8d57bf1e RH |
1590 | i = do_constant_folding_cond(INDEX_op_setcond_i32, |
1591 | op->args[2], op->args[4], | |
1592 | TCG_COND_NE); | |
1593 | if (i == 0) { | |
a763551a | 1594 | goto do_setcond_low; |
8d57bf1e | 1595 | } else if (i > 0) { |
a763551a RH |
1596 | goto do_setcond_const; |
1597 | } | |
bc1473ef | 1598 | } |
6c4382f8 | 1599 | break; |
bc1473ef | 1600 | |
b10f3833 RH |
1601 | default: |
1602 | break; | |
1603 | } | |
1604 | ||
137f1f44 | 1605 | finish_folding(&ctx, op); |
34f93921 PK |
1606 | |
1607 | /* Eliminate duplicate and redundant fence instructions. */ | |
d0ed5151 | 1608 | if (ctx.prev_mb) { |
34f93921 PK |
1609 | switch (opc) { |
1610 | case INDEX_op_mb: | |
1611 | /* Merge two barriers of the same type into one, | |
1612 | * or a weaker barrier into a stronger one, | |
1613 | * or two weaker barriers into a stronger one. | |
1614 | * mb X; mb Y => mb X|Y | |
1615 | * mb; strl => mb; st | |
1616 | * ldaq; mb => ld; mb | |
1617 | * ldaq; strl => ld; mb; st | |
1618 | * Other combinations are also merged into a strong | |
1619 | * barrier. This is stricter than specified but for | |
1620 | * the purposes of TCG is better than not optimizing. | |
1621 | */ | |
d0ed5151 | 1622 | ctx.prev_mb->args[0] |= op->args[0]; |
34f93921 PK |
1623 | tcg_op_remove(s, op); |
1624 | break; | |
1625 | ||
1626 | default: | |
1627 | /* Opcodes that end the block stop the optimization. */ | |
1628 | if ((def->flags & TCG_OPF_BB_END) == 0) { | |
1629 | break; | |
1630 | } | |
1631 | /* fallthru */ | |
1632 | case INDEX_op_qemu_ld_i32: | |
1633 | case INDEX_op_qemu_ld_i64: | |
1634 | case INDEX_op_qemu_st_i32: | |
07ce0b05 | 1635 | case INDEX_op_qemu_st8_i32: |
34f93921 | 1636 | case INDEX_op_qemu_st_i64: |
34f93921 | 1637 | /* Opcodes that touch guest memory stop the optimization. */ |
d0ed5151 | 1638 | ctx.prev_mb = NULL; |
34f93921 PK |
1639 | break; |
1640 | } | |
1641 | } else if (opc == INDEX_op_mb) { | |
d0ed5151 | 1642 | ctx.prev_mb = op; |
34f93921 | 1643 | } |
8f2e8c07 | 1644 | } |
8f2e8c07 | 1645 | } |