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1 | /* |
2 | * Optimizations for Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2010 Samsung Electronics. | |
5 | * Contributed by Kirill Batuzov <[email protected]> | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
757e725b | 26 | #include "qemu/osdep.h" |
dcb32f1d | 27 | #include "tcg/tcg-op.h" |
8f2e8c07 | 28 | |
8f2e8c07 KB |
29 | #define CASE_OP_32_64(x) \ |
30 | glue(glue(case INDEX_op_, x), _i32): \ | |
31 | glue(glue(case INDEX_op_, x), _i64) | |
8f2e8c07 | 32 | |
170ba88f RH |
33 | #define CASE_OP_32_64_VEC(x) \ |
34 | glue(glue(case INDEX_op_, x), _i32): \ | |
35 | glue(glue(case INDEX_op_, x), _i64): \ | |
36 | glue(glue(case INDEX_op_, x), _vec) | |
37 | ||
22613af4 | 38 | struct tcg_temp_info { |
b41059dd | 39 | bool is_const; |
6349039d RH |
40 | TCGTemp *prev_copy; |
41 | TCGTemp *next_copy; | |
22613af4 | 42 | tcg_target_ulong val; |
3a9d8b17 | 43 | tcg_target_ulong mask; |
22613af4 KB |
44 | }; |
45 | ||
6349039d | 46 | static inline struct tcg_temp_info *ts_info(TCGTemp *ts) |
d9c769c6 | 47 | { |
6349039d | 48 | return ts->state_ptr; |
d9c769c6 AJ |
49 | } |
50 | ||
6349039d | 51 | static inline struct tcg_temp_info *arg_info(TCGArg arg) |
d9c769c6 | 52 | { |
6349039d RH |
53 | return ts_info(arg_temp(arg)); |
54 | } | |
55 | ||
56 | static inline bool ts_is_const(TCGTemp *ts) | |
57 | { | |
58 | return ts_info(ts)->is_const; | |
59 | } | |
60 | ||
61 | static inline bool arg_is_const(TCGArg arg) | |
62 | { | |
63 | return ts_is_const(arg_temp(arg)); | |
64 | } | |
65 | ||
66 | static inline bool ts_is_copy(TCGTemp *ts) | |
67 | { | |
68 | return ts_info(ts)->next_copy != ts; | |
d9c769c6 AJ |
69 | } |
70 | ||
b41059dd | 71 | /* Reset TEMP's state, possibly removing the temp for the list of copies. */ |
6349039d RH |
72 | static void reset_ts(TCGTemp *ts) |
73 | { | |
74 | struct tcg_temp_info *ti = ts_info(ts); | |
75 | struct tcg_temp_info *pi = ts_info(ti->prev_copy); | |
76 | struct tcg_temp_info *ni = ts_info(ti->next_copy); | |
77 | ||
78 | ni->prev_copy = ti->prev_copy; | |
79 | pi->next_copy = ti->next_copy; | |
80 | ti->next_copy = ts; | |
81 | ti->prev_copy = ts; | |
82 | ti->is_const = false; | |
83 | ti->mask = -1; | |
84 | } | |
85 | ||
86 | static void reset_temp(TCGArg arg) | |
22613af4 | 87 | { |
6349039d | 88 | reset_ts(arg_temp(arg)); |
22613af4 KB |
89 | } |
90 | ||
1208d7dd | 91 | /* Initialize and activate a temporary. */ |
34184b07 EC |
92 | static void init_ts_info(struct tcg_temp_info *infos, |
93 | TCGTempSet *temps_used, TCGTemp *ts) | |
1208d7dd | 94 | { |
6349039d | 95 | size_t idx = temp_idx(ts); |
34184b07 EC |
96 | if (!test_bit(idx, temps_used->l)) { |
97 | struct tcg_temp_info *ti = &infos[idx]; | |
6349039d RH |
98 | |
99 | ts->state_ptr = ti; | |
100 | ti->next_copy = ts; | |
101 | ti->prev_copy = ts; | |
102 | ti->is_const = false; | |
103 | ti->mask = -1; | |
34184b07 | 104 | set_bit(idx, temps_used->l); |
1208d7dd AJ |
105 | } |
106 | } | |
107 | ||
34184b07 EC |
108 | static void init_arg_info(struct tcg_temp_info *infos, |
109 | TCGTempSet *temps_used, TCGArg arg) | |
6349039d | 110 | { |
34184b07 | 111 | init_ts_info(infos, temps_used, arg_temp(arg)); |
6349039d RH |
112 | } |
113 | ||
6349039d | 114 | static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) |
e590d4e6 | 115 | { |
6349039d | 116 | TCGTemp *i; |
e590d4e6 AJ |
117 | |
118 | /* If this is already a global, we can't do better. */ | |
fa477d25 | 119 | if (ts->temp_global) { |
6349039d | 120 | return ts; |
e590d4e6 AJ |
121 | } |
122 | ||
123 | /* Search for a global first. */ | |
6349039d RH |
124 | for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { |
125 | if (i->temp_global) { | |
e590d4e6 AJ |
126 | return i; |
127 | } | |
128 | } | |
129 | ||
130 | /* If it is a temp, search for a temp local. */ | |
fa477d25 | 131 | if (!ts->temp_local) { |
6349039d RH |
132 | for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { |
133 | if (ts->temp_local) { | |
e590d4e6 AJ |
134 | return i; |
135 | } | |
136 | } | |
137 | } | |
138 | ||
139 | /* Failure to find a better representation, return the same temp. */ | |
6349039d | 140 | return ts; |
e590d4e6 AJ |
141 | } |
142 | ||
6349039d | 143 | static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) |
e590d4e6 | 144 | { |
6349039d | 145 | TCGTemp *i; |
e590d4e6 | 146 | |
6349039d | 147 | if (ts1 == ts2) { |
e590d4e6 AJ |
148 | return true; |
149 | } | |
150 | ||
6349039d | 151 | if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) { |
e590d4e6 AJ |
152 | return false; |
153 | } | |
154 | ||
6349039d RH |
155 | for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) { |
156 | if (i == ts2) { | |
e590d4e6 AJ |
157 | return true; |
158 | } | |
159 | } | |
160 | ||
161 | return false; | |
162 | } | |
163 | ||
6349039d RH |
164 | static bool args_are_copies(TCGArg arg1, TCGArg arg2) |
165 | { | |
166 | return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); | |
167 | } | |
168 | ||
acd93701 | 169 | static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) |
97a79eb7 | 170 | { |
170ba88f RH |
171 | const TCGOpDef *def; |
172 | TCGOpcode new_op; | |
97a79eb7 | 173 | tcg_target_ulong mask; |
6349039d | 174 | struct tcg_temp_info *di = arg_info(dst); |
97a79eb7 | 175 | |
170ba88f RH |
176 | def = &tcg_op_defs[op->opc]; |
177 | if (def->flags & TCG_OPF_VECTOR) { | |
178 | new_op = INDEX_op_dupi_vec; | |
179 | } else if (def->flags & TCG_OPF_64BIT) { | |
180 | new_op = INDEX_op_movi_i64; | |
181 | } else { | |
182 | new_op = INDEX_op_movi_i32; | |
183 | } | |
97a79eb7 | 184 | op->opc = new_op; |
170ba88f RH |
185 | /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ |
186 | op->args[0] = dst; | |
187 | op->args[1] = val; | |
97a79eb7 AJ |
188 | |
189 | reset_temp(dst); | |
6349039d RH |
190 | di->is_const = true; |
191 | di->val = val; | |
97a79eb7 | 192 | mask = val; |
96152126 | 193 | if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) { |
97a79eb7 AJ |
194 | /* High bits of the destination are now garbage. */ |
195 | mask |= ~0xffffffffull; | |
196 | } | |
6349039d | 197 | di->mask = mask; |
97a79eb7 AJ |
198 | } |
199 | ||
acd93701 | 200 | static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) |
22613af4 | 201 | { |
6349039d RH |
202 | TCGTemp *dst_ts = arg_temp(dst); |
203 | TCGTemp *src_ts = arg_temp(src); | |
170ba88f | 204 | const TCGOpDef *def; |
6349039d RH |
205 | struct tcg_temp_info *di; |
206 | struct tcg_temp_info *si; | |
207 | tcg_target_ulong mask; | |
208 | TCGOpcode new_op; | |
209 | ||
210 | if (ts_are_copies(dst_ts, src_ts)) { | |
5365718a AJ |
211 | tcg_op_remove(s, op); |
212 | return; | |
213 | } | |
214 | ||
6349039d RH |
215 | reset_ts(dst_ts); |
216 | di = ts_info(dst_ts); | |
217 | si = ts_info(src_ts); | |
170ba88f RH |
218 | def = &tcg_op_defs[op->opc]; |
219 | if (def->flags & TCG_OPF_VECTOR) { | |
220 | new_op = INDEX_op_mov_vec; | |
221 | } else if (def->flags & TCG_OPF_64BIT) { | |
222 | new_op = INDEX_op_mov_i64; | |
223 | } else { | |
224 | new_op = INDEX_op_mov_i32; | |
225 | } | |
c45cb8bb | 226 | op->opc = new_op; |
170ba88f | 227 | /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ |
6349039d RH |
228 | op->args[0] = dst; |
229 | op->args[1] = src; | |
a62f6f56 | 230 | |
6349039d | 231 | mask = si->mask; |
24666baf RH |
232 | if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { |
233 | /* High bits of the destination are now garbage. */ | |
234 | mask |= ~0xffffffffull; | |
235 | } | |
6349039d | 236 | di->mask = mask; |
e590d4e6 | 237 | |
6349039d RH |
238 | if (src_ts->type == dst_ts->type) { |
239 | struct tcg_temp_info *ni = ts_info(si->next_copy); | |
240 | ||
241 | di->next_copy = si->next_copy; | |
242 | di->prev_copy = src_ts; | |
243 | ni->prev_copy = dst_ts; | |
244 | si->next_copy = dst_ts; | |
245 | di->is_const = si->is_const; | |
246 | di->val = si->val; | |
247 | } | |
22613af4 KB |
248 | } |
249 | ||
fe0de7aa | 250 | static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) |
53108fb5 | 251 | { |
03271524 RH |
252 | uint64_t l64, h64; |
253 | ||
53108fb5 KB |
254 | switch (op) { |
255 | CASE_OP_32_64(add): | |
256 | return x + y; | |
257 | ||
258 | CASE_OP_32_64(sub): | |
259 | return x - y; | |
260 | ||
261 | CASE_OP_32_64(mul): | |
262 | return x * y; | |
263 | ||
9a81090b KB |
264 | CASE_OP_32_64(and): |
265 | return x & y; | |
266 | ||
267 | CASE_OP_32_64(or): | |
268 | return x | y; | |
269 | ||
270 | CASE_OP_32_64(xor): | |
271 | return x ^ y; | |
272 | ||
55c0975c | 273 | case INDEX_op_shl_i32: |
50c5c4d1 | 274 | return (uint32_t)x << (y & 31); |
55c0975c | 275 | |
55c0975c | 276 | case INDEX_op_shl_i64: |
50c5c4d1 | 277 | return (uint64_t)x << (y & 63); |
55c0975c KB |
278 | |
279 | case INDEX_op_shr_i32: | |
50c5c4d1 | 280 | return (uint32_t)x >> (y & 31); |
55c0975c | 281 | |
55c0975c | 282 | case INDEX_op_shr_i64: |
50c5c4d1 | 283 | return (uint64_t)x >> (y & 63); |
55c0975c KB |
284 | |
285 | case INDEX_op_sar_i32: | |
50c5c4d1 | 286 | return (int32_t)x >> (y & 31); |
55c0975c | 287 | |
55c0975c | 288 | case INDEX_op_sar_i64: |
50c5c4d1 | 289 | return (int64_t)x >> (y & 63); |
55c0975c KB |
290 | |
291 | case INDEX_op_rotr_i32: | |
50c5c4d1 | 292 | return ror32(x, y & 31); |
55c0975c | 293 | |
55c0975c | 294 | case INDEX_op_rotr_i64: |
50c5c4d1 | 295 | return ror64(x, y & 63); |
55c0975c KB |
296 | |
297 | case INDEX_op_rotl_i32: | |
50c5c4d1 | 298 | return rol32(x, y & 31); |
55c0975c | 299 | |
55c0975c | 300 | case INDEX_op_rotl_i64: |
50c5c4d1 | 301 | return rol64(x, y & 63); |
25c4d9cc RH |
302 | |
303 | CASE_OP_32_64(not): | |
a640f031 | 304 | return ~x; |
25c4d9cc | 305 | |
cb25c80a RH |
306 | CASE_OP_32_64(neg): |
307 | return -x; | |
308 | ||
309 | CASE_OP_32_64(andc): | |
310 | return x & ~y; | |
311 | ||
312 | CASE_OP_32_64(orc): | |
313 | return x | ~y; | |
314 | ||
315 | CASE_OP_32_64(eqv): | |
316 | return ~(x ^ y); | |
317 | ||
318 | CASE_OP_32_64(nand): | |
319 | return ~(x & y); | |
320 | ||
321 | CASE_OP_32_64(nor): | |
322 | return ~(x | y); | |
323 | ||
0e28d006 RH |
324 | case INDEX_op_clz_i32: |
325 | return (uint32_t)x ? clz32(x) : y; | |
326 | ||
327 | case INDEX_op_clz_i64: | |
328 | return x ? clz64(x) : y; | |
329 | ||
330 | case INDEX_op_ctz_i32: | |
331 | return (uint32_t)x ? ctz32(x) : y; | |
332 | ||
333 | case INDEX_op_ctz_i64: | |
334 | return x ? ctz64(x) : y; | |
335 | ||
a768e4e9 RH |
336 | case INDEX_op_ctpop_i32: |
337 | return ctpop32(x); | |
338 | ||
339 | case INDEX_op_ctpop_i64: | |
340 | return ctpop64(x); | |
341 | ||
25c4d9cc | 342 | CASE_OP_32_64(ext8s): |
a640f031 | 343 | return (int8_t)x; |
25c4d9cc RH |
344 | |
345 | CASE_OP_32_64(ext16s): | |
a640f031 | 346 | return (int16_t)x; |
25c4d9cc RH |
347 | |
348 | CASE_OP_32_64(ext8u): | |
a640f031 | 349 | return (uint8_t)x; |
25c4d9cc RH |
350 | |
351 | CASE_OP_32_64(ext16u): | |
a640f031 KB |
352 | return (uint16_t)x; |
353 | ||
6498594c RH |
354 | CASE_OP_32_64(bswap16): |
355 | return bswap16(x); | |
356 | ||
357 | CASE_OP_32_64(bswap32): | |
358 | return bswap32(x); | |
359 | ||
360 | case INDEX_op_bswap64_i64: | |
361 | return bswap64(x); | |
362 | ||
8bcb5c8f | 363 | case INDEX_op_ext_i32_i64: |
a640f031 KB |
364 | case INDEX_op_ext32s_i64: |
365 | return (int32_t)x; | |
366 | ||
8bcb5c8f | 367 | case INDEX_op_extu_i32_i64: |
609ad705 | 368 | case INDEX_op_extrl_i64_i32: |
a640f031 KB |
369 | case INDEX_op_ext32u_i64: |
370 | return (uint32_t)x; | |
a640f031 | 371 | |
609ad705 RH |
372 | case INDEX_op_extrh_i64_i32: |
373 | return (uint64_t)x >> 32; | |
374 | ||
03271524 RH |
375 | case INDEX_op_muluh_i32: |
376 | return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32; | |
377 | case INDEX_op_mulsh_i32: | |
378 | return ((int64_t)(int32_t)x * (int32_t)y) >> 32; | |
379 | ||
380 | case INDEX_op_muluh_i64: | |
381 | mulu64(&l64, &h64, x, y); | |
382 | return h64; | |
383 | case INDEX_op_mulsh_i64: | |
384 | muls64(&l64, &h64, x, y); | |
385 | return h64; | |
386 | ||
01547f7f RH |
387 | case INDEX_op_div_i32: |
388 | /* Avoid crashing on divide by zero, otherwise undefined. */ | |
389 | return (int32_t)x / ((int32_t)y ? : 1); | |
390 | case INDEX_op_divu_i32: | |
391 | return (uint32_t)x / ((uint32_t)y ? : 1); | |
392 | case INDEX_op_div_i64: | |
393 | return (int64_t)x / ((int64_t)y ? : 1); | |
394 | case INDEX_op_divu_i64: | |
395 | return (uint64_t)x / ((uint64_t)y ? : 1); | |
396 | ||
397 | case INDEX_op_rem_i32: | |
398 | return (int32_t)x % ((int32_t)y ? : 1); | |
399 | case INDEX_op_remu_i32: | |
400 | return (uint32_t)x % ((uint32_t)y ? : 1); | |
401 | case INDEX_op_rem_i64: | |
402 | return (int64_t)x % ((int64_t)y ? : 1); | |
403 | case INDEX_op_remu_i64: | |
404 | return (uint64_t)x % ((uint64_t)y ? : 1); | |
405 | ||
53108fb5 KB |
406 | default: |
407 | fprintf(stderr, | |
408 | "Unrecognized operation %d in do_constant_folding.\n", op); | |
409 | tcg_abort(); | |
410 | } | |
411 | } | |
412 | ||
fe0de7aa | 413 | static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y) |
53108fb5 | 414 | { |
170ba88f | 415 | const TCGOpDef *def = &tcg_op_defs[op]; |
53108fb5 | 416 | TCGArg res = do_constant_folding_2(op, x, y); |
170ba88f | 417 | if (!(def->flags & TCG_OPF_64BIT)) { |
29f3ff8d | 418 | res = (int32_t)res; |
53108fb5 | 419 | } |
53108fb5 KB |
420 | return res; |
421 | } | |
422 | ||
9519da7e RH |
423 | static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c) |
424 | { | |
425 | switch (c) { | |
426 | case TCG_COND_EQ: | |
427 | return x == y; | |
428 | case TCG_COND_NE: | |
429 | return x != y; | |
430 | case TCG_COND_LT: | |
431 | return (int32_t)x < (int32_t)y; | |
432 | case TCG_COND_GE: | |
433 | return (int32_t)x >= (int32_t)y; | |
434 | case TCG_COND_LE: | |
435 | return (int32_t)x <= (int32_t)y; | |
436 | case TCG_COND_GT: | |
437 | return (int32_t)x > (int32_t)y; | |
438 | case TCG_COND_LTU: | |
439 | return x < y; | |
440 | case TCG_COND_GEU: | |
441 | return x >= y; | |
442 | case TCG_COND_LEU: | |
443 | return x <= y; | |
444 | case TCG_COND_GTU: | |
445 | return x > y; | |
446 | default: | |
447 | tcg_abort(); | |
448 | } | |
449 | } | |
450 | ||
451 | static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c) | |
452 | { | |
453 | switch (c) { | |
454 | case TCG_COND_EQ: | |
455 | return x == y; | |
456 | case TCG_COND_NE: | |
457 | return x != y; | |
458 | case TCG_COND_LT: | |
459 | return (int64_t)x < (int64_t)y; | |
460 | case TCG_COND_GE: | |
461 | return (int64_t)x >= (int64_t)y; | |
462 | case TCG_COND_LE: | |
463 | return (int64_t)x <= (int64_t)y; | |
464 | case TCG_COND_GT: | |
465 | return (int64_t)x > (int64_t)y; | |
466 | case TCG_COND_LTU: | |
467 | return x < y; | |
468 | case TCG_COND_GEU: | |
469 | return x >= y; | |
470 | case TCG_COND_LEU: | |
471 | return x <= y; | |
472 | case TCG_COND_GTU: | |
473 | return x > y; | |
474 | default: | |
475 | tcg_abort(); | |
476 | } | |
477 | } | |
478 | ||
479 | static bool do_constant_folding_cond_eq(TCGCond c) | |
480 | { | |
481 | switch (c) { | |
482 | case TCG_COND_GT: | |
483 | case TCG_COND_LTU: | |
484 | case TCG_COND_LT: | |
485 | case TCG_COND_GTU: | |
486 | case TCG_COND_NE: | |
487 | return 0; | |
488 | case TCG_COND_GE: | |
489 | case TCG_COND_GEU: | |
490 | case TCG_COND_LE: | |
491 | case TCG_COND_LEU: | |
492 | case TCG_COND_EQ: | |
493 | return 1; | |
494 | default: | |
495 | tcg_abort(); | |
496 | } | |
497 | } | |
498 | ||
b336ceb6 AJ |
499 | /* Return 2 if the condition can't be simplified, and the result |
500 | of the condition (0 or 1) if it can */ | |
f8dd19e5 AJ |
501 | static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, |
502 | TCGArg y, TCGCond c) | |
503 | { | |
6349039d RH |
504 | tcg_target_ulong xv = arg_info(x)->val; |
505 | tcg_target_ulong yv = arg_info(y)->val; | |
506 | if (arg_is_const(x) && arg_is_const(y)) { | |
170ba88f RH |
507 | const TCGOpDef *def = &tcg_op_defs[op]; |
508 | tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR)); | |
509 | if (def->flags & TCG_OPF_64BIT) { | |
6349039d | 510 | return do_constant_folding_cond_64(xv, yv, c); |
170ba88f RH |
511 | } else { |
512 | return do_constant_folding_cond_32(xv, yv, c); | |
b336ceb6 | 513 | } |
6349039d | 514 | } else if (args_are_copies(x, y)) { |
9519da7e | 515 | return do_constant_folding_cond_eq(c); |
6349039d | 516 | } else if (arg_is_const(y) && yv == 0) { |
b336ceb6 | 517 | switch (c) { |
f8dd19e5 | 518 | case TCG_COND_LTU: |
b336ceb6 | 519 | return 0; |
f8dd19e5 | 520 | case TCG_COND_GEU: |
b336ceb6 AJ |
521 | return 1; |
522 | default: | |
523 | return 2; | |
f8dd19e5 | 524 | } |
f8dd19e5 | 525 | } |
550276ae | 526 | return 2; |
f8dd19e5 AJ |
527 | } |
528 | ||
6c4382f8 RH |
529 | /* Return 2 if the condition can't be simplified, and the result |
530 | of the condition (0 or 1) if it can */ | |
531 | static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) | |
532 | { | |
533 | TCGArg al = p1[0], ah = p1[1]; | |
534 | TCGArg bl = p2[0], bh = p2[1]; | |
535 | ||
6349039d RH |
536 | if (arg_is_const(bl) && arg_is_const(bh)) { |
537 | tcg_target_ulong blv = arg_info(bl)->val; | |
538 | tcg_target_ulong bhv = arg_info(bh)->val; | |
539 | uint64_t b = deposit64(blv, 32, 32, bhv); | |
6c4382f8 | 540 | |
6349039d RH |
541 | if (arg_is_const(al) && arg_is_const(ah)) { |
542 | tcg_target_ulong alv = arg_info(al)->val; | |
543 | tcg_target_ulong ahv = arg_info(ah)->val; | |
544 | uint64_t a = deposit64(alv, 32, 32, ahv); | |
6c4382f8 RH |
545 | return do_constant_folding_cond_64(a, b, c); |
546 | } | |
547 | if (b == 0) { | |
548 | switch (c) { | |
549 | case TCG_COND_LTU: | |
550 | return 0; | |
551 | case TCG_COND_GEU: | |
552 | return 1; | |
553 | default: | |
554 | break; | |
555 | } | |
556 | } | |
557 | } | |
6349039d | 558 | if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { |
6c4382f8 RH |
559 | return do_constant_folding_cond_eq(c); |
560 | } | |
561 | return 2; | |
562 | } | |
563 | ||
24c9ae4e RH |
564 | static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) |
565 | { | |
566 | TCGArg a1 = *p1, a2 = *p2; | |
567 | int sum = 0; | |
6349039d RH |
568 | sum += arg_is_const(a1); |
569 | sum -= arg_is_const(a2); | |
24c9ae4e RH |
570 | |
571 | /* Prefer the constant in second argument, and then the form | |
572 | op a, a, b, which is better handled on non-RISC hosts. */ | |
573 | if (sum > 0 || (sum == 0 && dest == a2)) { | |
574 | *p1 = a2; | |
575 | *p2 = a1; | |
576 | return true; | |
577 | } | |
578 | return false; | |
579 | } | |
580 | ||
0bfcb865 RH |
581 | static bool swap_commutative2(TCGArg *p1, TCGArg *p2) |
582 | { | |
583 | int sum = 0; | |
6349039d RH |
584 | sum += arg_is_const(p1[0]); |
585 | sum += arg_is_const(p1[1]); | |
586 | sum -= arg_is_const(p2[0]); | |
587 | sum -= arg_is_const(p2[1]); | |
0bfcb865 RH |
588 | if (sum > 0) { |
589 | TCGArg t; | |
590 | t = p1[0], p1[0] = p2[0], p2[0] = t; | |
591 | t = p1[1], p1[1] = p2[1], p2[1] = t; | |
592 | return true; | |
593 | } | |
594 | return false; | |
595 | } | |
596 | ||
22613af4 | 597 | /* Propagate constants and copies, fold constant expressions. */ |
36e60ef6 | 598 | void tcg_optimize(TCGContext *s) |
8f2e8c07 | 599 | { |
15fa08f8 RH |
600 | int nb_temps, nb_globals; |
601 | TCGOp *op, *op_next, *prev_mb = NULL; | |
34184b07 EC |
602 | struct tcg_temp_info *infos; |
603 | TCGTempSet temps_used; | |
5d8f5363 | 604 | |
22613af4 KB |
605 | /* Array VALS has an element for each temp. |
606 | If this temp holds a constant then its value is kept in VALS' element. | |
e590d4e6 AJ |
607 | If this temp is a copy of other ones then the other copies are |
608 | available through the doubly linked circular list. */ | |
8f2e8c07 KB |
609 | |
610 | nb_temps = s->nb_temps; | |
611 | nb_globals = s->nb_globals; | |
34184b07 EC |
612 | bitmap_zero(temps_used.l, nb_temps); |
613 | infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps); | |
8f2e8c07 | 614 | |
15fa08f8 | 615 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { |
24666baf | 616 | tcg_target_ulong mask, partmask, affected; |
c45cb8bb | 617 | int nb_oargs, nb_iargs, i; |
cf066674 | 618 | TCGArg tmp; |
c45cb8bb RH |
619 | TCGOpcode opc = op->opc; |
620 | const TCGOpDef *def = &tcg_op_defs[opc]; | |
621 | ||
1208d7dd AJ |
622 | /* Count the arguments, and initialize the temps that are |
623 | going to be used */ | |
c45cb8bb | 624 | if (opc == INDEX_op_call) { |
cd9090aa RH |
625 | nb_oargs = TCGOP_CALLO(op); |
626 | nb_iargs = TCGOP_CALLI(op); | |
1208d7dd | 627 | for (i = 0; i < nb_oargs + nb_iargs; i++) { |
6349039d RH |
628 | TCGTemp *ts = arg_temp(op->args[i]); |
629 | if (ts) { | |
34184b07 | 630 | init_ts_info(infos, &temps_used, ts); |
1208d7dd AJ |
631 | } |
632 | } | |
1ff8c541 | 633 | } else { |
cf066674 RH |
634 | nb_oargs = def->nb_oargs; |
635 | nb_iargs = def->nb_iargs; | |
1208d7dd | 636 | for (i = 0; i < nb_oargs + nb_iargs; i++) { |
34184b07 | 637 | init_arg_info(infos, &temps_used, op->args[i]); |
1208d7dd | 638 | } |
cf066674 RH |
639 | } |
640 | ||
641 | /* Do copy propagation */ | |
642 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { | |
6349039d RH |
643 | TCGTemp *ts = arg_temp(op->args[i]); |
644 | if (ts && ts_is_copy(ts)) { | |
645 | op->args[i] = temp_arg(find_better_copy(s, ts)); | |
22613af4 KB |
646 | } |
647 | } | |
648 | ||
53108fb5 | 649 | /* For commutative operations make constant second argument */ |
c45cb8bb | 650 | switch (opc) { |
170ba88f RH |
651 | CASE_OP_32_64_VEC(add): |
652 | CASE_OP_32_64_VEC(mul): | |
653 | CASE_OP_32_64_VEC(and): | |
654 | CASE_OP_32_64_VEC(or): | |
655 | CASE_OP_32_64_VEC(xor): | |
cb25c80a RH |
656 | CASE_OP_32_64(eqv): |
657 | CASE_OP_32_64(nand): | |
658 | CASE_OP_32_64(nor): | |
03271524 RH |
659 | CASE_OP_32_64(muluh): |
660 | CASE_OP_32_64(mulsh): | |
acd93701 | 661 | swap_commutative(op->args[0], &op->args[1], &op->args[2]); |
53108fb5 | 662 | break; |
65a7cce1 | 663 | CASE_OP_32_64(brcond): |
acd93701 RH |
664 | if (swap_commutative(-1, &op->args[0], &op->args[1])) { |
665 | op->args[2] = tcg_swap_cond(op->args[2]); | |
65a7cce1 AJ |
666 | } |
667 | break; | |
668 | CASE_OP_32_64(setcond): | |
acd93701 RH |
669 | if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { |
670 | op->args[3] = tcg_swap_cond(op->args[3]); | |
65a7cce1 AJ |
671 | } |
672 | break; | |
fa01a208 | 673 | CASE_OP_32_64(movcond): |
acd93701 RH |
674 | if (swap_commutative(-1, &op->args[1], &op->args[2])) { |
675 | op->args[5] = tcg_swap_cond(op->args[5]); | |
5d8f5363 RH |
676 | } |
677 | /* For movcond, we canonicalize the "false" input reg to match | |
678 | the destination reg so that the tcg backend can implement | |
679 | a "move if true" operation. */ | |
acd93701 RH |
680 | if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { |
681 | op->args[5] = tcg_invert_cond(op->args[5]); | |
fa01a208 | 682 | } |
1e484e61 | 683 | break; |
d7156f7c | 684 | CASE_OP_32_64(add2): |
acd93701 RH |
685 | swap_commutative(op->args[0], &op->args[2], &op->args[4]); |
686 | swap_commutative(op->args[1], &op->args[3], &op->args[5]); | |
1e484e61 | 687 | break; |
d7156f7c | 688 | CASE_OP_32_64(mulu2): |
4d3203fd | 689 | CASE_OP_32_64(muls2): |
acd93701 | 690 | swap_commutative(op->args[0], &op->args[2], &op->args[3]); |
1414968a | 691 | break; |
0bfcb865 | 692 | case INDEX_op_brcond2_i32: |
acd93701 RH |
693 | if (swap_commutative2(&op->args[0], &op->args[2])) { |
694 | op->args[4] = tcg_swap_cond(op->args[4]); | |
0bfcb865 RH |
695 | } |
696 | break; | |
697 | case INDEX_op_setcond2_i32: | |
acd93701 RH |
698 | if (swap_commutative2(&op->args[1], &op->args[3])) { |
699 | op->args[5] = tcg_swap_cond(op->args[5]); | |
0bfcb865 RH |
700 | } |
701 | break; | |
53108fb5 KB |
702 | default: |
703 | break; | |
704 | } | |
705 | ||
2d497542 RH |
706 | /* Simplify expressions for "shift/rot r, 0, a => movi r, 0", |
707 | and "sub r, 0, a => neg r, a" case. */ | |
c45cb8bb | 708 | switch (opc) { |
01ee5282 AJ |
709 | CASE_OP_32_64(shl): |
710 | CASE_OP_32_64(shr): | |
711 | CASE_OP_32_64(sar): | |
712 | CASE_OP_32_64(rotl): | |
713 | CASE_OP_32_64(rotr): | |
6349039d RH |
714 | if (arg_is_const(op->args[1]) |
715 | && arg_info(op->args[1])->val == 0) { | |
acd93701 | 716 | tcg_opt_gen_movi(s, op, op->args[0], 0); |
01ee5282 AJ |
717 | continue; |
718 | } | |
719 | break; | |
170ba88f | 720 | CASE_OP_32_64_VEC(sub): |
2d497542 RH |
721 | { |
722 | TCGOpcode neg_op; | |
723 | bool have_neg; | |
724 | ||
6349039d | 725 | if (arg_is_const(op->args[2])) { |
2d497542 RH |
726 | /* Proceed with possible constant folding. */ |
727 | break; | |
728 | } | |
c45cb8bb | 729 | if (opc == INDEX_op_sub_i32) { |
2d497542 RH |
730 | neg_op = INDEX_op_neg_i32; |
731 | have_neg = TCG_TARGET_HAS_neg_i32; | |
170ba88f | 732 | } else if (opc == INDEX_op_sub_i64) { |
2d497542 RH |
733 | neg_op = INDEX_op_neg_i64; |
734 | have_neg = TCG_TARGET_HAS_neg_i64; | |
ac383dde RH |
735 | } else if (TCG_TARGET_HAS_neg_vec) { |
736 | TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64; | |
737 | unsigned vece = TCGOP_VECE(op); | |
170ba88f | 738 | neg_op = INDEX_op_neg_vec; |
ac383dde RH |
739 | have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0; |
740 | } else { | |
741 | break; | |
2d497542 RH |
742 | } |
743 | if (!have_neg) { | |
744 | break; | |
745 | } | |
6349039d RH |
746 | if (arg_is_const(op->args[1]) |
747 | && arg_info(op->args[1])->val == 0) { | |
c45cb8bb | 748 | op->opc = neg_op; |
acd93701 RH |
749 | reset_temp(op->args[0]); |
750 | op->args[1] = op->args[2]; | |
2d497542 RH |
751 | continue; |
752 | } | |
753 | } | |
754 | break; | |
170ba88f | 755 | CASE_OP_32_64_VEC(xor): |
e201b564 | 756 | CASE_OP_32_64(nand): |
6349039d RH |
757 | if (!arg_is_const(op->args[1]) |
758 | && arg_is_const(op->args[2]) | |
759 | && arg_info(op->args[2])->val == -1) { | |
e201b564 RH |
760 | i = 1; |
761 | goto try_not; | |
762 | } | |
763 | break; | |
764 | CASE_OP_32_64(nor): | |
6349039d RH |
765 | if (!arg_is_const(op->args[1]) |
766 | && arg_is_const(op->args[2]) | |
767 | && arg_info(op->args[2])->val == 0) { | |
e201b564 RH |
768 | i = 1; |
769 | goto try_not; | |
770 | } | |
771 | break; | |
170ba88f | 772 | CASE_OP_32_64_VEC(andc): |
6349039d RH |
773 | if (!arg_is_const(op->args[2]) |
774 | && arg_is_const(op->args[1]) | |
775 | && arg_info(op->args[1])->val == -1) { | |
e201b564 RH |
776 | i = 2; |
777 | goto try_not; | |
778 | } | |
779 | break; | |
170ba88f | 780 | CASE_OP_32_64_VEC(orc): |
e201b564 | 781 | CASE_OP_32_64(eqv): |
6349039d RH |
782 | if (!arg_is_const(op->args[2]) |
783 | && arg_is_const(op->args[1]) | |
784 | && arg_info(op->args[1])->val == 0) { | |
e201b564 RH |
785 | i = 2; |
786 | goto try_not; | |
787 | } | |
788 | break; | |
789 | try_not: | |
790 | { | |
791 | TCGOpcode not_op; | |
792 | bool have_not; | |
793 | ||
170ba88f RH |
794 | if (def->flags & TCG_OPF_VECTOR) { |
795 | not_op = INDEX_op_not_vec; | |
796 | have_not = TCG_TARGET_HAS_not_vec; | |
797 | } else if (def->flags & TCG_OPF_64BIT) { | |
e201b564 RH |
798 | not_op = INDEX_op_not_i64; |
799 | have_not = TCG_TARGET_HAS_not_i64; | |
800 | } else { | |
801 | not_op = INDEX_op_not_i32; | |
802 | have_not = TCG_TARGET_HAS_not_i32; | |
803 | } | |
804 | if (!have_not) { | |
805 | break; | |
806 | } | |
c45cb8bb | 807 | op->opc = not_op; |
acd93701 RH |
808 | reset_temp(op->args[0]); |
809 | op->args[1] = op->args[i]; | |
e201b564 RH |
810 | continue; |
811 | } | |
01ee5282 AJ |
812 | default: |
813 | break; | |
814 | } | |
815 | ||
464a1441 | 816 | /* Simplify expression for "op r, a, const => mov r, a" cases */ |
c45cb8bb | 817 | switch (opc) { |
170ba88f RH |
818 | CASE_OP_32_64_VEC(add): |
819 | CASE_OP_32_64_VEC(sub): | |
820 | CASE_OP_32_64_VEC(or): | |
821 | CASE_OP_32_64_VEC(xor): | |
822 | CASE_OP_32_64_VEC(andc): | |
55c0975c KB |
823 | CASE_OP_32_64(shl): |
824 | CASE_OP_32_64(shr): | |
825 | CASE_OP_32_64(sar): | |
25c4d9cc RH |
826 | CASE_OP_32_64(rotl): |
827 | CASE_OP_32_64(rotr): | |
6349039d RH |
828 | if (!arg_is_const(op->args[1]) |
829 | && arg_is_const(op->args[2]) | |
830 | && arg_info(op->args[2])->val == 0) { | |
acd93701 | 831 | tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); |
97a79eb7 | 832 | continue; |
53108fb5 KB |
833 | } |
834 | break; | |
170ba88f RH |
835 | CASE_OP_32_64_VEC(and): |
836 | CASE_OP_32_64_VEC(orc): | |
464a1441 | 837 | CASE_OP_32_64(eqv): |
6349039d RH |
838 | if (!arg_is_const(op->args[1]) |
839 | && arg_is_const(op->args[2]) | |
840 | && arg_info(op->args[2])->val == -1) { | |
acd93701 | 841 | tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); |
97a79eb7 | 842 | continue; |
464a1441 RH |
843 | } |
844 | break; | |
56e49438 AJ |
845 | default: |
846 | break; | |
847 | } | |
848 | ||
3031244b AJ |
849 | /* Simplify using known-zero bits. Currently only ops with a single |
850 | output argument is supported. */ | |
3a9d8b17 | 851 | mask = -1; |
633f6502 | 852 | affected = -1; |
c45cb8bb | 853 | switch (opc) { |
3a9d8b17 | 854 | CASE_OP_32_64(ext8s): |
6349039d | 855 | if ((arg_info(op->args[1])->mask & 0x80) != 0) { |
3a9d8b17 PB |
856 | break; |
857 | } | |
858 | CASE_OP_32_64(ext8u): | |
859 | mask = 0xff; | |
860 | goto and_const; | |
861 | CASE_OP_32_64(ext16s): | |
6349039d | 862 | if ((arg_info(op->args[1])->mask & 0x8000) != 0) { |
3a9d8b17 PB |
863 | break; |
864 | } | |
865 | CASE_OP_32_64(ext16u): | |
866 | mask = 0xffff; | |
867 | goto and_const; | |
868 | case INDEX_op_ext32s_i64: | |
6349039d | 869 | if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { |
3a9d8b17 PB |
870 | break; |
871 | } | |
872 | case INDEX_op_ext32u_i64: | |
873 | mask = 0xffffffffU; | |
874 | goto and_const; | |
875 | ||
876 | CASE_OP_32_64(and): | |
6349039d RH |
877 | mask = arg_info(op->args[2])->mask; |
878 | if (arg_is_const(op->args[2])) { | |
3a9d8b17 | 879 | and_const: |
6349039d | 880 | affected = arg_info(op->args[1])->mask & ~mask; |
3a9d8b17 | 881 | } |
6349039d | 882 | mask = arg_info(op->args[1])->mask & mask; |
3a9d8b17 PB |
883 | break; |
884 | ||
8bcb5c8f | 885 | case INDEX_op_ext_i32_i64: |
6349039d | 886 | if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { |
8bcb5c8f AJ |
887 | break; |
888 | } | |
889 | case INDEX_op_extu_i32_i64: | |
890 | /* We do not compute affected as it is a size changing op. */ | |
6349039d | 891 | mask = (uint32_t)arg_info(op->args[1])->mask; |
8bcb5c8f AJ |
892 | break; |
893 | ||
23ec69ed RH |
894 | CASE_OP_32_64(andc): |
895 | /* Known-zeros does not imply known-ones. Therefore unless | |
acd93701 | 896 | op->args[2] is constant, we can't infer anything from it. */ |
6349039d RH |
897 | if (arg_is_const(op->args[2])) { |
898 | mask = ~arg_info(op->args[2])->mask; | |
23ec69ed RH |
899 | goto and_const; |
900 | } | |
6349039d RH |
901 | /* But we certainly know nothing outside args[1] may be set. */ |
902 | mask = arg_info(op->args[1])->mask; | |
23ec69ed RH |
903 | break; |
904 | ||
e46b225a | 905 | case INDEX_op_sar_i32: |
6349039d RH |
906 | if (arg_is_const(op->args[2])) { |
907 | tmp = arg_info(op->args[2])->val & 31; | |
908 | mask = (int32_t)arg_info(op->args[1])->mask >> tmp; | |
e46b225a AJ |
909 | } |
910 | break; | |
911 | case INDEX_op_sar_i64: | |
6349039d RH |
912 | if (arg_is_const(op->args[2])) { |
913 | tmp = arg_info(op->args[2])->val & 63; | |
914 | mask = (int64_t)arg_info(op->args[1])->mask >> tmp; | |
3a9d8b17 PB |
915 | } |
916 | break; | |
917 | ||
e46b225a | 918 | case INDEX_op_shr_i32: |
6349039d RH |
919 | if (arg_is_const(op->args[2])) { |
920 | tmp = arg_info(op->args[2])->val & 31; | |
921 | mask = (uint32_t)arg_info(op->args[1])->mask >> tmp; | |
e46b225a AJ |
922 | } |
923 | break; | |
924 | case INDEX_op_shr_i64: | |
6349039d RH |
925 | if (arg_is_const(op->args[2])) { |
926 | tmp = arg_info(op->args[2])->val & 63; | |
927 | mask = (uint64_t)arg_info(op->args[1])->mask >> tmp; | |
3a9d8b17 PB |
928 | } |
929 | break; | |
930 | ||
609ad705 | 931 | case INDEX_op_extrl_i64_i32: |
6349039d | 932 | mask = (uint32_t)arg_info(op->args[1])->mask; |
609ad705 RH |
933 | break; |
934 | case INDEX_op_extrh_i64_i32: | |
6349039d | 935 | mask = (uint64_t)arg_info(op->args[1])->mask >> 32; |
4bb7a41e RH |
936 | break; |
937 | ||
3a9d8b17 | 938 | CASE_OP_32_64(shl): |
6349039d RH |
939 | if (arg_is_const(op->args[2])) { |
940 | tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1); | |
941 | mask = arg_info(op->args[1])->mask << tmp; | |
3a9d8b17 PB |
942 | } |
943 | break; | |
944 | ||
945 | CASE_OP_32_64(neg): | |
946 | /* Set to 1 all bits to the left of the rightmost. */ | |
6349039d RH |
947 | mask = -(arg_info(op->args[1])->mask |
948 | & -arg_info(op->args[1])->mask); | |
3a9d8b17 PB |
949 | break; |
950 | ||
951 | CASE_OP_32_64(deposit): | |
6349039d RH |
952 | mask = deposit64(arg_info(op->args[1])->mask, |
953 | op->args[3], op->args[4], | |
954 | arg_info(op->args[2])->mask); | |
3a9d8b17 PB |
955 | break; |
956 | ||
7ec8bab3 | 957 | CASE_OP_32_64(extract): |
6349039d RH |
958 | mask = extract64(arg_info(op->args[1])->mask, |
959 | op->args[2], op->args[3]); | |
acd93701 | 960 | if (op->args[2] == 0) { |
6349039d | 961 | affected = arg_info(op->args[1])->mask & ~mask; |
7ec8bab3 RH |
962 | } |
963 | break; | |
964 | CASE_OP_32_64(sextract): | |
6349039d | 965 | mask = sextract64(arg_info(op->args[1])->mask, |
acd93701 RH |
966 | op->args[2], op->args[3]); |
967 | if (op->args[2] == 0 && (tcg_target_long)mask >= 0) { | |
6349039d | 968 | affected = arg_info(op->args[1])->mask & ~mask; |
7ec8bab3 RH |
969 | } |
970 | break; | |
971 | ||
3a9d8b17 PB |
972 | CASE_OP_32_64(or): |
973 | CASE_OP_32_64(xor): | |
6349039d | 974 | mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask; |
3a9d8b17 PB |
975 | break; |
976 | ||
0e28d006 RH |
977 | case INDEX_op_clz_i32: |
978 | case INDEX_op_ctz_i32: | |
6349039d | 979 | mask = arg_info(op->args[2])->mask | 31; |
0e28d006 RH |
980 | break; |
981 | ||
982 | case INDEX_op_clz_i64: | |
983 | case INDEX_op_ctz_i64: | |
6349039d | 984 | mask = arg_info(op->args[2])->mask | 63; |
0e28d006 RH |
985 | break; |
986 | ||
a768e4e9 RH |
987 | case INDEX_op_ctpop_i32: |
988 | mask = 32 | 31; | |
989 | break; | |
990 | case INDEX_op_ctpop_i64: | |
991 | mask = 64 | 63; | |
992 | break; | |
993 | ||
3a9d8b17 | 994 | CASE_OP_32_64(setcond): |
a763551a | 995 | case INDEX_op_setcond2_i32: |
3a9d8b17 PB |
996 | mask = 1; |
997 | break; | |
998 | ||
999 | CASE_OP_32_64(movcond): | |
6349039d | 1000 | mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask; |
3a9d8b17 PB |
1001 | break; |
1002 | ||
c8d70272 | 1003 | CASE_OP_32_64(ld8u): |
c8d70272 AJ |
1004 | mask = 0xff; |
1005 | break; | |
1006 | CASE_OP_32_64(ld16u): | |
c8d70272 AJ |
1007 | mask = 0xffff; |
1008 | break; | |
1009 | case INDEX_op_ld32u_i64: | |
c8d70272 AJ |
1010 | mask = 0xffffffffu; |
1011 | break; | |
1012 | ||
1013 | CASE_OP_32_64(qemu_ld): | |
1014 | { | |
acd93701 | 1015 | TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs]; |
14776ab5 | 1016 | MemOp mop = get_memop(oi); |
c8d70272 AJ |
1017 | if (!(mop & MO_SIGN)) { |
1018 | mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; | |
1019 | } | |
1020 | } | |
1021 | break; | |
1022 | ||
3a9d8b17 PB |
1023 | default: |
1024 | break; | |
1025 | } | |
1026 | ||
bc8d688f RH |
1027 | /* 32-bit ops generate 32-bit results. For the result is zero test |
1028 | below, we can ignore high bits, but for further optimizations we | |
1029 | need to record that the high bits contain garbage. */ | |
24666baf | 1030 | partmask = mask; |
bc8d688f | 1031 | if (!(def->flags & TCG_OPF_64BIT)) { |
24666baf RH |
1032 | mask |= ~(tcg_target_ulong)0xffffffffu; |
1033 | partmask &= 0xffffffffu; | |
1034 | affected &= 0xffffffffu; | |
f096dc96 AJ |
1035 | } |
1036 | ||
24666baf | 1037 | if (partmask == 0) { |
eabb7b91 | 1038 | tcg_debug_assert(nb_oargs == 1); |
acd93701 | 1039 | tcg_opt_gen_movi(s, op, op->args[0], 0); |
633f6502 PB |
1040 | continue; |
1041 | } | |
1042 | if (affected == 0) { | |
eabb7b91 | 1043 | tcg_debug_assert(nb_oargs == 1); |
acd93701 | 1044 | tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); |
633f6502 PB |
1045 | continue; |
1046 | } | |
1047 | ||
56e49438 | 1048 | /* Simplify expression for "op r, a, 0 => movi r, 0" cases */ |
c45cb8bb | 1049 | switch (opc) { |
170ba88f RH |
1050 | CASE_OP_32_64_VEC(and): |
1051 | CASE_OP_32_64_VEC(mul): | |
03271524 RH |
1052 | CASE_OP_32_64(muluh): |
1053 | CASE_OP_32_64(mulsh): | |
6349039d RH |
1054 | if (arg_is_const(op->args[2]) |
1055 | && arg_info(op->args[2])->val == 0) { | |
acd93701 | 1056 | tcg_opt_gen_movi(s, op, op->args[0], 0); |
53108fb5 KB |
1057 | continue; |
1058 | } | |
1059 | break; | |
56e49438 AJ |
1060 | default: |
1061 | break; | |
1062 | } | |
1063 | ||
1064 | /* Simplify expression for "op r, a, a => mov r, a" cases */ | |
c45cb8bb | 1065 | switch (opc) { |
170ba88f RH |
1066 | CASE_OP_32_64_VEC(or): |
1067 | CASE_OP_32_64_VEC(and): | |
6349039d | 1068 | if (args_are_copies(op->args[1], op->args[2])) { |
acd93701 | 1069 | tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); |
9a81090b KB |
1070 | continue; |
1071 | } | |
1072 | break; | |
fe0de7aa BS |
1073 | default: |
1074 | break; | |
53108fb5 KB |
1075 | } |
1076 | ||
3c94193e | 1077 | /* Simplify expression for "op r, a, a => movi r, 0" cases */ |
c45cb8bb | 1078 | switch (opc) { |
170ba88f RH |
1079 | CASE_OP_32_64_VEC(andc): |
1080 | CASE_OP_32_64_VEC(sub): | |
1081 | CASE_OP_32_64_VEC(xor): | |
6349039d | 1082 | if (args_are_copies(op->args[1], op->args[2])) { |
acd93701 | 1083 | tcg_opt_gen_movi(s, op, op->args[0], 0); |
3c94193e AJ |
1084 | continue; |
1085 | } | |
1086 | break; | |
1087 | default: | |
1088 | break; | |
1089 | } | |
1090 | ||
22613af4 KB |
1091 | /* Propagate constants through copy operations and do constant |
1092 | folding. Constants will be substituted to arguments by register | |
1093 | allocator where needed and possible. Also detect copies. */ | |
c45cb8bb | 1094 | switch (opc) { |
170ba88f | 1095 | CASE_OP_32_64_VEC(mov): |
acd93701 | 1096 | tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); |
97a79eb7 | 1097 | break; |
22613af4 | 1098 | CASE_OP_32_64(movi): |
170ba88f | 1099 | case INDEX_op_dupi_vec: |
acd93701 | 1100 | tcg_opt_gen_movi(s, op, op->args[0], op->args[1]); |
22613af4 | 1101 | break; |
6e14e91b | 1102 | |
170ba88f RH |
1103 | case INDEX_op_dup_vec: |
1104 | if (arg_is_const(op->args[1])) { | |
1105 | tmp = arg_info(op->args[1])->val; | |
1106 | tmp = dup_const(TCGOP_VECE(op), tmp); | |
1107 | tcg_opt_gen_movi(s, op, op->args[0], tmp); | |
1fb57da7 | 1108 | break; |
170ba88f | 1109 | } |
1fb57da7 | 1110 | goto do_default; |
170ba88f | 1111 | |
a640f031 | 1112 | CASE_OP_32_64(not): |
cb25c80a | 1113 | CASE_OP_32_64(neg): |
25c4d9cc RH |
1114 | CASE_OP_32_64(ext8s): |
1115 | CASE_OP_32_64(ext8u): | |
1116 | CASE_OP_32_64(ext16s): | |
1117 | CASE_OP_32_64(ext16u): | |
a768e4e9 | 1118 | CASE_OP_32_64(ctpop): |
6498594c RH |
1119 | CASE_OP_32_64(bswap16): |
1120 | CASE_OP_32_64(bswap32): | |
1121 | case INDEX_op_bswap64_i64: | |
a640f031 KB |
1122 | case INDEX_op_ext32s_i64: |
1123 | case INDEX_op_ext32u_i64: | |
8bcb5c8f AJ |
1124 | case INDEX_op_ext_i32_i64: |
1125 | case INDEX_op_extu_i32_i64: | |
609ad705 RH |
1126 | case INDEX_op_extrl_i64_i32: |
1127 | case INDEX_op_extrh_i64_i32: | |
6349039d RH |
1128 | if (arg_is_const(op->args[1])) { |
1129 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); | |
acd93701 | 1130 | tcg_opt_gen_movi(s, op, op->args[0], tmp); |
6e14e91b | 1131 | break; |
a640f031 | 1132 | } |
6e14e91b RH |
1133 | goto do_default; |
1134 | ||
53108fb5 KB |
1135 | CASE_OP_32_64(add): |
1136 | CASE_OP_32_64(sub): | |
1137 | CASE_OP_32_64(mul): | |
9a81090b KB |
1138 | CASE_OP_32_64(or): |
1139 | CASE_OP_32_64(and): | |
1140 | CASE_OP_32_64(xor): | |
55c0975c KB |
1141 | CASE_OP_32_64(shl): |
1142 | CASE_OP_32_64(shr): | |
1143 | CASE_OP_32_64(sar): | |
25c4d9cc RH |
1144 | CASE_OP_32_64(rotl): |
1145 | CASE_OP_32_64(rotr): | |
cb25c80a RH |
1146 | CASE_OP_32_64(andc): |
1147 | CASE_OP_32_64(orc): | |
1148 | CASE_OP_32_64(eqv): | |
1149 | CASE_OP_32_64(nand): | |
1150 | CASE_OP_32_64(nor): | |
03271524 RH |
1151 | CASE_OP_32_64(muluh): |
1152 | CASE_OP_32_64(mulsh): | |
01547f7f RH |
1153 | CASE_OP_32_64(div): |
1154 | CASE_OP_32_64(divu): | |
1155 | CASE_OP_32_64(rem): | |
1156 | CASE_OP_32_64(remu): | |
6349039d RH |
1157 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { |
1158 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, | |
1159 | arg_info(op->args[2])->val); | |
acd93701 | 1160 | tcg_opt_gen_movi(s, op, op->args[0], tmp); |
6e14e91b | 1161 | break; |
53108fb5 | 1162 | } |
6e14e91b RH |
1163 | goto do_default; |
1164 | ||
0e28d006 RH |
1165 | CASE_OP_32_64(clz): |
1166 | CASE_OP_32_64(ctz): | |
6349039d RH |
1167 | if (arg_is_const(op->args[1])) { |
1168 | TCGArg v = arg_info(op->args[1])->val; | |
0e28d006 RH |
1169 | if (v != 0) { |
1170 | tmp = do_constant_folding(opc, v, 0); | |
acd93701 | 1171 | tcg_opt_gen_movi(s, op, op->args[0], tmp); |
0e28d006 | 1172 | } else { |
acd93701 | 1173 | tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); |
0e28d006 RH |
1174 | } |
1175 | break; | |
1176 | } | |
1177 | goto do_default; | |
1178 | ||
7ef55fc9 | 1179 | CASE_OP_32_64(deposit): |
6349039d RH |
1180 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { |
1181 | tmp = deposit64(arg_info(op->args[1])->val, | |
1182 | op->args[3], op->args[4], | |
1183 | arg_info(op->args[2])->val); | |
acd93701 | 1184 | tcg_opt_gen_movi(s, op, op->args[0], tmp); |
6e14e91b | 1185 | break; |
7ef55fc9 | 1186 | } |
6e14e91b RH |
1187 | goto do_default; |
1188 | ||
7ec8bab3 | 1189 | CASE_OP_32_64(extract): |
6349039d RH |
1190 | if (arg_is_const(op->args[1])) { |
1191 | tmp = extract64(arg_info(op->args[1])->val, | |
acd93701 RH |
1192 | op->args[2], op->args[3]); |
1193 | tcg_opt_gen_movi(s, op, op->args[0], tmp); | |
7ec8bab3 RH |
1194 | break; |
1195 | } | |
1196 | goto do_default; | |
1197 | ||
1198 | CASE_OP_32_64(sextract): | |
6349039d RH |
1199 | if (arg_is_const(op->args[1])) { |
1200 | tmp = sextract64(arg_info(op->args[1])->val, | |
acd93701 RH |
1201 | op->args[2], op->args[3]); |
1202 | tcg_opt_gen_movi(s, op, op->args[0], tmp); | |
7ec8bab3 RH |
1203 | break; |
1204 | } | |
1205 | goto do_default; | |
1206 | ||
fce1296f RH |
1207 | CASE_OP_32_64(extract2): |
1208 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | |
1209 | TCGArg v1 = arg_info(op->args[1])->val; | |
1210 | TCGArg v2 = arg_info(op->args[2])->val; | |
1211 | ||
1212 | if (opc == INDEX_op_extract2_i64) { | |
1213 | tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3])); | |
1214 | } else { | |
80f4d7c3 RH |
1215 | tmp = (int32_t)(((uint32_t)v1 >> op->args[3]) | |
1216 | ((uint32_t)v2 << (32 - op->args[3]))); | |
fce1296f RH |
1217 | } |
1218 | tcg_opt_gen_movi(s, op, op->args[0], tmp); | |
1219 | break; | |
1220 | } | |
1221 | goto do_default; | |
1222 | ||
f8dd19e5 | 1223 | CASE_OP_32_64(setcond): |
acd93701 RH |
1224 | tmp = do_constant_folding_cond(opc, op->args[1], |
1225 | op->args[2], op->args[3]); | |
b336ceb6 | 1226 | if (tmp != 2) { |
acd93701 | 1227 | tcg_opt_gen_movi(s, op, op->args[0], tmp); |
6e14e91b | 1228 | break; |
f8dd19e5 | 1229 | } |
6e14e91b RH |
1230 | goto do_default; |
1231 | ||
fbeaa26c | 1232 | CASE_OP_32_64(brcond): |
acd93701 RH |
1233 | tmp = do_constant_folding_cond(opc, op->args[0], |
1234 | op->args[1], op->args[2]); | |
b336ceb6 AJ |
1235 | if (tmp != 2) { |
1236 | if (tmp) { | |
34184b07 | 1237 | bitmap_zero(temps_used.l, nb_temps); |
c45cb8bb | 1238 | op->opc = INDEX_op_br; |
acd93701 | 1239 | op->args[0] = op->args[3]; |
fbeaa26c | 1240 | } else { |
0c627cdc | 1241 | tcg_op_remove(s, op); |
fbeaa26c | 1242 | } |
6e14e91b | 1243 | break; |
fbeaa26c | 1244 | } |
6e14e91b RH |
1245 | goto do_default; |
1246 | ||
fa01a208 | 1247 | CASE_OP_32_64(movcond): |
acd93701 RH |
1248 | tmp = do_constant_folding_cond(opc, op->args[1], |
1249 | op->args[2], op->args[5]); | |
b336ceb6 | 1250 | if (tmp != 2) { |
acd93701 | 1251 | tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]); |
6e14e91b | 1252 | break; |
fa01a208 | 1253 | } |
6349039d RH |
1254 | if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { |
1255 | tcg_target_ulong tv = arg_info(op->args[3])->val; | |
1256 | tcg_target_ulong fv = arg_info(op->args[4])->val; | |
acd93701 | 1257 | TCGCond cond = op->args[5]; |
333b21b8 RH |
1258 | if (fv == 1 && tv == 0) { |
1259 | cond = tcg_invert_cond(cond); | |
1260 | } else if (!(tv == 1 && fv == 0)) { | |
1261 | goto do_default; | |
1262 | } | |
acd93701 | 1263 | op->args[3] = cond; |
333b21b8 RH |
1264 | op->opc = opc = (opc == INDEX_op_movcond_i32 |
1265 | ? INDEX_op_setcond_i32 | |
1266 | : INDEX_op_setcond_i64); | |
1267 | nb_iargs = 2; | |
1268 | } | |
6e14e91b | 1269 | goto do_default; |
212c328d RH |
1270 | |
1271 | case INDEX_op_add2_i32: | |
1272 | case INDEX_op_sub2_i32: | |
6349039d RH |
1273 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) |
1274 | && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) { | |
1275 | uint32_t al = arg_info(op->args[2])->val; | |
1276 | uint32_t ah = arg_info(op->args[3])->val; | |
1277 | uint32_t bl = arg_info(op->args[4])->val; | |
1278 | uint32_t bh = arg_info(op->args[5])->val; | |
212c328d RH |
1279 | uint64_t a = ((uint64_t)ah << 32) | al; |
1280 | uint64_t b = ((uint64_t)bh << 32) | bl; | |
1281 | TCGArg rl, rh; | |
ac1043f6 | 1282 | TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); |
212c328d | 1283 | |
c45cb8bb | 1284 | if (opc == INDEX_op_add2_i32) { |
212c328d RH |
1285 | a += b; |
1286 | } else { | |
1287 | a -= b; | |
1288 | } | |
1289 | ||
acd93701 RH |
1290 | rl = op->args[0]; |
1291 | rh = op->args[1]; | |
1292 | tcg_opt_gen_movi(s, op, rl, (int32_t)a); | |
1293 | tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); | |
212c328d RH |
1294 | break; |
1295 | } | |
1296 | goto do_default; | |
1414968a RH |
1297 | |
1298 | case INDEX_op_mulu2_i32: | |
6349039d RH |
1299 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { |
1300 | uint32_t a = arg_info(op->args[2])->val; | |
1301 | uint32_t b = arg_info(op->args[3])->val; | |
1414968a RH |
1302 | uint64_t r = (uint64_t)a * b; |
1303 | TCGArg rl, rh; | |
ac1043f6 | 1304 | TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); |
1414968a | 1305 | |
acd93701 RH |
1306 | rl = op->args[0]; |
1307 | rh = op->args[1]; | |
1308 | tcg_opt_gen_movi(s, op, rl, (int32_t)r); | |
1309 | tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); | |
1414968a RH |
1310 | break; |
1311 | } | |
1312 | goto do_default; | |
6e14e91b | 1313 | |
bc1473ef | 1314 | case INDEX_op_brcond2_i32: |
acd93701 RH |
1315 | tmp = do_constant_folding_cond2(&op->args[0], &op->args[2], |
1316 | op->args[4]); | |
6c4382f8 RH |
1317 | if (tmp != 2) { |
1318 | if (tmp) { | |
a763551a | 1319 | do_brcond_true: |
34184b07 | 1320 | bitmap_zero(temps_used.l, nb_temps); |
c45cb8bb | 1321 | op->opc = INDEX_op_br; |
acd93701 | 1322 | op->args[0] = op->args[5]; |
6c4382f8 | 1323 | } else { |
a763551a | 1324 | do_brcond_false: |
0c627cdc | 1325 | tcg_op_remove(s, op); |
6c4382f8 | 1326 | } |
acd93701 RH |
1327 | } else if ((op->args[4] == TCG_COND_LT |
1328 | || op->args[4] == TCG_COND_GE) | |
6349039d RH |
1329 | && arg_is_const(op->args[2]) |
1330 | && arg_info(op->args[2])->val == 0 | |
1331 | && arg_is_const(op->args[3]) | |
1332 | && arg_info(op->args[3])->val == 0) { | |
6c4382f8 RH |
1333 | /* Simplify LT/GE comparisons vs zero to a single compare |
1334 | vs the high word of the input. */ | |
a763551a | 1335 | do_brcond_high: |
34184b07 | 1336 | bitmap_zero(temps_used.l, nb_temps); |
c45cb8bb | 1337 | op->opc = INDEX_op_brcond_i32; |
acd93701 RH |
1338 | op->args[0] = op->args[1]; |
1339 | op->args[1] = op->args[3]; | |
1340 | op->args[2] = op->args[4]; | |
1341 | op->args[3] = op->args[5]; | |
1342 | } else if (op->args[4] == TCG_COND_EQ) { | |
a763551a RH |
1343 | /* Simplify EQ comparisons where one of the pairs |
1344 | can be simplified. */ | |
1345 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1346 | op->args[0], op->args[2], |
1347 | TCG_COND_EQ); | |
a763551a RH |
1348 | if (tmp == 0) { |
1349 | goto do_brcond_false; | |
1350 | } else if (tmp == 1) { | |
1351 | goto do_brcond_high; | |
1352 | } | |
1353 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1354 | op->args[1], op->args[3], |
1355 | TCG_COND_EQ); | |
a763551a RH |
1356 | if (tmp == 0) { |
1357 | goto do_brcond_false; | |
1358 | } else if (tmp != 1) { | |
1359 | goto do_default; | |
1360 | } | |
1361 | do_brcond_low: | |
34184b07 | 1362 | bitmap_zero(temps_used.l, nb_temps); |
c45cb8bb | 1363 | op->opc = INDEX_op_brcond_i32; |
acd93701 RH |
1364 | op->args[1] = op->args[2]; |
1365 | op->args[2] = op->args[4]; | |
1366 | op->args[3] = op->args[5]; | |
1367 | } else if (op->args[4] == TCG_COND_NE) { | |
a763551a RH |
1368 | /* Simplify NE comparisons where one of the pairs |
1369 | can be simplified. */ | |
1370 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1371 | op->args[0], op->args[2], |
1372 | TCG_COND_NE); | |
a763551a RH |
1373 | if (tmp == 0) { |
1374 | goto do_brcond_high; | |
1375 | } else if (tmp == 1) { | |
1376 | goto do_brcond_true; | |
1377 | } | |
1378 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1379 | op->args[1], op->args[3], |
1380 | TCG_COND_NE); | |
a763551a RH |
1381 | if (tmp == 0) { |
1382 | goto do_brcond_low; | |
1383 | } else if (tmp == 1) { | |
1384 | goto do_brcond_true; | |
1385 | } | |
1386 | goto do_default; | |
6c4382f8 RH |
1387 | } else { |
1388 | goto do_default; | |
bc1473ef | 1389 | } |
6c4382f8 | 1390 | break; |
bc1473ef RH |
1391 | |
1392 | case INDEX_op_setcond2_i32: | |
acd93701 RH |
1393 | tmp = do_constant_folding_cond2(&op->args[1], &op->args[3], |
1394 | op->args[5]); | |
6c4382f8 | 1395 | if (tmp != 2) { |
a763551a | 1396 | do_setcond_const: |
acd93701 RH |
1397 | tcg_opt_gen_movi(s, op, op->args[0], tmp); |
1398 | } else if ((op->args[5] == TCG_COND_LT | |
1399 | || op->args[5] == TCG_COND_GE) | |
6349039d RH |
1400 | && arg_is_const(op->args[3]) |
1401 | && arg_info(op->args[3])->val == 0 | |
1402 | && arg_is_const(op->args[4]) | |
1403 | && arg_info(op->args[4])->val == 0) { | |
6c4382f8 RH |
1404 | /* Simplify LT/GE comparisons vs zero to a single compare |
1405 | vs the high word of the input. */ | |
a763551a | 1406 | do_setcond_high: |
acd93701 | 1407 | reset_temp(op->args[0]); |
6349039d | 1408 | arg_info(op->args[0])->mask = 1; |
c45cb8bb | 1409 | op->opc = INDEX_op_setcond_i32; |
acd93701 RH |
1410 | op->args[1] = op->args[2]; |
1411 | op->args[2] = op->args[4]; | |
1412 | op->args[3] = op->args[5]; | |
1413 | } else if (op->args[5] == TCG_COND_EQ) { | |
a763551a RH |
1414 | /* Simplify EQ comparisons where one of the pairs |
1415 | can be simplified. */ | |
1416 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1417 | op->args[1], op->args[3], |
1418 | TCG_COND_EQ); | |
a763551a RH |
1419 | if (tmp == 0) { |
1420 | goto do_setcond_const; | |
1421 | } else if (tmp == 1) { | |
1422 | goto do_setcond_high; | |
1423 | } | |
1424 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1425 | op->args[2], op->args[4], |
1426 | TCG_COND_EQ); | |
a763551a RH |
1427 | if (tmp == 0) { |
1428 | goto do_setcond_high; | |
1429 | } else if (tmp != 1) { | |
1430 | goto do_default; | |
1431 | } | |
1432 | do_setcond_low: | |
acd93701 | 1433 | reset_temp(op->args[0]); |
6349039d | 1434 | arg_info(op->args[0])->mask = 1; |
c45cb8bb | 1435 | op->opc = INDEX_op_setcond_i32; |
acd93701 RH |
1436 | op->args[2] = op->args[3]; |
1437 | op->args[3] = op->args[5]; | |
1438 | } else if (op->args[5] == TCG_COND_NE) { | |
a763551a RH |
1439 | /* Simplify NE comparisons where one of the pairs |
1440 | can be simplified. */ | |
1441 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1442 | op->args[1], op->args[3], |
1443 | TCG_COND_NE); | |
a763551a RH |
1444 | if (tmp == 0) { |
1445 | goto do_setcond_high; | |
1446 | } else if (tmp == 1) { | |
1447 | goto do_setcond_const; | |
1448 | } | |
1449 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1450 | op->args[2], op->args[4], |
1451 | TCG_COND_NE); | |
a763551a RH |
1452 | if (tmp == 0) { |
1453 | goto do_setcond_low; | |
1454 | } else if (tmp == 1) { | |
1455 | goto do_setcond_const; | |
1456 | } | |
1457 | goto do_default; | |
6c4382f8 RH |
1458 | } else { |
1459 | goto do_default; | |
bc1473ef | 1460 | } |
6c4382f8 | 1461 | break; |
bc1473ef | 1462 | |
8f2e8c07 | 1463 | case INDEX_op_call: |
acd93701 | 1464 | if (!(op->args[nb_oargs + nb_iargs + 1] |
cf066674 | 1465 | & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { |
22613af4 | 1466 | for (i = 0; i < nb_globals; i++) { |
1208d7dd | 1467 | if (test_bit(i, temps_used.l)) { |
6349039d | 1468 | reset_ts(&s->temps[i]); |
1208d7dd | 1469 | } |
22613af4 KB |
1470 | } |
1471 | } | |
cf066674 | 1472 | goto do_reset_output; |
6e14e91b | 1473 | |
8f2e8c07 | 1474 | default: |
6e14e91b RH |
1475 | do_default: |
1476 | /* Default case: we know nothing about operation (or were unable | |
1477 | to compute the operation result) so no propagation is done. | |
1478 | We trash everything if the operation is the end of a basic | |
3a9d8b17 PB |
1479 | block, otherwise we only trash the output args. "mask" is |
1480 | the non-zero bits mask for the first output arg. */ | |
a2550660 | 1481 | if (def->flags & TCG_OPF_BB_END) { |
34184b07 | 1482 | bitmap_zero(temps_used.l, nb_temps); |
a2550660 | 1483 | } else { |
cf066674 RH |
1484 | do_reset_output: |
1485 | for (i = 0; i < nb_oargs; i++) { | |
acd93701 | 1486 | reset_temp(op->args[i]); |
3031244b AJ |
1487 | /* Save the corresponding known-zero bits mask for the |
1488 | first output argument (only one supported so far). */ | |
1489 | if (i == 0) { | |
6349039d | 1490 | arg_info(op->args[i])->mask = mask; |
3031244b | 1491 | } |
a2550660 | 1492 | } |
22613af4 | 1493 | } |
8f2e8c07 KB |
1494 | break; |
1495 | } | |
34f93921 PK |
1496 | |
1497 | /* Eliminate duplicate and redundant fence instructions. */ | |
acd93701 | 1498 | if (prev_mb) { |
34f93921 PK |
1499 | switch (opc) { |
1500 | case INDEX_op_mb: | |
1501 | /* Merge two barriers of the same type into one, | |
1502 | * or a weaker barrier into a stronger one, | |
1503 | * or two weaker barriers into a stronger one. | |
1504 | * mb X; mb Y => mb X|Y | |
1505 | * mb; strl => mb; st | |
1506 | * ldaq; mb => ld; mb | |
1507 | * ldaq; strl => ld; mb; st | |
1508 | * Other combinations are also merged into a strong | |
1509 | * barrier. This is stricter than specified but for | |
1510 | * the purposes of TCG is better than not optimizing. | |
1511 | */ | |
acd93701 | 1512 | prev_mb->args[0] |= op->args[0]; |
34f93921 PK |
1513 | tcg_op_remove(s, op); |
1514 | break; | |
1515 | ||
1516 | default: | |
1517 | /* Opcodes that end the block stop the optimization. */ | |
1518 | if ((def->flags & TCG_OPF_BB_END) == 0) { | |
1519 | break; | |
1520 | } | |
1521 | /* fallthru */ | |
1522 | case INDEX_op_qemu_ld_i32: | |
1523 | case INDEX_op_qemu_ld_i64: | |
1524 | case INDEX_op_qemu_st_i32: | |
1525 | case INDEX_op_qemu_st_i64: | |
1526 | case INDEX_op_call: | |
1527 | /* Opcodes that touch guest memory stop the optimization. */ | |
acd93701 | 1528 | prev_mb = NULL; |
34f93921 PK |
1529 | break; |
1530 | } | |
1531 | } else if (opc == INDEX_op_mb) { | |
acd93701 | 1532 | prev_mb = op; |
34f93921 | 1533 | } |
8f2e8c07 | 1534 | } |
8f2e8c07 | 1535 | } |