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1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20#ifndef QEMU_ARM_CPU_QOM_H
21#define QEMU_ARM_CPU_QOM_H
22
14cccb61 23#include "qom/cpu.h"
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24
25#define TYPE_ARM_CPU "arm-cpu"
26
27#define ARM_CPU_CLASS(klass) \
28 OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
29#define ARM_CPU(obj) \
30 OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
31#define ARM_CPU_GET_CLASS(obj) \
32 OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
33
34/**
35 * ARMCPUClass:
14969266 36 * @parent_realize: The parent class' realize handler.
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37 * @parent_reset: The parent class' reset handler.
38 *
39 * An ARM CPU model.
40 */
41typedef struct ARMCPUClass {
42 /*< private >*/
43 CPUClass parent_class;
44 /*< public >*/
45
14969266 46 DeviceRealize parent_realize;
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47 void (*parent_reset)(CPUState *cpu);
48} ARMCPUClass;
49
50/**
51 * ARMCPU:
52 * @env: #CPUARMState
53 *
54 * An ARM CPU core.
55 */
56typedef struct ARMCPU {
57 /*< private >*/
58 CPUState parent_obj;
59 /*< public >*/
60
61 CPUARMState env;
777dc784 62
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63 /* Coprocessor information */
64 GHashTable *cp_regs;
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65 /* For marshalling (mostly coprocessor) register state between the
66 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
67 * we use these arrays.
68 */
69 /* List of register indexes managed via these arrays; (full KVM style
70 * 64 bit indexes, not CPRegInfo 32 bit indexes)
71 */
72 uint64_t *cpreg_indexes;
73 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
74 uint64_t *cpreg_values;
2d8e5a0e 75 /* Length of the indexes, values, reset_values arrays */
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76 int32_t cpreg_array_len;
77 /* These are used only for migration: incoming data arrives in
78 * these fields and is sanity checked in post_load before copying
79 * to the working data structures above.
80 */
81 uint64_t *cpreg_vmstate_indexes;
82 uint64_t *cpreg_vmstate_values;
83 int32_t cpreg_vmstate_array_len;
4b6a83fb 84
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85 /* Timers used by the generic (architected) timer */
86 QEMUTimer *gt_timer[NUM_GTIMERS];
87 /* GPIO outputs for generic timer */
88 qemu_irq gt_timer_outputs[NUM_GTIMERS];
89
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90 /* MemoryRegion to use for secure physical accesses */
91 MemoryRegion *secure_memory;
92
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93 /* 'compatible' string for this CPU for Linux device trees */
94 const char *dtb_compatible;
95
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96 /* PSCI version for this CPU
97 * Bits[31:16] = Major Version
98 * Bits[15:0] = Minor Version
99 */
100 uint32_t psci_version;
101
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102 /* Should CPU start in PSCI powered-off state? */
103 bool start_powered_off;
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104 /* CPU currently in PSCI powered-off state */
105 bool powered_off;
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106 /* CPU has security extension */
107 bool has_el3;
5de16430 108
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109 /* CPU has memory protection unit */
110 bool has_mpu;
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111 /* PMSAv7 MPU number of supported regions */
112 uint32_t pmsav7_dregion;
8f325f56 113
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114 /* PSCI conduit used to invoke PSCI methods
115 * 0 - disabled, 1 - smc, 2 - hvc
116 */
117 uint32_t psci_conduit;
118
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119 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
120 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
121 */
122 uint32_t kvm_target;
123
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124 /* KVM init features for this CPU */
125 uint32_t kvm_init_features[7];
126
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127 /* Uniprocessor system with MP extensions */
128 bool mp_is_up;
129
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130 /* The instance init functions for implementation-specific subclasses
131 * set these fields to specify the implementation-dependent values of
132 * various constant registers and reset values of non-constant
133 * registers.
134 * Some of these might become QOM properties eventually.
135 * Field names match the official register names as defined in the
136 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
137 * is used for reset values of non-constant registers; no reset_
138 * prefix means a constant register.
139 */
140 uint32_t midr;
13b72b2b 141 uint32_t revidr;
325b3cef 142 uint32_t reset_fpsid;
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143 uint32_t mvfr0;
144 uint32_t mvfr1;
a50c0f51 145 uint32_t mvfr2;
64e1671f 146 uint32_t ctr;
0ca7e01c 147 uint32_t reset_sctlr;
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148 uint32_t id_pfr0;
149 uint32_t id_pfr1;
150 uint32_t id_dfr0;
151 uint32_t id_afr0;
152 uint32_t id_mmfr0;
153 uint32_t id_mmfr1;
154 uint32_t id_mmfr2;
155 uint32_t id_mmfr3;
156 uint32_t id_isar0;
157 uint32_t id_isar1;
158 uint32_t id_isar2;
159 uint32_t id_isar3;
160 uint32_t id_isar4;
161 uint32_t id_isar5;
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162 uint64_t id_aa64pfr0;
163 uint64_t id_aa64pfr1;
164 uint64_t id_aa64dfr0;
165 uint64_t id_aa64dfr1;
166 uint64_t id_aa64afr0;
167 uint64_t id_aa64afr1;
168 uint64_t id_aa64isar0;
169 uint64_t id_aa64isar1;
170 uint64_t id_aa64mmfr0;
171 uint64_t id_aa64mmfr1;
48eb3ae6 172 uint32_t dbgdidr;
85df3786 173 uint32_t clidr;
eb5e1d3c 174 uint64_t mp_affinity; /* MP ID without feature bits */
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175 /* The elements of this array are the CCSIDR values for each cache,
176 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
177 */
178 uint32_t ccsidr[16];
f318cec6 179 uint64_t reset_cbar;
2771db27 180 uint32_t reset_auxcr;
68e0a40a 181 bool reset_hivecs;
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182 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
183 uint32_t dcz_blocksize;
3933443e 184 uint64_t rvbar;
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185} ARMCPU;
186
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187#define TYPE_AARCH64_CPU "aarch64-cpu"
188#define AARCH64_CPU_CLASS(klass) \
189 OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
190#define AARCH64_CPU_GET_CLASS(obj) \
191 OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
192
193typedef struct AArch64CPUClass {
194 /*< private >*/
195 ARMCPUClass parent_class;
196 /*< public >*/
197} AArch64CPUClass;
198
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199static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
200{
6e42be7c 201 return container_of(env, ARMCPU, env);
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202}
203
204#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
205
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206#define ENV_OFFSET offsetof(ARMCPU, env)
207
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208#ifndef CONFIG_USER_ONLY
209extern const struct VMStateDescription vmstate_arm_cpu;
210#endif
211
2ceb98c0 212void register_cp_regs_for_features(ARMCPU *cpu);
721fae12 213void init_cpreg_list(ARMCPU *cpu);
dec9c2d4 214
97a8ea5a 215void arm_cpu_do_interrupt(CPUState *cpu);
e6f010cc 216void arm_v7m_cpu_do_interrupt(CPUState *cpu);
e8925712 217bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
97a8ea5a 218
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219void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
220 int flags);
221
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222hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
223 MemTxAttrs *attrs);
00b941e5 224
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225int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
226int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
227
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228int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
229 int cpuid, void *opaque);
230int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
231 int cpuid, void *opaque);
232
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233/* Callback functions for the generic timer's timers. */
234void arm_gt_ptimer_cb(void *opaque);
235void arm_gt_vtimer_cb(void *opaque);
b0e66d95 236void arm_gt_htimer_cb(void *opaque);
b4d3978c 237void arm_gt_stimer_cb(void *opaque);
55d284af 238
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239#define ARM_AFF0_SHIFT 0
240#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
241#define ARM_AFF1_SHIFT 8
242#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
243#define ARM_AFF2_SHIFT 16
244#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
245#define ARM_AFF3_SHIFT 32
246#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
247
248#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
249#define ARM64_AFFINITY_MASK \
250 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
251
14ade10f 252#ifdef TARGET_AARCH64
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253int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
254int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
f3a9b694 255#endif
52e60cdd 256
dec9c2d4 257#endif
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