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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_ARM_CPU_QOM_H | |
21 | #define QEMU_ARM_CPU_QOM_H | |
22 | ||
14cccb61 | 23 | #include "qom/cpu.h" |
dec9c2d4 AF |
24 | |
25 | #define TYPE_ARM_CPU "arm-cpu" | |
26 | ||
27 | #define ARM_CPU_CLASS(klass) \ | |
28 | OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU) | |
29 | #define ARM_CPU(obj) \ | |
30 | OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU) | |
31 | #define ARM_CPU_GET_CLASS(obj) \ | |
32 | OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) | |
33 | ||
34 | /** | |
35 | * ARMCPUClass: | |
14969266 | 36 | * @parent_realize: The parent class' realize handler. |
dec9c2d4 AF |
37 | * @parent_reset: The parent class' reset handler. |
38 | * | |
39 | * An ARM CPU model. | |
40 | */ | |
41 | typedef struct ARMCPUClass { | |
42 | /*< private >*/ | |
43 | CPUClass parent_class; | |
44 | /*< public >*/ | |
45 | ||
14969266 | 46 | DeviceRealize parent_realize; |
dec9c2d4 AF |
47 | void (*parent_reset)(CPUState *cpu); |
48 | } ARMCPUClass; | |
49 | ||
50 | /** | |
51 | * ARMCPU: | |
52 | * @env: #CPUARMState | |
53 | * | |
54 | * An ARM CPU core. | |
55 | */ | |
56 | typedef struct ARMCPU { | |
57 | /*< private >*/ | |
58 | CPUState parent_obj; | |
59 | /*< public >*/ | |
60 | ||
61 | CPUARMState env; | |
777dc784 | 62 | |
4b6a83fb PM |
63 | /* Coprocessor information */ |
64 | GHashTable *cp_regs; | |
721fae12 PM |
65 | /* For marshalling (mostly coprocessor) register state between the |
66 | * kernel and QEMU (for KVM) and between two QEMUs (for migration), | |
67 | * we use these arrays. | |
68 | */ | |
69 | /* List of register indexes managed via these arrays; (full KVM style | |
70 | * 64 bit indexes, not CPRegInfo 32 bit indexes) | |
71 | */ | |
72 | uint64_t *cpreg_indexes; | |
73 | /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ | |
74 | uint64_t *cpreg_values; | |
2d8e5a0e | 75 | /* Length of the indexes, values, reset_values arrays */ |
721fae12 PM |
76 | int32_t cpreg_array_len; |
77 | /* These are used only for migration: incoming data arrives in | |
78 | * these fields and is sanity checked in post_load before copying | |
79 | * to the working data structures above. | |
80 | */ | |
81 | uint64_t *cpreg_vmstate_indexes; | |
82 | uint64_t *cpreg_vmstate_values; | |
83 | int32_t cpreg_vmstate_array_len; | |
4b6a83fb | 84 | |
55d284af PM |
85 | /* Timers used by the generic (architected) timer */ |
86 | QEMUTimer *gt_timer[NUM_GTIMERS]; | |
87 | /* GPIO outputs for generic timer */ | |
88 | qemu_irq gt_timer_outputs[NUM_GTIMERS]; | |
89 | ||
54d3e3f5 PM |
90 | /* 'compatible' string for this CPU for Linux device trees */ |
91 | const char *dtb_compatible; | |
92 | ||
dd032e34 PS |
93 | /* PSCI version for this CPU |
94 | * Bits[31:16] = Major Version | |
95 | * Bits[15:0] = Minor Version | |
96 | */ | |
97 | uint32_t psci_version; | |
98 | ||
5de16430 PM |
99 | /* Should CPU start in PSCI powered-off state? */ |
100 | bool start_powered_off; | |
101 | ||
3541addc PM |
102 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or |
103 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | |
104 | */ | |
105 | uint32_t kvm_target; | |
106 | ||
228d5e04 PS |
107 | /* KVM init features for this CPU */ |
108 | uint32_t kvm_init_features[7]; | |
109 | ||
777dc784 PM |
110 | /* The instance init functions for implementation-specific subclasses |
111 | * set these fields to specify the implementation-dependent values of | |
112 | * various constant registers and reset values of non-constant | |
113 | * registers. | |
114 | * Some of these might become QOM properties eventually. | |
115 | * Field names match the official register names as defined in the | |
116 | * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix | |
117 | * is used for reset values of non-constant registers; no reset_ | |
118 | * prefix means a constant register. | |
119 | */ | |
120 | uint32_t midr; | |
325b3cef | 121 | uint32_t reset_fpsid; |
bd35c355 PM |
122 | uint32_t mvfr0; |
123 | uint32_t mvfr1; | |
a50c0f51 | 124 | uint32_t mvfr2; |
64e1671f | 125 | uint32_t ctr; |
0ca7e01c | 126 | uint32_t reset_sctlr; |
2e4d7e3e PM |
127 | uint32_t id_pfr0; |
128 | uint32_t id_pfr1; | |
129 | uint32_t id_dfr0; | |
130 | uint32_t id_afr0; | |
131 | uint32_t id_mmfr0; | |
132 | uint32_t id_mmfr1; | |
133 | uint32_t id_mmfr2; | |
134 | uint32_t id_mmfr3; | |
135 | uint32_t id_isar0; | |
136 | uint32_t id_isar1; | |
137 | uint32_t id_isar2; | |
138 | uint32_t id_isar3; | |
139 | uint32_t id_isar4; | |
140 | uint32_t id_isar5; | |
e60cef86 PM |
141 | uint64_t id_aa64pfr0; |
142 | uint64_t id_aa64pfr1; | |
143 | uint64_t id_aa64dfr0; | |
144 | uint64_t id_aa64dfr1; | |
145 | uint64_t id_aa64afr0; | |
146 | uint64_t id_aa64afr1; | |
147 | uint64_t id_aa64isar0; | |
148 | uint64_t id_aa64isar1; | |
149 | uint64_t id_aa64mmfr0; | |
150 | uint64_t id_aa64mmfr1; | |
85df3786 PM |
151 | uint32_t clidr; |
152 | /* The elements of this array are the CCSIDR values for each cache, | |
153 | * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. | |
154 | */ | |
155 | uint32_t ccsidr[16]; | |
f318cec6 | 156 | uint64_t reset_cbar; |
2771db27 | 157 | uint32_t reset_auxcr; |
68e0a40a | 158 | bool reset_hivecs; |
aca3f40b PM |
159 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
160 | uint32_t dcz_blocksize; | |
3933443e | 161 | uint64_t rvbar; |
dec9c2d4 AF |
162 | } ARMCPU; |
163 | ||
d14d42f1 PM |
164 | #define TYPE_AARCH64_CPU "aarch64-cpu" |
165 | #define AARCH64_CPU_CLASS(klass) \ | |
166 | OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU) | |
167 | #define AARCH64_CPU_GET_CLASS(obj) \ | |
168 | OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU) | |
169 | ||
170 | typedef struct AArch64CPUClass { | |
171 | /*< private >*/ | |
172 | ARMCPUClass parent_class; | |
173 | /*< public >*/ | |
174 | } AArch64CPUClass; | |
175 | ||
dec9c2d4 AF |
176 | static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) |
177 | { | |
6e42be7c | 178 | return container_of(env, ARMCPU, env); |
dec9c2d4 AF |
179 | } |
180 | ||
181 | #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) | |
182 | ||
fadf9825 AF |
183 | #define ENV_OFFSET offsetof(ARMCPU, env) |
184 | ||
3cc1d208 JQ |
185 | #ifndef CONFIG_USER_ONLY |
186 | extern const struct VMStateDescription vmstate_arm_cpu; | |
187 | #endif | |
188 | ||
2ceb98c0 | 189 | void register_cp_regs_for_features(ARMCPU *cpu); |
721fae12 | 190 | void init_cpreg_list(ARMCPU *cpu); |
dec9c2d4 | 191 | |
97a8ea5a | 192 | void arm_cpu_do_interrupt(CPUState *cpu); |
e6f010cc | 193 | void arm_v7m_cpu_do_interrupt(CPUState *cpu); |
97a8ea5a | 194 | |
878096ee AF |
195 | void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
196 | int flags); | |
197 | ||
00b941e5 AF |
198 | hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
199 | ||
5b50e790 AF |
200 | int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
201 | int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
202 | ||
55d284af PM |
203 | /* Callback functions for the generic timer's timers. */ |
204 | void arm_gt_ptimer_cb(void *opaque); | |
205 | void arm_gt_vtimer_cb(void *opaque); | |
206 | ||
14ade10f | 207 | #ifdef TARGET_AARCH64 |
96c04212 AG |
208 | int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
209 | int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
52e60cdd RH |
210 | |
211 | void aarch64_cpu_do_interrupt(CPUState *cs); | |
14ade10f AG |
212 | #endif |
213 | ||
dec9c2d4 | 214 | #endif |