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Commit | Line | Data |
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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
181962fd | 22 | #include "target/arm/idau.h" |
929e754d | 23 | #include "qemu/error-report.h" |
da34e65c | 24 | #include "qapi/error.h" |
778c3a06 | 25 | #include "cpu.h" |
ccd38087 | 26 | #include "internals.h" |
dec9c2d4 | 27 | #include "qemu-common.h" |
63c91552 | 28 | #include "exec/exec-all.h" |
5de16430 | 29 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
30 | #if !defined(CONFIG_USER_ONLY) |
31 | #include "hw/loader.h" | |
32 | #endif | |
7c1840b6 | 33 | #include "hw/arm/arm.h" |
9c17d615 | 34 | #include "sysemu/sysemu.h" |
b3946626 | 35 | #include "sysemu/hw_accel.h" |
50a2c6e5 | 36 | #include "kvm_arm.h" |
110f6c70 | 37 | #include "disas/capstone.h" |
24f91e81 | 38 | #include "fpu/softfloat.h" |
dec9c2d4 | 39 | |
f45748f1 AF |
40 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
41 | { | |
42 | ARMCPU *cpu = ARM_CPU(cs); | |
43 | ||
44 | cpu->env.regs[15] = value; | |
45 | } | |
46 | ||
8c2e1b00 AF |
47 | static bool arm_cpu_has_work(CPUState *cs) |
48 | { | |
543486db RH |
49 | ARMCPU *cpu = ARM_CPU(cs); |
50 | ||
062ba099 | 51 | return (cpu->power_state != PSCI_OFF) |
543486db | 52 | && cs->interrupt_request & |
136e67e9 EI |
53 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
54 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
55 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
56 | } |
57 | ||
b5c53d1b AL |
58 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
59 | void *opaque) | |
60 | { | |
61 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); | |
62 | ||
63 | entry->hook = hook; | |
64 | entry->opaque = opaque; | |
65 | ||
66 | QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); | |
67 | } | |
68 | ||
08267487 | 69 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
bd7d00fc PM |
70 | void *opaque) |
71 | { | |
08267487 AL |
72 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); |
73 | ||
74 | entry->hook = hook; | |
75 | entry->opaque = opaque; | |
76 | ||
77 | QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); | |
bd7d00fc PM |
78 | } |
79 | ||
4b6a83fb PM |
80 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
81 | { | |
82 | /* Reset a single ARMCPRegInfo register */ | |
83 | ARMCPRegInfo *ri = value; | |
84 | ARMCPU *cpu = opaque; | |
85 | ||
b061a82b | 86 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
87 | return; |
88 | } | |
89 | ||
90 | if (ri->resetfn) { | |
91 | ri->resetfn(&cpu->env, ri); | |
92 | return; | |
93 | } | |
94 | ||
95 | /* A zero offset is never possible as it would be regs[0] | |
96 | * so we use it to indicate that reset is being handled elsewhere. | |
97 | * This is basically only used for fields in non-core coprocessors | |
98 | * (like the pxa2xx ones). | |
99 | */ | |
100 | if (!ri->fieldoffset) { | |
101 | return; | |
102 | } | |
103 | ||
67ed771d | 104 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
105 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
106 | } else { | |
107 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
108 | } | |
109 | } | |
110 | ||
49a66191 PM |
111 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
112 | { | |
113 | /* Purely an assertion check: we've already done reset once, | |
114 | * so now check that running the reset for the cpreg doesn't | |
115 | * change its value. This traps bugs where two different cpregs | |
116 | * both try to reset the same state field but to different values. | |
117 | */ | |
118 | ARMCPRegInfo *ri = value; | |
119 | ARMCPU *cpu = opaque; | |
120 | uint64_t oldvalue, newvalue; | |
121 | ||
122 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | |
123 | return; | |
124 | } | |
125 | ||
126 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
127 | cp_reg_reset(key, value, opaque); | |
128 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
129 | assert(oldvalue == newvalue); | |
130 | } | |
131 | ||
dec9c2d4 AF |
132 | /* CPUClass::reset() */ |
133 | static void arm_cpu_reset(CPUState *s) | |
134 | { | |
135 | ARMCPU *cpu = ARM_CPU(s); | |
136 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 137 | CPUARMState *env = &cpu->env; |
3c30dd5a | 138 | |
dec9c2d4 AF |
139 | acc->parent_reset(s); |
140 | ||
1f5c00cf AB |
141 | memset(env, 0, offsetof(CPUARMState, end_reset_fields)); |
142 | ||
4b6a83fb | 143 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
144 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
145 | ||
3c30dd5a PM |
146 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
147 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
148 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
a50c0f51 | 149 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; |
3c30dd5a | 150 | |
062ba099 | 151 | cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; |
543486db RH |
152 | s->halted = cpu->start_powered_off; |
153 | ||
3c30dd5a PM |
154 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
155 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
156 | } | |
157 | ||
3926cc84 AG |
158 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
159 | /* 64 bit CPUs always start in 64 bit mode */ | |
160 | env->aarch64 = 1; | |
d356312f PM |
161 | #if defined(CONFIG_USER_ONLY) |
162 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 163 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 164 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
8c6afa6a | 165 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 166 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
d356312f | 167 | #else |
5097227c GB |
168 | /* Reset into the highest available EL */ |
169 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
170 | env->pstate = PSTATE_MODE_EL3h; | |
171 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
172 | env->pstate = PSTATE_MODE_EL2h; | |
173 | } else { | |
174 | env->pstate = PSTATE_MODE_EL1h; | |
175 | } | |
3933443e | 176 | env->pc = cpu->rvbar; |
8c6afa6a PM |
177 | #endif |
178 | } else { | |
179 | #if defined(CONFIG_USER_ONLY) | |
180 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 181 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 182 | #endif |
3926cc84 AG |
183 | } |
184 | ||
3c30dd5a PM |
185 | #if defined(CONFIG_USER_ONLY) |
186 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
187 | /* For user mode we must enable access to coprocessors */ | |
188 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
189 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
190 | env->cp15.c15_cpar = 3; | |
191 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
192 | env->cp15.c15_cpar = 1; | |
193 | } | |
194 | #else | |
195 | /* SVC mode with interrupts disabled. */ | |
4cc35614 PM |
196 | env->uncached_cpsr = ARM_CPU_MODE_SVC; |
197 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
dc7abe4d | 198 | |
531c60a9 | 199 | if (arm_feature(env, ARM_FEATURE_M)) { |
6e3cf5df MG |
200 | uint32_t initial_msp; /* Loaded from 0x0 */ |
201 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 202 | uint8_t *rom; |
38e2a77c | 203 | uint32_t vecbase; |
6e3cf5df | 204 | |
1e577cc7 PM |
205 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
206 | env->v7m.secure = true; | |
3b2e9344 PM |
207 | } else { |
208 | /* This bit resets to 0 if security is supported, but 1 if | |
209 | * it is not. The bit is not present in v7M, but we set it | |
210 | * here so we can avoid having to make checks on it conditional | |
211 | * on ARM_FEATURE_V8 (we don't let the guest see the bit). | |
212 | */ | |
213 | env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; | |
1e577cc7 PM |
214 | } |
215 | ||
9d40cd8a | 216 | /* In v7M the reset value of this bit is IMPDEF, but ARM recommends |
2c4da50d | 217 | * that it resets to 1, so QEMU always does that rather than making |
9d40cd8a | 218 | * it dependent on CPU model. In v8M it is RES1. |
2c4da50d | 219 | */ |
9d40cd8a PM |
220 | env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; |
221 | env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | |
222 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
223 | /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | |
224 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
225 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
226 | } | |
2c4da50d | 227 | |
056f43df PM |
228 | /* Unlike A/R profile, M profile defines the reset LR value */ |
229 | env->regs[14] = 0xffffffff; | |
230 | ||
38e2a77c PM |
231 | env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; |
232 | ||
233 | /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | |
234 | vecbase = env->v7m.vecbase[env->v7m.secure]; | |
235 | rom = rom_ptr(vecbase); | |
3c30dd5a | 236 | if (rom) { |
6e3cf5df MG |
237 | /* Address zero is covered by ROM which hasn't yet been |
238 | * copied into physical memory. | |
239 | */ | |
240 | initial_msp = ldl_p(rom); | |
241 | initial_pc = ldl_p(rom + 4); | |
242 | } else { | |
243 | /* Address zero not covered by a ROM blob, or the ROM blob | |
244 | * is in non-modifiable memory and this is a second reset after | |
245 | * it got copied into memory. In the latter case, rom_ptr | |
246 | * will return a NULL pointer and we should use ldl_phys instead. | |
247 | */ | |
38e2a77c PM |
248 | initial_msp = ldl_phys(s->as, vecbase); |
249 | initial_pc = ldl_phys(s->as, vecbase + 4); | |
3c30dd5a | 250 | } |
6e3cf5df MG |
251 | |
252 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
253 | env->regs[15] = initial_pc & ~1; | |
254 | env->thumb = initial_pc & 1; | |
3c30dd5a | 255 | } |
387f9806 | 256 | |
137feaa9 FA |
257 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
258 | * executing as AArch32 then check if highvecs are enabled and | |
259 | * adjust the PC accordingly. | |
260 | */ | |
261 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 262 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
263 | } |
264 | ||
dc3c4c14 PM |
265 | /* M profile requires that reset clears the exclusive monitor; |
266 | * A profile does not, but clearing it makes more sense than having it | |
267 | * set with an exclusive access on address zero. | |
268 | */ | |
269 | arm_clear_exclusive(env); | |
270 | ||
3c30dd5a | 271 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a | 272 | #endif |
69ceea64 | 273 | |
0e1a46bb | 274 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
69ceea64 | 275 | if (cpu->pmsav7_dregion > 0) { |
0e1a46bb | 276 | if (arm_feature(env, ARM_FEATURE_V8)) { |
62c58ee0 PM |
277 | memset(env->pmsav8.rbar[M_REG_NS], 0, |
278 | sizeof(*env->pmsav8.rbar[M_REG_NS]) | |
279 | * cpu->pmsav7_dregion); | |
280 | memset(env->pmsav8.rlar[M_REG_NS], 0, | |
281 | sizeof(*env->pmsav8.rlar[M_REG_NS]) | |
282 | * cpu->pmsav7_dregion); | |
283 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
284 | memset(env->pmsav8.rbar[M_REG_S], 0, | |
285 | sizeof(*env->pmsav8.rbar[M_REG_S]) | |
286 | * cpu->pmsav7_dregion); | |
287 | memset(env->pmsav8.rlar[M_REG_S], 0, | |
288 | sizeof(*env->pmsav8.rlar[M_REG_S]) | |
289 | * cpu->pmsav7_dregion); | |
290 | } | |
0e1a46bb PM |
291 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
292 | memset(env->pmsav7.drbar, 0, | |
293 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | |
294 | memset(env->pmsav7.drsr, 0, | |
295 | sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | |
296 | memset(env->pmsav7.dracr, 0, | |
297 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | |
298 | } | |
69ceea64 | 299 | } |
1bc04a88 PM |
300 | env->pmsav7.rnr[M_REG_NS] = 0; |
301 | env->pmsav7.rnr[M_REG_S] = 0; | |
4125e6fe PM |
302 | env->pmsav8.mair0[M_REG_NS] = 0; |
303 | env->pmsav8.mair0[M_REG_S] = 0; | |
304 | env->pmsav8.mair1[M_REG_NS] = 0; | |
305 | env->pmsav8.mair1[M_REG_S] = 0; | |
69ceea64 PM |
306 | } |
307 | ||
9901c576 PM |
308 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
309 | if (cpu->sau_sregion > 0) { | |
310 | memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); | |
311 | memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); | |
312 | } | |
313 | env->sau.rnr = 0; | |
314 | /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what | |
315 | * the Cortex-M33 does. | |
316 | */ | |
317 | env->sau.ctrl = 0; | |
318 | } | |
319 | ||
3c30dd5a PM |
320 | set_flush_to_zero(1, &env->vfp.standard_fp_status); |
321 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
322 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
323 | set_float_detect_tininess(float_tininess_before_rounding, | |
324 | &env->vfp.fp_status); | |
325 | set_float_detect_tininess(float_tininess_before_rounding, | |
326 | &env->vfp.standard_fp_status); | |
bcc531f0 PM |
327 | set_float_detect_tininess(float_tininess_before_rounding, |
328 | &env->vfp.fp_status_f16); | |
50a2c6e5 PB |
329 | #ifndef CONFIG_USER_ONLY |
330 | if (kvm_enabled()) { | |
331 | kvm_arm_reset_vcpu(cpu); | |
332 | } | |
333 | #endif | |
9ee98ce8 | 334 | |
46747d15 | 335 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 336 | hw_watchpoint_update_all(cpu); |
dec9c2d4 AF |
337 | } |
338 | ||
e8925712 RH |
339 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
340 | { | |
341 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
342 | CPUARMState *env = cs->env_ptr; |
343 | uint32_t cur_el = arm_current_el(env); | |
344 | bool secure = arm_is_secure(env); | |
345 | uint32_t target_el; | |
346 | uint32_t excp_idx; | |
e8925712 RH |
347 | bool ret = false; |
348 | ||
012a906b GB |
349 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
350 | excp_idx = EXCP_FIQ; | |
351 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
352 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
353 | cs->exception_index = excp_idx; | |
354 | env->exception.target_el = target_el; | |
355 | cc->do_interrupt(cs); | |
356 | ret = true; | |
357 | } | |
e8925712 | 358 | } |
012a906b GB |
359 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
360 | excp_idx = EXCP_IRQ; | |
361 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
362 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
363 | cs->exception_index = excp_idx; | |
364 | env->exception.target_el = target_el; | |
365 | cc->do_interrupt(cs); | |
366 | ret = true; | |
367 | } | |
e8925712 | 368 | } |
012a906b GB |
369 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
370 | excp_idx = EXCP_VIRQ; | |
371 | target_el = 1; | |
372 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
373 | cs->exception_index = excp_idx; | |
374 | env->exception.target_el = target_el; | |
375 | cc->do_interrupt(cs); | |
376 | ret = true; | |
377 | } | |
136e67e9 | 378 | } |
012a906b GB |
379 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
380 | excp_idx = EXCP_VFIQ; | |
381 | target_el = 1; | |
382 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
383 | cs->exception_index = excp_idx; | |
384 | env->exception.target_el = target_el; | |
385 | cc->do_interrupt(cs); | |
386 | ret = true; | |
387 | } | |
136e67e9 | 388 | } |
e8925712 RH |
389 | |
390 | return ret; | |
391 | } | |
392 | ||
b5c633c5 PM |
393 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
394 | static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
395 | { | |
396 | CPUClass *cc = CPU_GET_CLASS(cs); | |
397 | ARMCPU *cpu = ARM_CPU(cs); | |
398 | CPUARMState *env = &cpu->env; | |
399 | bool ret = false; | |
400 | ||
f4e8e4ed | 401 | /* ARMv7-M interrupt masking works differently than -A or -R. |
7ecdaa4a PM |
402 | * There is no FIQ/IRQ distinction. Instead of I and F bits |
403 | * masking FIQ and IRQ interrupts, an exception is taken only | |
404 | * if it is higher priority than the current execution priority | |
405 | * (which depends on state like BASEPRI, FAULTMASK and the | |
406 | * currently active exception). | |
b5c633c5 PM |
407 | */ |
408 | if (interrupt_request & CPU_INTERRUPT_HARD | |
f4e8e4ed | 409 | && (armv7m_nvic_can_take_pending_exception(env->nvic))) { |
b5c633c5 PM |
410 | cs->exception_index = EXCP_IRQ; |
411 | cc->do_interrupt(cs); | |
412 | ret = true; | |
413 | } | |
414 | return ret; | |
415 | } | |
416 | #endif | |
417 | ||
7c1840b6 PM |
418 | #ifndef CONFIG_USER_ONLY |
419 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
420 | { | |
421 | ARMCPU *cpu = opaque; | |
136e67e9 | 422 | CPUARMState *env = &cpu->env; |
7c1840b6 | 423 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
424 | static const int mask[] = { |
425 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
426 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
427 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
428 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
429 | }; | |
7c1840b6 PM |
430 | |
431 | switch (irq) { | |
136e67e9 EI |
432 | case ARM_CPU_VIRQ: |
433 | case ARM_CPU_VFIQ: | |
f128bf29 | 434 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
136e67e9 EI |
435 | /* fall through */ |
436 | case ARM_CPU_IRQ: | |
7c1840b6 PM |
437 | case ARM_CPU_FIQ: |
438 | if (level) { | |
136e67e9 | 439 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 440 | } else { |
136e67e9 | 441 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
442 | } |
443 | break; | |
444 | default: | |
8f6fd322 | 445 | g_assert_not_reached(); |
7c1840b6 PM |
446 | } |
447 | } | |
448 | ||
449 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
450 | { | |
451 | #ifdef CONFIG_KVM | |
452 | ARMCPU *cpu = opaque; | |
453 | CPUState *cs = CPU(cpu); | |
454 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
455 | ||
456 | switch (irq) { | |
457 | case ARM_CPU_IRQ: | |
458 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
459 | break; | |
460 | case ARM_CPU_FIQ: | |
461 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
462 | break; | |
463 | default: | |
8f6fd322 | 464 | g_assert_not_reached(); |
7c1840b6 PM |
465 | } |
466 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
467 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
468 | #endif | |
469 | } | |
84f2bed3 | 470 | |
ed50ff78 | 471 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
472 | { |
473 | ARMCPU *cpu = ARM_CPU(cs); | |
474 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
475 | |
476 | cpu_synchronize_state(cs); | |
ed50ff78 | 477 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
478 | } |
479 | ||
7c1840b6 PM |
480 | #endif |
481 | ||
581be094 PM |
482 | static inline void set_feature(CPUARMState *env, int feature) |
483 | { | |
918f5dca | 484 | env->features |= 1ULL << feature; |
581be094 PM |
485 | } |
486 | ||
08828484 GB |
487 | static inline void unset_feature(CPUARMState *env, int feature) |
488 | { | |
489 | env->features &= ~(1ULL << feature); | |
490 | } | |
491 | ||
48440620 PC |
492 | static int |
493 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) | |
494 | { | |
495 | return print_insn_arm(pc | 1, info); | |
496 | } | |
497 | ||
498 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | |
499 | { | |
500 | ARMCPU *ac = ARM_CPU(cpu); | |
501 | CPUARMState *env = &ac->env; | |
7bcdbf51 | 502 | bool sctlr_b; |
48440620 PC |
503 | |
504 | if (is_a64(env)) { | |
505 | /* We might not be compiled with the A64 disassembler | |
506 | * because it needs a C++ compiler. Leave print_insn | |
507 | * unset in this case to use the caller default behaviour. | |
508 | */ | |
509 | #if defined(CONFIG_ARM_A64_DIS) | |
510 | info->print_insn = print_insn_arm_a64; | |
511 | #endif | |
110f6c70 | 512 | info->cap_arch = CS_ARCH_ARM64; |
15fa1a0a RH |
513 | info->cap_insn_unit = 4; |
514 | info->cap_insn_split = 4; | |
48440620 | 515 | } else { |
110f6c70 RH |
516 | int cap_mode; |
517 | if (env->thumb) { | |
518 | info->print_insn = print_insn_thumb1; | |
15fa1a0a RH |
519 | info->cap_insn_unit = 2; |
520 | info->cap_insn_split = 4; | |
110f6c70 RH |
521 | cap_mode = CS_MODE_THUMB; |
522 | } else { | |
523 | info->print_insn = print_insn_arm; | |
15fa1a0a RH |
524 | info->cap_insn_unit = 4; |
525 | info->cap_insn_split = 4; | |
110f6c70 RH |
526 | cap_mode = CS_MODE_ARM; |
527 | } | |
528 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
529 | cap_mode |= CS_MODE_V8; | |
530 | } | |
531 | if (arm_feature(env, ARM_FEATURE_M)) { | |
532 | cap_mode |= CS_MODE_MCLASS; | |
533 | } | |
534 | info->cap_arch = CS_ARCH_ARM; | |
535 | info->cap_mode = cap_mode; | |
48440620 | 536 | } |
7bcdbf51 RH |
537 | |
538 | sctlr_b = arm_sctlr_b(env); | |
539 | if (bswap_code(sctlr_b)) { | |
48440620 PC |
540 | #ifdef TARGET_WORDS_BIGENDIAN |
541 | info->endian = BFD_ENDIAN_LITTLE; | |
542 | #else | |
543 | info->endian = BFD_ENDIAN_BIG; | |
544 | #endif | |
545 | } | |
f7478a92 | 546 | info->flags &= ~INSN_ARM_BE32; |
7bcdbf51 RH |
547 | #ifndef CONFIG_USER_ONLY |
548 | if (sctlr_b) { | |
f7478a92 JB |
549 | info->flags |= INSN_ARM_BE32; |
550 | } | |
7bcdbf51 | 551 | #endif |
48440620 PC |
552 | } |
553 | ||
46de5913 IM |
554 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) |
555 | { | |
556 | uint32_t Aff1 = idx / clustersz; | |
557 | uint32_t Aff0 = idx % clustersz; | |
558 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | |
559 | } | |
560 | ||
777dc784 PM |
561 | static void arm_cpu_initfn(Object *obj) |
562 | { | |
c05efcb1 | 563 | CPUState *cs = CPU(obj); |
777dc784 PM |
564 | ARMCPU *cpu = ARM_CPU(obj); |
565 | ||
c05efcb1 | 566 | cs->env_ptr = &cpu->env; |
4b6a83fb PM |
567 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
568 | g_free, g_free); | |
79614b78 | 569 | |
b5c53d1b | 570 | QLIST_INIT(&cpu->pre_el_change_hooks); |
08267487 AL |
571 | QLIST_INIT(&cpu->el_change_hooks); |
572 | ||
7c1840b6 PM |
573 | #ifndef CONFIG_USER_ONLY |
574 | /* Our inbound IRQ and FIQ lines */ | |
575 | if (kvm_enabled()) { | |
136e67e9 EI |
576 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
577 | * the same interface as non-KVM CPUs. | |
578 | */ | |
579 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 580 | } else { |
136e67e9 | 581 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 582 | } |
55d284af | 583 | |
bc72ad67 | 584 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 585 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 586 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 587 | arm_gt_vtimer_cb, cpu); |
b0e66d95 EI |
588 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
589 | arm_gt_htimer_cb, cpu); | |
b4d3978c PM |
590 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
591 | arm_gt_stimer_cb, cpu); | |
55d284af PM |
592 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
593 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
aa1b3111 PM |
594 | |
595 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, | |
596 | "gicv3-maintenance-interrupt", 1); | |
07f48730 AJ |
597 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, |
598 | "pmu-interrupt", 1); | |
7c1840b6 PM |
599 | #endif |
600 | ||
54d3e3f5 PM |
601 | /* DTB consumers generally don't in fact care what the 'compatible' |
602 | * string is, so always provide some string and trust that a hypothetical | |
603 | * picky DTB consumer will also provide a helpful error message. | |
604 | */ | |
605 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 606 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 607 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 608 | |
98128601 RH |
609 | if (tcg_enabled()) { |
610 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
79614b78 | 611 | } |
4b6a83fb PM |
612 | } |
613 | ||
07a5b0d2 | 614 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 615 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 616 | |
68e0a40a AP |
617 | static Property arm_cpu_reset_hivecs_property = |
618 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
619 | ||
3933443e PM |
620 | static Property arm_cpu_rvbar_property = |
621 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
622 | ||
c25bd18a PM |
623 | static Property arm_cpu_has_el2_property = |
624 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | |
625 | ||
51942aee GB |
626 | static Property arm_cpu_has_el3_property = |
627 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
628 | ||
3a062d57 JB |
629 | static Property arm_cpu_cfgend_property = |
630 | DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | |
631 | ||
929e754d WH |
632 | /* use property name "pmu" to match other archs and virt tools */ |
633 | static Property arm_cpu_has_pmu_property = | |
634 | DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); | |
635 | ||
8f325f56 PC |
636 | static Property arm_cpu_has_mpu_property = |
637 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
638 | ||
8d92e26b PM |
639 | /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, |
640 | * because the CPU initfn will have already set cpu->pmsav7_dregion to | |
641 | * the right value for that particular CPU type, and we don't want | |
642 | * to override that with an incorrect constant value. | |
643 | */ | |
3281af81 | 644 | static Property arm_cpu_pmsav7_dregion_property = |
8d92e26b PM |
645 | DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, |
646 | pmsav7_dregion, | |
647 | qdev_prop_uint32, uint32_t); | |
3281af81 | 648 | |
38e2a77c PM |
649 | /* M profile: initial value of the Secure VTOR */ |
650 | static Property arm_cpu_initsvtor_property = | |
651 | DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); | |
652 | ||
07a5b0d2 PC |
653 | static void arm_cpu_post_init(Object *obj) |
654 | { | |
655 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 656 | |
790a1150 PM |
657 | /* M profile implies PMSA. We have to do this here rather than |
658 | * in realize with the other feature-implication checks because | |
659 | * we look at the PMSA bit to see if we should add some properties. | |
660 | */ | |
661 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
662 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | |
663 | } | |
664 | ||
f318cec6 PM |
665 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
666 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 667 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 668 | &error_abort); |
07a5b0d2 | 669 | } |
68e0a40a AP |
670 | |
671 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
672 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 673 | &error_abort); |
68e0a40a | 674 | } |
3933443e PM |
675 | |
676 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
677 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
678 | &error_abort); | |
679 | } | |
51942aee GB |
680 | |
681 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
682 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
683 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
684 | */ | |
685 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, | |
686 | &error_abort); | |
9e273ef2 PM |
687 | |
688 | #ifndef CONFIG_USER_ONLY | |
689 | object_property_add_link(obj, "secure-memory", | |
690 | TYPE_MEMORY_REGION, | |
691 | (Object **)&cpu->secure_memory, | |
692 | qdev_prop_allow_set_link_before_realize, | |
693 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
694 | &error_abort); | |
695 | #endif | |
51942aee | 696 | } |
8f325f56 | 697 | |
c25bd18a PM |
698 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { |
699 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, | |
700 | &error_abort); | |
701 | } | |
702 | ||
929e754d WH |
703 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { |
704 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, | |
705 | &error_abort); | |
706 | } | |
707 | ||
452a0955 | 708 | if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { |
8f325f56 PC |
709 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, |
710 | &error_abort); | |
3281af81 PC |
711 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
712 | qdev_property_add_static(DEVICE(obj), | |
713 | &arm_cpu_pmsav7_dregion_property, | |
714 | &error_abort); | |
715 | } | |
8f325f56 PC |
716 | } |
717 | ||
181962fd PM |
718 | if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { |
719 | object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | |
720 | qdev_prop_allow_set_link_before_realize, | |
721 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
722 | &error_abort); | |
38e2a77c PM |
723 | qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, |
724 | &error_abort); | |
181962fd PM |
725 | } |
726 | ||
3a062d57 JB |
727 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, |
728 | &error_abort); | |
07a5b0d2 PC |
729 | } |
730 | ||
4b6a83fb PM |
731 | static void arm_cpu_finalizefn(Object *obj) |
732 | { | |
733 | ARMCPU *cpu = ARM_CPU(obj); | |
08267487 AL |
734 | ARMELChangeHook *hook, *next; |
735 | ||
4b6a83fb | 736 | g_hash_table_destroy(cpu->cp_regs); |
08267487 | 737 | |
b5c53d1b AL |
738 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
739 | QLIST_REMOVE(hook, node); | |
740 | g_free(hook); | |
741 | } | |
08267487 AL |
742 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
743 | QLIST_REMOVE(hook, node); | |
744 | g_free(hook); | |
745 | } | |
777dc784 PM |
746 | } |
747 | ||
14969266 | 748 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 749 | { |
14a10fc3 | 750 | CPUState *cs = CPU(dev); |
14969266 AF |
751 | ARMCPU *cpu = ARM_CPU(dev); |
752 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 753 | CPUARMState *env = &cpu->env; |
e97da98f | 754 | int pagebits; |
ce5b1bbf LV |
755 | Error *local_err = NULL; |
756 | ||
c4487d76 PM |
757 | /* If we needed to query the host kernel for the CPU features |
758 | * then it's possible that might have failed in the initfn, but | |
759 | * this is the first point where we can report it. | |
760 | */ | |
761 | if (cpu->host_cpu_probe_failed) { | |
762 | if (!kvm_enabled()) { | |
763 | error_setg(errp, "The 'host' CPU type can only be used with KVM"); | |
764 | } else { | |
765 | error_setg(errp, "Failed to retrieve host CPU features"); | |
766 | } | |
767 | return; | |
768 | } | |
769 | ||
ce5b1bbf LV |
770 | cpu_exec_realizefn(cs, &local_err); |
771 | if (local_err != NULL) { | |
772 | error_propagate(errp, local_err); | |
773 | return; | |
774 | } | |
14969266 | 775 | |
581be094 | 776 | /* Some features automatically imply others: */ |
81e69fb0 MR |
777 | if (arm_feature(env, ARM_FEATURE_V8)) { |
778 | set_feature(env, ARM_FEATURE_V7); | |
779 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
780 | set_feature(env, ARM_FEATURE_LPAE); | |
781 | } | |
581be094 PM |
782 | if (arm_feature(env, ARM_FEATURE_V7)) { |
783 | set_feature(env, ARM_FEATURE_VAPA); | |
784 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 785 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
786 | if (!arm_feature(env, ARM_FEATURE_M)) { |
787 | set_feature(env, ARM_FEATURE_V6K); | |
788 | } else { | |
789 | set_feature(env, ARM_FEATURE_V6); | |
790 | } | |
91db4642 CLG |
791 | |
792 | /* Always define VBAR for V7 CPUs even if it doesn't exist in | |
793 | * non-EL3 configs. This is needed by some legacy boards. | |
794 | */ | |
795 | set_feature(env, ARM_FEATURE_VBAR); | |
581be094 PM |
796 | } |
797 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
798 | set_feature(env, ARM_FEATURE_V6); | |
799 | set_feature(env, ARM_FEATURE_MVFR); | |
800 | } | |
801 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
802 | set_feature(env, ARM_FEATURE_V5); | |
c99a55d3 | 803 | set_feature(env, ARM_FEATURE_JAZELLE); |
581be094 PM |
804 | if (!arm_feature(env, ARM_FEATURE_M)) { |
805 | set_feature(env, ARM_FEATURE_AUXCR); | |
806 | } | |
807 | } | |
808 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
809 | set_feature(env, ARM_FEATURE_V4T); | |
810 | } | |
811 | if (arm_feature(env, ARM_FEATURE_M)) { | |
812 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
813 | } | |
814 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
815 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
816 | } | |
817 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
818 | set_feature(env, ARM_FEATURE_VFP3); | |
da5141fc | 819 | set_feature(env, ARM_FEATURE_VFP_FP16); |
581be094 PM |
820 | } |
821 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
822 | set_feature(env, ARM_FEATURE_VFP); | |
823 | } | |
de9b05b8 | 824 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 825 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
826 | set_feature(env, ARM_FEATURE_PXN); |
827 | } | |
f318cec6 PM |
828 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
829 | set_feature(env, ARM_FEATURE_CBAR); | |
830 | } | |
62b44f05 AR |
831 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
832 | !arm_feature(env, ARM_FEATURE_M)) { | |
833 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
834 | } | |
2ceb98c0 | 835 | |
e97da98f PM |
836 | if (arm_feature(env, ARM_FEATURE_V7) && |
837 | !arm_feature(env, ARM_FEATURE_M) && | |
452a0955 | 838 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
e97da98f PM |
839 | /* v7VMSA drops support for the old ARMv5 tiny pages, so we |
840 | * can use 4K pages. | |
841 | */ | |
842 | pagebits = 12; | |
843 | } else { | |
844 | /* For CPUs which might have tiny 1K pages, or which have an | |
845 | * MPU and might have small region sizes, stick with 1K pages. | |
846 | */ | |
847 | pagebits = 10; | |
848 | } | |
849 | if (!set_preferred_target_page_bits(pagebits)) { | |
850 | /* This can only ever happen for hotplugging a CPU, or if | |
851 | * the board code incorrectly creates a CPU which it has | |
852 | * promised via minimum_page_size that it will not. | |
853 | */ | |
854 | error_setg(errp, "This CPU requires a smaller page size than the " | |
855 | "system is using"); | |
856 | return; | |
857 | } | |
858 | ||
ce5b1bbf LV |
859 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
860 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
861 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
862 | * so these bits always RAZ. | |
863 | */ | |
864 | if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { | |
46de5913 IM |
865 | cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, |
866 | ARM_DEFAULT_CPUS_PER_CLUSTER); | |
ce5b1bbf LV |
867 | } |
868 | ||
68e0a40a AP |
869 | if (cpu->reset_hivecs) { |
870 | cpu->reset_sctlr |= (1 << 13); | |
871 | } | |
872 | ||
3a062d57 JB |
873 | if (cpu->cfgend) { |
874 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | |
875 | cpu->reset_sctlr |= SCTLR_EE; | |
876 | } else { | |
877 | cpu->reset_sctlr |= SCTLR_B; | |
878 | } | |
879 | } | |
880 | ||
51942aee GB |
881 | if (!cpu->has_el3) { |
882 | /* If the has_el3 CPU property is disabled then we need to disable the | |
883 | * feature. | |
884 | */ | |
885 | unset_feature(env, ARM_FEATURE_EL3); | |
886 | ||
887 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 888 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
889 | */ |
890 | cpu->id_pfr1 &= ~0xf0; | |
3d5c84ff | 891 | cpu->id_aa64pfr0 &= ~0xf000; |
51942aee GB |
892 | } |
893 | ||
c25bd18a PM |
894 | if (!cpu->has_el2) { |
895 | unset_feature(env, ARM_FEATURE_EL2); | |
896 | } | |
897 | ||
d6f02ce3 | 898 | if (!cpu->has_pmu) { |
929e754d | 899 | unset_feature(env, ARM_FEATURE_PMU); |
2b3ffa92 | 900 | cpu->id_aa64dfr0 &= ~0xf00; |
929e754d WH |
901 | } |
902 | ||
3c2f7bb3 PM |
903 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
904 | /* Disable the hypervisor feature bits in the processor feature | |
905 | * registers if we don't have EL2. These are id_pfr1[15:12] and | |
906 | * id_aa64pfr0_el1[11:8]. | |
907 | */ | |
908 | cpu->id_aa64pfr0 &= ~0xf00; | |
909 | cpu->id_pfr1 &= ~0xf000; | |
910 | } | |
911 | ||
f50cd314 PM |
912 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
913 | * to false or by setting pmsav7-dregion to 0. | |
914 | */ | |
8f325f56 | 915 | if (!cpu->has_mpu) { |
f50cd314 PM |
916 | cpu->pmsav7_dregion = 0; |
917 | } | |
918 | if (cpu->pmsav7_dregion == 0) { | |
919 | cpu->has_mpu = false; | |
8f325f56 PC |
920 | } |
921 | ||
452a0955 | 922 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
3281af81 PC |
923 | arm_feature(env, ARM_FEATURE_V7)) { |
924 | uint32_t nr = cpu->pmsav7_dregion; | |
925 | ||
926 | if (nr > 0xff) { | |
9af9e0fe | 927 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
928 | return; |
929 | } | |
6cb0b013 PC |
930 | |
931 | if (nr) { | |
0e1a46bb PM |
932 | if (arm_feature(env, ARM_FEATURE_V8)) { |
933 | /* PMSAv8 */ | |
62c58ee0 PM |
934 | env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); |
935 | env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | |
936 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
937 | env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | |
938 | env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | |
939 | } | |
0e1a46bb PM |
940 | } else { |
941 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
942 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
943 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
944 | } | |
6cb0b013 | 945 | } |
3281af81 PC |
946 | } |
947 | ||
9901c576 PM |
948 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
949 | uint32_t nr = cpu->sau_sregion; | |
950 | ||
951 | if (nr > 0xff) { | |
952 | error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); | |
953 | return; | |
954 | } | |
955 | ||
956 | if (nr) { | |
957 | env->sau.rbar = g_new0(uint32_t, nr); | |
958 | env->sau.rlar = g_new0(uint32_t, nr); | |
959 | } | |
960 | } | |
961 | ||
91db4642 CLG |
962 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
963 | set_feature(env, ARM_FEATURE_VBAR); | |
964 | } | |
965 | ||
2ceb98c0 | 966 | register_cp_regs_for_features(cpu); |
14969266 AF |
967 | arm_cpu_register_gdb_regs_for_features(cpu); |
968 | ||
721fae12 PM |
969 | init_cpreg_list(cpu); |
970 | ||
9e273ef2 | 971 | #ifndef CONFIG_USER_ONLY |
1d2091bc | 972 | if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1d2091bc PM |
973 | cs->num_ases = 2; |
974 | ||
9e273ef2 PM |
975 | if (!cpu->secure_memory) { |
976 | cpu->secure_memory = cs->memory; | |
977 | } | |
80ceb07a PX |
978 | cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", |
979 | cpu->secure_memory); | |
1d2091bc PM |
980 | } else { |
981 | cs->num_ases = 1; | |
9e273ef2 | 982 | } |
80ceb07a | 983 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); |
f9a69711 AF |
984 | |
985 | /* No core_count specified, default to smp_cpus. */ | |
986 | if (cpu->core_count == -1) { | |
987 | cpu->core_count = smp_cpus; | |
988 | } | |
9e273ef2 PM |
989 | #endif |
990 | ||
14a10fc3 | 991 | qemu_init_vcpu(cs); |
00d0f7cb | 992 | cpu_reset(cs); |
14969266 AF |
993 | |
994 | acc->parent_realize(dev, errp); | |
581be094 PM |
995 | } |
996 | ||
5900d6b2 AF |
997 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
998 | { | |
999 | ObjectClass *oc; | |
51492fd1 | 1000 | char *typename; |
fb8d6c24 | 1001 | char **cpuname; |
a0032cc5 | 1002 | const char *cpunamestr; |
5900d6b2 | 1003 | |
fb8d6c24 | 1004 | cpuname = g_strsplit(cpu_model, ",", 1); |
a0032cc5 PM |
1005 | cpunamestr = cpuname[0]; |
1006 | #ifdef CONFIG_USER_ONLY | |
1007 | /* For backwards compatibility usermode emulation allows "-cpu any", | |
1008 | * which has the same semantics as "-cpu max". | |
1009 | */ | |
1010 | if (!strcmp(cpunamestr, "any")) { | |
1011 | cpunamestr = "max"; | |
1012 | } | |
1013 | #endif | |
1014 | typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); | |
51492fd1 | 1015 | oc = object_class_by_name(typename); |
fb8d6c24 | 1016 | g_strfreev(cpuname); |
51492fd1 | 1017 | g_free(typename); |
245fb54d AF |
1018 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
1019 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
1020 | return NULL; |
1021 | } | |
1022 | return oc; | |
1023 | } | |
1024 | ||
15ee776b PM |
1025 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
1026 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
1027 | ||
777dc784 PM |
1028 | static void arm926_initfn(Object *obj) |
1029 | { | |
1030 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1031 | |
1032 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
1033 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1034 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1035 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1036 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
c99a55d3 | 1037 | set_feature(&cpu->env, ARM_FEATURE_JAZELLE); |
b2d06f96 | 1038 | cpu->midr = 0x41069265; |
325b3cef | 1039 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 1040 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1041 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
1042 | } |
1043 | ||
1044 | static void arm946_initfn(Object *obj) | |
1045 | { | |
1046 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1047 | |
1048 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 | 1049 | set_feature(&cpu->env, ARM_FEATURE_V5); |
452a0955 | 1050 | set_feature(&cpu->env, ARM_FEATURE_PMSA); |
c4804214 | 1051 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1052 | cpu->midr = 0x41059461; |
64e1671f | 1053 | cpu->ctr = 0x0f004006; |
0ca7e01c | 1054 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1055 | } |
1056 | ||
1057 | static void arm1026_initfn(Object *obj) | |
1058 | { | |
1059 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1060 | |
1061 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
1062 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1063 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1064 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
1065 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1066 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
c99a55d3 | 1067 | set_feature(&cpu->env, ARM_FEATURE_JAZELLE); |
b2d06f96 | 1068 | cpu->midr = 0x4106a262; |
325b3cef | 1069 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 1070 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1071 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 1072 | cpu->reset_auxcr = 1; |
06d76f31 PM |
1073 | { |
1074 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
1075 | ARMCPRegInfo ifar = { | |
1076 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1077 | .access = PL1_RW, | |
b848ce2b | 1078 | .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), |
06d76f31 PM |
1079 | .resetvalue = 0 |
1080 | }; | |
1081 | define_one_arm_cp_reg(cpu, &ifar); | |
1082 | } | |
777dc784 PM |
1083 | } |
1084 | ||
1085 | static void arm1136_r2_initfn(Object *obj) | |
1086 | { | |
1087 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
1088 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
1089 | * older core than plain "arm1136". In particular this does not | |
1090 | * have the v6K features. | |
1091 | * These ID register values are correct for 1136 but may be wrong | |
1092 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
1093 | * of the ID registers). | |
1094 | */ | |
54d3e3f5 PM |
1095 | |
1096 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
1097 | set_feature(&cpu->env, ARM_FEATURE_V6); |
1098 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1099 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1100 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1101 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 1102 | cpu->midr = 0x4107b362; |
325b3cef | 1103 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
1104 | cpu->mvfr0 = 0x11111111; |
1105 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 1106 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1107 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1108 | cpu->id_pfr0 = 0x111; |
1109 | cpu->id_pfr1 = 0x1; | |
1110 | cpu->id_dfr0 = 0x2; | |
1111 | cpu->id_afr0 = 0x3; | |
1112 | cpu->id_mmfr0 = 0x01130003; | |
1113 | cpu->id_mmfr1 = 0x10030302; | |
1114 | cpu->id_mmfr2 = 0x01222110; | |
1115 | cpu->id_isar0 = 0x00140011; | |
1116 | cpu->id_isar1 = 0x12002111; | |
1117 | cpu->id_isar2 = 0x11231111; | |
1118 | cpu->id_isar3 = 0x01102131; | |
1119 | cpu->id_isar4 = 0x141; | |
2771db27 | 1120 | cpu->reset_auxcr = 7; |
777dc784 PM |
1121 | } |
1122 | ||
1123 | static void arm1136_initfn(Object *obj) | |
1124 | { | |
1125 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1126 | |
1127 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
1128 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1129 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
1130 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1131 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1132 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1133 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 1134 | cpu->midr = 0x4117b363; |
325b3cef | 1135 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
1136 | cpu->mvfr0 = 0x11111111; |
1137 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 1138 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1139 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1140 | cpu->id_pfr0 = 0x111; |
1141 | cpu->id_pfr1 = 0x1; | |
1142 | cpu->id_dfr0 = 0x2; | |
1143 | cpu->id_afr0 = 0x3; | |
1144 | cpu->id_mmfr0 = 0x01130003; | |
1145 | cpu->id_mmfr1 = 0x10030302; | |
1146 | cpu->id_mmfr2 = 0x01222110; | |
1147 | cpu->id_isar0 = 0x00140011; | |
1148 | cpu->id_isar1 = 0x12002111; | |
1149 | cpu->id_isar2 = 0x11231111; | |
1150 | cpu->id_isar3 = 0x01102131; | |
1151 | cpu->id_isar4 = 0x141; | |
2771db27 | 1152 | cpu->reset_auxcr = 7; |
777dc784 PM |
1153 | } |
1154 | ||
1155 | static void arm1176_initfn(Object *obj) | |
1156 | { | |
1157 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1158 | |
1159 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
1160 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1161 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1162 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
1163 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1164 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1165 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
c0ccb02d | 1166 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1167 | cpu->midr = 0x410fb767; |
325b3cef | 1168 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
1169 | cpu->mvfr0 = 0x11111111; |
1170 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 1171 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1172 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1173 | cpu->id_pfr0 = 0x111; |
1174 | cpu->id_pfr1 = 0x11; | |
1175 | cpu->id_dfr0 = 0x33; | |
1176 | cpu->id_afr0 = 0; | |
1177 | cpu->id_mmfr0 = 0x01130003; | |
1178 | cpu->id_mmfr1 = 0x10030302; | |
1179 | cpu->id_mmfr2 = 0x01222100; | |
1180 | cpu->id_isar0 = 0x0140011; | |
1181 | cpu->id_isar1 = 0x12002111; | |
1182 | cpu->id_isar2 = 0x11231121; | |
1183 | cpu->id_isar3 = 0x01102131; | |
1184 | cpu->id_isar4 = 0x01141; | |
2771db27 | 1185 | cpu->reset_auxcr = 7; |
777dc784 PM |
1186 | } |
1187 | ||
1188 | static void arm11mpcore_initfn(Object *obj) | |
1189 | { | |
1190 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1191 | |
1192 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
1193 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1194 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1195 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 1196 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 1197 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1198 | cpu->midr = 0x410fb022; |
325b3cef | 1199 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
1200 | cpu->mvfr0 = 0x11111111; |
1201 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 1202 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
1203 | cpu->id_pfr0 = 0x111; |
1204 | cpu->id_pfr1 = 0x1; | |
1205 | cpu->id_dfr0 = 0; | |
1206 | cpu->id_afr0 = 0x2; | |
1207 | cpu->id_mmfr0 = 0x01100103; | |
1208 | cpu->id_mmfr1 = 0x10020302; | |
1209 | cpu->id_mmfr2 = 0x01222000; | |
1210 | cpu->id_isar0 = 0x00100011; | |
1211 | cpu->id_isar1 = 0x12002111; | |
1212 | cpu->id_isar2 = 0x11221011; | |
1213 | cpu->id_isar3 = 0x01102131; | |
1214 | cpu->id_isar4 = 0x141; | |
2771db27 | 1215 | cpu->reset_auxcr = 1; |
777dc784 PM |
1216 | } |
1217 | ||
1218 | static void cortex_m3_initfn(Object *obj) | |
1219 | { | |
1220 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1221 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1222 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 1223 | cpu->midr = 0x410fc231; |
8d92e26b | 1224 | cpu->pmsav7_dregion = 8; |
5a53e2c1 PM |
1225 | cpu->id_pfr0 = 0x00000030; |
1226 | cpu->id_pfr1 = 0x00000200; | |
1227 | cpu->id_dfr0 = 0x00100000; | |
1228 | cpu->id_afr0 = 0x00000000; | |
1229 | cpu->id_mmfr0 = 0x00000030; | |
1230 | cpu->id_mmfr1 = 0x00000000; | |
1231 | cpu->id_mmfr2 = 0x00000000; | |
1232 | cpu->id_mmfr3 = 0x00000000; | |
1233 | cpu->id_isar0 = 0x01141110; | |
1234 | cpu->id_isar1 = 0x02111000; | |
1235 | cpu->id_isar2 = 0x21112231; | |
1236 | cpu->id_isar3 = 0x01111110; | |
1237 | cpu->id_isar4 = 0x01310102; | |
1238 | cpu->id_isar5 = 0x00000000; | |
777dc784 PM |
1239 | } |
1240 | ||
ba890a9b AR |
1241 | static void cortex_m4_initfn(Object *obj) |
1242 | { | |
1243 | ARMCPU *cpu = ARM_CPU(obj); | |
1244 | ||
1245 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
1246 | set_feature(&cpu->env, ARM_FEATURE_M); | |
1247 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | |
1248 | cpu->midr = 0x410fc240; /* r0p0 */ | |
8d92e26b | 1249 | cpu->pmsav7_dregion = 8; |
5a53e2c1 PM |
1250 | cpu->id_pfr0 = 0x00000030; |
1251 | cpu->id_pfr1 = 0x00000200; | |
1252 | cpu->id_dfr0 = 0x00100000; | |
1253 | cpu->id_afr0 = 0x00000000; | |
1254 | cpu->id_mmfr0 = 0x00000030; | |
1255 | cpu->id_mmfr1 = 0x00000000; | |
1256 | cpu->id_mmfr2 = 0x00000000; | |
1257 | cpu->id_mmfr3 = 0x00000000; | |
1258 | cpu->id_isar0 = 0x01141110; | |
1259 | cpu->id_isar1 = 0x02111000; | |
1260 | cpu->id_isar2 = 0x21112231; | |
1261 | cpu->id_isar3 = 0x01111110; | |
1262 | cpu->id_isar4 = 0x01310102; | |
1263 | cpu->id_isar5 = 0x00000000; | |
ba890a9b | 1264 | } |
9901c576 | 1265 | |
c7b26382 PM |
1266 | static void cortex_m33_initfn(Object *obj) |
1267 | { | |
1268 | ARMCPU *cpu = ARM_CPU(obj); | |
1269 | ||
1270 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
1271 | set_feature(&cpu->env, ARM_FEATURE_M); | |
1272 | set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | |
1273 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | |
1274 | cpu->midr = 0x410fd213; /* r0p3 */ | |
1275 | cpu->pmsav7_dregion = 16; | |
1276 | cpu->sau_sregion = 8; | |
1277 | cpu->id_pfr0 = 0x00000030; | |
1278 | cpu->id_pfr1 = 0x00000210; | |
1279 | cpu->id_dfr0 = 0x00200000; | |
1280 | cpu->id_afr0 = 0x00000000; | |
1281 | cpu->id_mmfr0 = 0x00101F40; | |
1282 | cpu->id_mmfr1 = 0x00000000; | |
1283 | cpu->id_mmfr2 = 0x01000000; | |
1284 | cpu->id_mmfr3 = 0x00000000; | |
1285 | cpu->id_isar0 = 0x01101110; | |
1286 | cpu->id_isar1 = 0x02212000; | |
1287 | cpu->id_isar2 = 0x20232232; | |
1288 | cpu->id_isar3 = 0x01111131; | |
1289 | cpu->id_isar4 = 0x01310132; | |
1290 | cpu->id_isar5 = 0x00000000; | |
1291 | cpu->clidr = 0x00000000; | |
1292 | cpu->ctr = 0x8000c000; | |
1293 | } | |
1294 | ||
e6f010cc AF |
1295 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
1296 | { | |
e6f010cc AF |
1297 | CPUClass *cc = CPU_CLASS(oc); |
1298 | ||
b5c633c5 | 1299 | #ifndef CONFIG_USER_ONLY |
e6f010cc AF |
1300 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
1301 | #endif | |
b5c633c5 PM |
1302 | |
1303 | cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; | |
e6f010cc AF |
1304 | } |
1305 | ||
d6a6b13e PC |
1306 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
1307 | /* Dummy the TCM region regs for the moment */ | |
1308 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1309 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
1310 | { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1311 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
95e9a242 LM |
1312 | { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, |
1313 | .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, | |
d6a6b13e PC |
1314 | REGINFO_SENTINEL |
1315 | }; | |
1316 | ||
1317 | static void cortex_r5_initfn(Object *obj) | |
1318 | { | |
1319 | ARMCPU *cpu = ARM_CPU(obj); | |
1320 | ||
1321 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
1322 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); | |
1323 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
1324 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
452a0955 | 1325 | set_feature(&cpu->env, ARM_FEATURE_PMSA); |
d6a6b13e PC |
1326 | cpu->midr = 0x411fc153; /* r1p3 */ |
1327 | cpu->id_pfr0 = 0x0131; | |
1328 | cpu->id_pfr1 = 0x001; | |
1329 | cpu->id_dfr0 = 0x010400; | |
1330 | cpu->id_afr0 = 0x0; | |
1331 | cpu->id_mmfr0 = 0x0210030; | |
1332 | cpu->id_mmfr1 = 0x00000000; | |
1333 | cpu->id_mmfr2 = 0x01200000; | |
1334 | cpu->id_mmfr3 = 0x0211; | |
1335 | cpu->id_isar0 = 0x2101111; | |
1336 | cpu->id_isar1 = 0x13112111; | |
1337 | cpu->id_isar2 = 0x21232141; | |
1338 | cpu->id_isar3 = 0x01112131; | |
1339 | cpu->id_isar4 = 0x0010142; | |
1340 | cpu->id_isar5 = 0x0; | |
1341 | cpu->mp_is_up = true; | |
8d92e26b | 1342 | cpu->pmsav7_dregion = 16; |
d6a6b13e PC |
1343 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); |
1344 | } | |
1345 | ||
34f90529 PM |
1346 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
1347 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
1348 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1349 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1350 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1351 | REGINFO_SENTINEL | |
1352 | }; | |
1353 | ||
777dc784 PM |
1354 | static void cortex_a8_initfn(Object *obj) |
1355 | { | |
1356 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1357 | |
1358 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
1359 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1360 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1361 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1362 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 1363 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 1364 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1365 | cpu->midr = 0x410fc080; |
325b3cef | 1366 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 | 1367 | cpu->mvfr0 = 0x11110222; |
0f194473 | 1368 | cpu->mvfr1 = 0x00011111; |
64e1671f | 1369 | cpu->ctr = 0x82048004; |
0ca7e01c | 1370 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1371 | cpu->id_pfr0 = 0x1031; |
1372 | cpu->id_pfr1 = 0x11; | |
1373 | cpu->id_dfr0 = 0x400; | |
1374 | cpu->id_afr0 = 0; | |
1375 | cpu->id_mmfr0 = 0x31100003; | |
1376 | cpu->id_mmfr1 = 0x20000000; | |
1377 | cpu->id_mmfr2 = 0x01202000; | |
1378 | cpu->id_mmfr3 = 0x11; | |
1379 | cpu->id_isar0 = 0x00101111; | |
1380 | cpu->id_isar1 = 0x12112111; | |
1381 | cpu->id_isar2 = 0x21232031; | |
1382 | cpu->id_isar3 = 0x11112131; | |
1383 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 1384 | cpu->dbgdidr = 0x15141000; |
85df3786 PM |
1385 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
1386 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
1387 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
1388 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 1389 | cpu->reset_auxcr = 2; |
34f90529 | 1390 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
1391 | } |
1392 | ||
1047b9d7 PM |
1393 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
1394 | /* power_control should be set to maximum latency. Again, | |
1395 | * default to 0 and set by private hook | |
1396 | */ | |
1397 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1398 | .access = PL1_RW, .resetvalue = 0, | |
1399 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
1400 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1401 | .access = PL1_RW, .resetvalue = 0, | |
1402 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
1403 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1404 | .access = PL1_RW, .resetvalue = 0, | |
1405 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
1406 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1407 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1408 | /* TLB lockdown control */ | |
1409 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
1410 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1411 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
1412 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1413 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
1414 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1415 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
1416 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1417 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
1418 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1419 | REGINFO_SENTINEL | |
1420 | }; | |
1421 | ||
777dc784 PM |
1422 | static void cortex_a9_initfn(Object *obj) |
1423 | { | |
1424 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1425 | |
1426 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
1427 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1428 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1429 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
1430 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1431 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 1432 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
1433 | /* Note that A9 supports the MP extensions even for |
1434 | * A9UP and single-core A9MP (which are both different | |
1435 | * and valid configurations; we don't model A9UP). | |
1436 | */ | |
1437 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 1438 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 1439 | cpu->midr = 0x410fc090; |
325b3cef | 1440 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
1441 | cpu->mvfr0 = 0x11110222; |
1442 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 1443 | cpu->ctr = 0x80038003; |
0ca7e01c | 1444 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1445 | cpu->id_pfr0 = 0x1031; |
1446 | cpu->id_pfr1 = 0x11; | |
1447 | cpu->id_dfr0 = 0x000; | |
1448 | cpu->id_afr0 = 0; | |
1449 | cpu->id_mmfr0 = 0x00100103; | |
1450 | cpu->id_mmfr1 = 0x20000000; | |
1451 | cpu->id_mmfr2 = 0x01230000; | |
1452 | cpu->id_mmfr3 = 0x00002111; | |
1453 | cpu->id_isar0 = 0x00101111; | |
1454 | cpu->id_isar1 = 0x13112111; | |
1455 | cpu->id_isar2 = 0x21232041; | |
1456 | cpu->id_isar3 = 0x11112131; | |
1457 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 1458 | cpu->dbgdidr = 0x35141000; |
85df3786 | 1459 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
1460 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
1461 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 1462 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
1463 | } |
1464 | ||
34f90529 | 1465 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 1466 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
1467 | { |
1468 | /* Linux wants the number of processors from here. | |
1469 | * Might as well set the interrupt-controller bit too. | |
1470 | */ | |
c4241c7d | 1471 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
1472 | } |
1473 | #endif | |
1474 | ||
1475 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
1476 | #ifndef CONFIG_USER_ONLY | |
1477 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1478 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
1479 | .writefn = arm_cp_write_ignore, }, | |
1480 | #endif | |
1481 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
1482 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1483 | REGINFO_SENTINEL | |
1484 | }; | |
1485 | ||
dcf578ed AY |
1486 | static void cortex_a7_initfn(Object *obj) |
1487 | { | |
1488 | ARMCPU *cpu = ARM_CPU(obj); | |
1489 | ||
1490 | cpu->dtb_compatible = "arm,cortex-a7"; | |
1491 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
1492 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
1493 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1494 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
1495 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
1496 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
1497 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
1498 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
1499 | set_feature(&cpu->env, ARM_FEATURE_LPAE); | |
1500 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
1501 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; | |
1502 | cpu->midr = 0x410fc075; | |
1503 | cpu->reset_fpsid = 0x41023075; | |
1504 | cpu->mvfr0 = 0x10110222; | |
1505 | cpu->mvfr1 = 0x11111111; | |
1506 | cpu->ctr = 0x84448003; | |
1507 | cpu->reset_sctlr = 0x00c50078; | |
1508 | cpu->id_pfr0 = 0x00001131; | |
1509 | cpu->id_pfr1 = 0x00011011; | |
1510 | cpu->id_dfr0 = 0x02010555; | |
1511 | cpu->pmceid0 = 0x00000000; | |
1512 | cpu->pmceid1 = 0x00000000; | |
1513 | cpu->id_afr0 = 0x00000000; | |
1514 | cpu->id_mmfr0 = 0x10101105; | |
1515 | cpu->id_mmfr1 = 0x40000000; | |
1516 | cpu->id_mmfr2 = 0x01240000; | |
1517 | cpu->id_mmfr3 = 0x02102211; | |
1518 | cpu->id_isar0 = 0x01101110; | |
1519 | cpu->id_isar1 = 0x13112111; | |
1520 | cpu->id_isar2 = 0x21232041; | |
1521 | cpu->id_isar3 = 0x11112131; | |
1522 | cpu->id_isar4 = 0x10011142; | |
1523 | cpu->dbgdidr = 0x3515f005; | |
1524 | cpu->clidr = 0x0a200023; | |
1525 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1526 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1527 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
1528 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ | |
1529 | } | |
1530 | ||
777dc784 PM |
1531 | static void cortex_a15_initfn(Object *obj) |
1532 | { | |
1533 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1534 | |
1535 | cpu->dtb_compatible = "arm,cortex-a15"; | |
581be094 PM |
1536 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1537 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
581be094 PM |
1538 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1539 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
1540 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 1541 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 1542 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 1543 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
de9b05b8 | 1544 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
c0ccb02d | 1545 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
3541addc | 1546 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 1547 | cpu->midr = 0x412fc0f1; |
325b3cef | 1548 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
1549 | cpu->mvfr0 = 0x10110222; |
1550 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 1551 | cpu->ctr = 0x8444c004; |
0ca7e01c | 1552 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1553 | cpu->id_pfr0 = 0x00001131; |
1554 | cpu->id_pfr1 = 0x00011011; | |
1555 | cpu->id_dfr0 = 0x02010555; | |
4054bfa9 AF |
1556 | cpu->pmceid0 = 0x0000000; |
1557 | cpu->pmceid1 = 0x00000000; | |
2e4d7e3e PM |
1558 | cpu->id_afr0 = 0x00000000; |
1559 | cpu->id_mmfr0 = 0x10201105; | |
1560 | cpu->id_mmfr1 = 0x20000000; | |
1561 | cpu->id_mmfr2 = 0x01240000; | |
1562 | cpu->id_mmfr3 = 0x02102211; | |
1563 | cpu->id_isar0 = 0x02101110; | |
1564 | cpu->id_isar1 = 0x13112111; | |
1565 | cpu->id_isar2 = 0x21232041; | |
1566 | cpu->id_isar3 = 0x11112131; | |
1567 | cpu->id_isar4 = 0x10011142; | |
48eb3ae6 | 1568 | cpu->dbgdidr = 0x3515f021; |
85df3786 PM |
1569 | cpu->clidr = 0x0a200023; |
1570 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1571 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1572 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 1573 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
1574 | } |
1575 | ||
1576 | static void ti925t_initfn(Object *obj) | |
1577 | { | |
1578 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1579 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
1580 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 1581 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 1582 | cpu->ctr = 0x5109149; |
0ca7e01c | 1583 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1584 | } |
1585 | ||
1586 | static void sa1100_initfn(Object *obj) | |
1587 | { | |
1588 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1589 | |
1590 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 1591 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1592 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1593 | cpu->midr = 0x4401A11B; |
0ca7e01c | 1594 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1595 | } |
1596 | ||
1597 | static void sa1110_initfn(Object *obj) | |
1598 | { | |
1599 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 1600 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1601 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1602 | cpu->midr = 0x6901B119; |
0ca7e01c | 1603 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1604 | } |
1605 | ||
1606 | static void pxa250_initfn(Object *obj) | |
1607 | { | |
1608 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1609 | |
1610 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1611 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1612 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1613 | cpu->midr = 0x69052100; |
64e1671f | 1614 | cpu->ctr = 0xd172172; |
0ca7e01c | 1615 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1616 | } |
1617 | ||
1618 | static void pxa255_initfn(Object *obj) | |
1619 | { | |
1620 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1621 | |
1622 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1623 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1624 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1625 | cpu->midr = 0x69052d00; |
64e1671f | 1626 | cpu->ctr = 0xd172172; |
0ca7e01c | 1627 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1628 | } |
1629 | ||
1630 | static void pxa260_initfn(Object *obj) | |
1631 | { | |
1632 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1633 | |
1634 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1635 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1636 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1637 | cpu->midr = 0x69052903; |
64e1671f | 1638 | cpu->ctr = 0xd172172; |
0ca7e01c | 1639 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1640 | } |
1641 | ||
1642 | static void pxa261_initfn(Object *obj) | |
1643 | { | |
1644 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1645 | |
1646 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1647 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1648 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1649 | cpu->midr = 0x69052d05; |
64e1671f | 1650 | cpu->ctr = 0xd172172; |
0ca7e01c | 1651 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1652 | } |
1653 | ||
1654 | static void pxa262_initfn(Object *obj) | |
1655 | { | |
1656 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1657 | |
1658 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1659 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1660 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1661 | cpu->midr = 0x69052d06; |
64e1671f | 1662 | cpu->ctr = 0xd172172; |
0ca7e01c | 1663 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1664 | } |
1665 | ||
1666 | static void pxa270a0_initfn(Object *obj) | |
1667 | { | |
1668 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1669 | |
1670 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1671 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1672 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1673 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1674 | cpu->midr = 0x69054110; |
64e1671f | 1675 | cpu->ctr = 0xd172172; |
0ca7e01c | 1676 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1677 | } |
1678 | ||
1679 | static void pxa270a1_initfn(Object *obj) | |
1680 | { | |
1681 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1682 | |
1683 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1684 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1685 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1686 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1687 | cpu->midr = 0x69054111; |
64e1671f | 1688 | cpu->ctr = 0xd172172; |
0ca7e01c | 1689 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1690 | } |
1691 | ||
1692 | static void pxa270b0_initfn(Object *obj) | |
1693 | { | |
1694 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1695 | |
1696 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1697 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1698 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1699 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1700 | cpu->midr = 0x69054112; |
64e1671f | 1701 | cpu->ctr = 0xd172172; |
0ca7e01c | 1702 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1703 | } |
1704 | ||
1705 | static void pxa270b1_initfn(Object *obj) | |
1706 | { | |
1707 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1708 | |
1709 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1710 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1711 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1712 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1713 | cpu->midr = 0x69054113; |
64e1671f | 1714 | cpu->ctr = 0xd172172; |
0ca7e01c | 1715 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1716 | } |
1717 | ||
1718 | static void pxa270c0_initfn(Object *obj) | |
1719 | { | |
1720 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1721 | |
1722 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1723 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1724 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1725 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1726 | cpu->midr = 0x69054114; |
64e1671f | 1727 | cpu->ctr = 0xd172172; |
0ca7e01c | 1728 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1729 | } |
1730 | ||
1731 | static void pxa270c5_initfn(Object *obj) | |
1732 | { | |
1733 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1734 | |
1735 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1736 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1737 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1738 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1739 | cpu->midr = 0x69054117; |
64e1671f | 1740 | cpu->ctr = 0xd172172; |
0ca7e01c | 1741 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1742 | } |
1743 | ||
bab52d4b PM |
1744 | #ifndef TARGET_AARCH64 |
1745 | /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); | |
1746 | * otherwise, a CPU with as many features enabled as our emulation supports. | |
1747 | * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; | |
1748 | * this only needs to handle 32 bits. | |
1749 | */ | |
1750 | static void arm_max_initfn(Object *obj) | |
1751 | { | |
1752 | ARMCPU *cpu = ARM_CPU(obj); | |
1753 | ||
1754 | if (kvm_enabled()) { | |
1755 | kvm_arm_set_cpu_features_from_host(cpu); | |
1756 | } else { | |
1757 | cortex_a15_initfn(obj); | |
a0032cc5 PM |
1758 | #ifdef CONFIG_USER_ONLY |
1759 | /* We don't set these in system emulation mode for the moment, | |
1760 | * since we don't correctly set the ID registers to advertise them, | |
bab52d4b | 1761 | */ |
a0032cc5 PM |
1762 | set_feature(&cpu->env, ARM_FEATURE_V8); |
1763 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
1764 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1765 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
1766 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); | |
1767 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
1768 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
1769 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
1770 | set_feature(&cpu->env, ARM_FEATURE_CRC); | |
1771 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | |
1772 | set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | |
bab52d4b | 1773 | #endif |
a0032cc5 | 1774 | } |
777dc784 | 1775 | } |
f5f6d38b | 1776 | #endif |
777dc784 | 1777 | |
15ee776b PM |
1778 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
1779 | ||
777dc784 PM |
1780 | typedef struct ARMCPUInfo { |
1781 | const char *name; | |
1782 | void (*initfn)(Object *obj); | |
e6f010cc | 1783 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
1784 | } ARMCPUInfo; |
1785 | ||
1786 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 1787 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
1788 | { .name = "arm926", .initfn = arm926_initfn }, |
1789 | { .name = "arm946", .initfn = arm946_initfn }, | |
1790 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
1791 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
1792 | * older core than plain "arm1136". In particular this does not | |
1793 | * have the v6K features. | |
1794 | */ | |
1795 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
1796 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
1797 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
1798 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
1799 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
1800 | .class_init = arm_v7m_class_init }, | |
ba890a9b AR |
1801 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, |
1802 | .class_init = arm_v7m_class_init }, | |
c7b26382 PM |
1803 | { .name = "cortex-m33", .initfn = cortex_m33_initfn, |
1804 | .class_init = arm_v7m_class_init }, | |
d6a6b13e | 1805 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, |
dcf578ed | 1806 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, |
777dc784 PM |
1807 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
1808 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
1809 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
1810 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
1811 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
1812 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
1813 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
1814 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
1815 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
1816 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
1817 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
1818 | /* "pxa270" is an alias for "pxa270-a0" */ | |
1819 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
1820 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
1821 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
1822 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
1823 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
1824 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
1825 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
bab52d4b PM |
1826 | #ifndef TARGET_AARCH64 |
1827 | { .name = "max", .initfn = arm_max_initfn }, | |
1828 | #endif | |
f5f6d38b | 1829 | #ifdef CONFIG_USER_ONLY |
a0032cc5 | 1830 | { .name = "any", .initfn = arm_max_initfn }, |
f5f6d38b | 1831 | #endif |
15ee776b | 1832 | #endif |
83e6813a | 1833 | { .name = NULL } |
777dc784 PM |
1834 | }; |
1835 | ||
5de16430 PM |
1836 | static Property arm_cpu_properties[] = { |
1837 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 1838 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
51a9b04b | 1839 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
ce5b1bbf LV |
1840 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, |
1841 | mp_affinity, ARM64_AFFINITY_INVALID), | |
15f8b142 | 1842 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), |
f9a69711 | 1843 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), |
5de16430 PM |
1844 | DEFINE_PROP_END_OF_LIST() |
1845 | }; | |
1846 | ||
8c6084bf | 1847 | #ifdef CONFIG_USER_ONLY |
98670d47 LV |
1848 | static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, |
1849 | int rw, int mmu_idx) | |
8c6084bf PM |
1850 | { |
1851 | ARMCPU *cpu = ARM_CPU(cs); | |
1852 | CPUARMState *env = &cpu->env; | |
1853 | ||
1854 | env->exception.vaddress = address; | |
1855 | if (rw == 2) { | |
1856 | cs->exception_index = EXCP_PREFETCH_ABORT; | |
1857 | } else { | |
1858 | cs->exception_index = EXCP_DATA_ABORT; | |
1859 | } | |
1860 | return 1; | |
1861 | } | |
1862 | #endif | |
1863 | ||
b3820e6c DH |
1864 | static gchar *arm_gdb_arch_name(CPUState *cs) |
1865 | { | |
1866 | ARMCPU *cpu = ARM_CPU(cs); | |
1867 | CPUARMState *env = &cpu->env; | |
1868 | ||
1869 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
1870 | return g_strdup("iwmmxt"); | |
1871 | } | |
1872 | return g_strdup("arm"); | |
1873 | } | |
1874 | ||
dec9c2d4 AF |
1875 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
1876 | { | |
1877 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
1878 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
1879 | DeviceClass *dc = DEVICE_CLASS(oc); |
1880 | ||
bf853881 PMD |
1881 | device_class_set_parent_realize(dc, arm_cpu_realizefn, |
1882 | &acc->parent_realize); | |
5de16430 | 1883 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
1884 | |
1885 | acc->parent_reset = cc->reset; | |
1886 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
1887 | |
1888 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 1889 | cc->has_work = arm_cpu_has_work; |
e8925712 | 1890 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 1891 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 1892 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
1893 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
1894 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7510454e AF |
1895 | #ifdef CONFIG_USER_ONLY |
1896 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
1897 | #else | |
0adf7d3c | 1898 | cc->do_interrupt = arm_cpu_do_interrupt; |
30901475 | 1899 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; |
c79c0a31 | 1900 | cc->do_transaction_failed = arm_cpu_do_transaction_failed; |
0faea0c7 | 1901 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; |
017518c1 | 1902 | cc->asidx_from_attrs = arm_asidx_from_attrs; |
00b941e5 | 1903 | cc->vmsd = &vmstate_arm_cpu; |
ed50ff78 | 1904 | cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; |
da2b9140 AJ |
1905 | cc->write_elf64_note = arm_cpu_write_elf64_note; |
1906 | cc->write_elf32_note = arm_cpu_write_elf32_note; | |
00b941e5 | 1907 | #endif |
a0e372f0 | 1908 | cc->gdb_num_core_regs = 26; |
5b24c641 | 1909 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 1910 | cc->gdb_arch_name = arm_gdb_arch_name; |
200bf5b7 | 1911 | cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; |
2472b6c0 | 1912 | cc->gdb_stop_before_watchpoint = true; |
3ff6fc91 | 1913 | cc->debug_excp_handler = arm_debug_excp_handler; |
3826121d | 1914 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; |
40612000 JB |
1915 | #if !defined(CONFIG_USER_ONLY) |
1916 | cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; | |
1917 | #endif | |
48440620 PC |
1918 | |
1919 | cc->disas_set_info = arm_disas_set_info; | |
74d7fc7f | 1920 | #ifdef CONFIG_TCG |
55c3ceef | 1921 | cc->tcg_initialize = arm_translate_init; |
74d7fc7f | 1922 | #endif |
dec9c2d4 AF |
1923 | } |
1924 | ||
86f0a186 PM |
1925 | #ifdef CONFIG_KVM |
1926 | static void arm_host_initfn(Object *obj) | |
1927 | { | |
1928 | ARMCPU *cpu = ARM_CPU(obj); | |
1929 | ||
1930 | kvm_arm_set_cpu_features_from_host(cpu); | |
1931 | } | |
1932 | ||
1933 | static const TypeInfo host_arm_cpu_type_info = { | |
1934 | .name = TYPE_ARM_HOST_CPU, | |
1935 | #ifdef TARGET_AARCH64 | |
1936 | .parent = TYPE_AARCH64_CPU, | |
1937 | #else | |
1938 | .parent = TYPE_ARM_CPU, | |
1939 | #endif | |
1940 | .instance_init = arm_host_initfn, | |
1941 | }; | |
1942 | ||
1943 | #endif | |
1944 | ||
777dc784 PM |
1945 | static void cpu_register(const ARMCPUInfo *info) |
1946 | { | |
1947 | TypeInfo type_info = { | |
777dc784 PM |
1948 | .parent = TYPE_ARM_CPU, |
1949 | .instance_size = sizeof(ARMCPU), | |
1950 | .instance_init = info->initfn, | |
1951 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 1952 | .class_init = info->class_init, |
777dc784 PM |
1953 | }; |
1954 | ||
51492fd1 | 1955 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 1956 | type_register(&type_info); |
51492fd1 | 1957 | g_free((void *)type_info.name); |
777dc784 PM |
1958 | } |
1959 | ||
dec9c2d4 AF |
1960 | static const TypeInfo arm_cpu_type_info = { |
1961 | .name = TYPE_ARM_CPU, | |
1962 | .parent = TYPE_CPU, | |
1963 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 1964 | .instance_init = arm_cpu_initfn, |
07a5b0d2 | 1965 | .instance_post_init = arm_cpu_post_init, |
4b6a83fb | 1966 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 1967 | .abstract = true, |
dec9c2d4 AF |
1968 | .class_size = sizeof(ARMCPUClass), |
1969 | .class_init = arm_cpu_class_init, | |
1970 | }; | |
1971 | ||
181962fd PM |
1972 | static const TypeInfo idau_interface_type_info = { |
1973 | .name = TYPE_IDAU_INTERFACE, | |
1974 | .parent = TYPE_INTERFACE, | |
1975 | .class_size = sizeof(IDAUInterfaceClass), | |
1976 | }; | |
1977 | ||
dec9c2d4 AF |
1978 | static void arm_cpu_register_types(void) |
1979 | { | |
83e6813a | 1980 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 1981 | |
dec9c2d4 | 1982 | type_register_static(&arm_cpu_type_info); |
181962fd | 1983 | type_register_static(&idau_interface_type_info); |
83e6813a PM |
1984 | |
1985 | while (info->name) { | |
1986 | cpu_register(info); | |
1987 | info++; | |
777dc784 | 1988 | } |
86f0a186 PM |
1989 | |
1990 | #ifdef CONFIG_KVM | |
1991 | type_register_static(&host_arm_cpu_type_info); | |
1992 | #endif | |
dec9c2d4 AF |
1993 | } |
1994 | ||
1995 | type_init(arm_cpu_register_types) |