[qemu.git] / hw / ppc / virtex_ml507.c

/*
 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
 *
 * Copyright (c) 2010 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/char/serial.h"
#include "hw/block/flash.h"
#include "sysemu/sysemu.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "sysemu/device_tree.h"
#include "hw/loader.h"
#include "elf.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"

#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "ppc405.h"

#include "sysemu/block-backend.h"

#define EPAPR_MAGIC    (0x45504150)
#define FLASH_SIZE     (16 * 1024 * 1024)

#define INTC_BASEADDR       0x81800000
#define UART16550_BASEADDR  0x83e01003
#define TIMER_BASEADDR      0x83c00000
#define PFLASH_BASEADDR     0xfc000000

#define TIMER_IRQ           3
#define UART16550_IRQ       9

static struct boot_info
{
    uint32_t bootstrap_pc;
    uint32_t cmdline;
    uint32_t fdt;
    uint32_t ima_size;
    void *vfdt;
} boot_info;

/* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
                                     target_ulong va,
                                     hwaddr pa)
{
    ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];

    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1U << 31; /* up to 0x80000000  */
    tlb->EPN = va & TARGET_PAGE_MASK;
    tlb->RPN = pa & TARGET_PAGE_MASK;
    tlb->PID = 0;

    tlb = &env->tlb.tlbe[1];
    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1U << 31; /* up to 0xffffffff  */
    tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->PID = 0;
}

static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
                                      int do_init,
                                      const char *cpu_model,
                                      uint32_t sysclk)
{
    PowerPCCPU *cpu;
    CPUPPCState *env;
    qemu_irq *irqs;

    cpu = cpu_ppc_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "Unable to initialize CPU!\n");
        exit(1);
    }
    env = &cpu->env;

    ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);

    ppc_dcr_init(env, NULL, NULL);

    /* interrupt controller */
    irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
    irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
    irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
    ppcuic_init(env, irqs, 0x0C0, 0, 1);
    return cpu;
}

static void main_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    struct boot_info *bi = env->load_info;

    cpu_reset(CPU(cpu));
    /* Linux Kernel Parameters (passing device tree):
       *   r3: pointer to the fdt
       *   r4: 0
       *   r5: 0
       *   r6: epapr magic
       *   r7: size of IMA in bytes
       *   r8: 0
       *   r9: 0
    */
    env->gpr[1] = (16<<20) - 8;
    /* Provide a device-tree.  */
    env->gpr[3] = bi->fdt;
    env->nip = bi->bootstrap_pc;

    /* Create a mapping for the kernel.  */
    mmubooke_create_initial_mapping(env, 0, 0);
    env->gpr[6] = tswap32(EPAPR_MAGIC);
    env->gpr[7] = bi->ima_size;
}

#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
static int xilinx_load_device_tree(hwaddr addr,
                                      uint32_t ramsize,
                                      hwaddr initrd_base,
                                      hwaddr initrd_size,
                                      const char *kernel_cmdline)
{
    char *path;
    int fdt_size;
    void *fdt = NULL;
    int r;
    const char *dtb_filename;

    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
    if (dtb_filename) {
        fdt = load_device_tree(dtb_filename, &fdt_size);
        if (!fdt) {
            error_report("Error while loading device tree file '%s'",
                dtb_filename);
        }
    } else {
        /* Try the local "ppc.dtb" override.  */
        fdt = load_device_tree("ppc.dtb", &fdt_size);
        if (!fdt) {
            path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
            if (path) {
                fdt = load_device_tree(path, &fdt_size);
                g_free(path);
            }
        }
    }
    if (!fdt) {
        return 0;
    }

    r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
                              initrd_base);
    if (r < 0) {
        error_report("couldn't set /chosen/linux,initrd-start");
    }

    r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
                              (initrd_base + initrd_size));
    if (r < 0) {
        error_report("couldn't set /chosen/linux,initrd-end");
    }

    r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
    if (r < 0)
        fprintf(stderr, "couldn't set /chosen/bootargs\n");
    cpu_physical_memory_write(addr, fdt, fdt_size);
    return fdt_size;
}

static void virtex_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    hwaddr initrd_base = 0;
    int initrd_size = 0;
    MemoryRegion *address_space_mem = get_system_memory();
    DeviceState *dev;
    PowerPCCPU *cpu;
    CPUPPCState *env;
    hwaddr ram_base = 0;
    DriveInfo *dinfo;
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32], *cpu_irq;
    int kernel_size;
    int i;

    /* init CPUs */
    if (machine->cpu_model == NULL) {
        machine->cpu_model = "440-Xilinx";
    }

    cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_model, 400000000);
    env = &cpu->env;
    qemu_register_reset(main_cpu_reset, cpu);

    memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          (64 * 1024), FLASH_SIZE >> 16,
                          1, 0x89, 0x18, 0x0000, 0x0, 1);

    cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
    dev = qdev_create(NULL, "xlnx.xps-intc");
    qdev_prop_set_uint32(dev, "kind-of-intr", 0);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }

    serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
                   115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);

    /* 2 timers at irq 2 @ 62 Mhz.  */
    dev = qdev_create(NULL, "xlnx.xps-timer");
    qdev_prop_set_uint32(dev, "one-timer-only", 0);
    qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);

    if (kernel_filename) {
        uint64_t entry, low, high;
        hwaddr boot_offset;

        /* Boots a kernel elf binary.  */
        kernel_size = load_elf(kernel_filename, NULL, NULL,
                               &entry, &low, &high, 1, PPC_ELF_MACHINE, 0);
        boot_info.bootstrap_pc = entry & 0x00ffffff;

        if (kernel_size < 0) {
            boot_offset = 0x1200000;
            /* If we failed loading ELF's try a raw image.  */
            kernel_size = load_image_targphys(kernel_filename,
                                              boot_offset,
                                              ram_size);
            boot_info.bootstrap_pc = boot_offset;
            high = boot_info.bootstrap_pc + kernel_size + 8192;
        }

        boot_info.ima_size = kernel_size;

        /* Load initrd. */
        if (machine->initrd_filename) {
            initrd_base = high = ROUND_UP(high, 4);
            initrd_size = load_image_targphys(machine->initrd_filename,
                                              high, ram_size - high);

            if (initrd_size < 0) {
                error_report("couldn't load ram disk '%s'",
                             machine->initrd_filename);
                exit(1);
            }
            high = ROUND_UP(high + initrd_size, 4);
        }

        /* Provide a device-tree.  */
        boot_info.fdt = high + (8192 * 2);
        boot_info.fdt &= ~8191;

        xilinx_load_device_tree(boot_info.fdt, ram_size,
                                initrd_base, initrd_size,
                                kernel_cmdline);
    }
    env->load_info = &boot_info;
}

static void virtex_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx Virtex ML507 reference design";
    mc->init = virtex_init;
}

DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
Commit	Line	Data
2c50e26e EI	1	/*
	2	* Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
	3	*
	4	* Copyright (c) 2010 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
0d75590d	25	#include "qemu/osdep.h"
83c9f4ca PB	26	#include "hw/sysbus.h"
83c9f4ca PB	27	#include "hw/hw.h"
0d09e41a PB	28	#include "hw/char/serial.h"
0d09e41a PB	29	#include "hw/block/flash.h"
9c17d615	30	#include "sysemu/sysemu.h"
bd2be150	31	#include "hw/devices.h"
83c9f4ca	32	#include "hw/boards.h"
9c17d615	33	#include "sysemu/device_tree.h"
83c9f4ca	34	#include "hw/loader.h"
2c50e26e	35	#include "elf.h"
d49b6836	36	#include "qemu/error-report.h"
1de7afc9	37	#include "qemu/log.h"
022c62cb	38	#include "exec/address-spaces.h"
2c50e26e	39
0d09e41a PB	40	#include "hw/ppc/ppc.h"
0d09e41a PB	41	#include "hw/ppc/ppc4xx.h"
47b43a1f	42	#include "ppc405.h"
2c50e26e	43
fa1d36df	44	#include "sysemu/block-backend.h"
2c50e26e EI	45
	46	#define EPAPR_MAGIC (0x45504150)
	47	#define FLASH_SIZE (16 * 1024 * 1024)
	48
81cce07e PC	49	#define INTC_BASEADDR 0x81800000
	50	#define UART16550_BASEADDR 0x83e01003
	51	#define TIMER_BASEADDR 0x83c00000
	52	#define PFLASH_BASEADDR 0xfc000000
	53
	54	#define TIMER_IRQ 3
	55	#define UART16550_IRQ 9
	56
2c50e26e EI	57	static struct boot_info
	58	{
	59	uint32_t bootstrap_pc;
	60	uint32_t cmdline;
	61	uint32_t fdt;
	62	uint32_t ima_size;
	63	void *vfdt;
	64	} boot_info;
	65
	66	/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
e2684c0b	67	static void mmubooke_create_initial_mapping(CPUPPCState *env,
2c50e26e	68	target_ulong va,
a8170e5e	69	hwaddr pa)
2c50e26e	70	{
1c53accc	71	ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
2c50e26e EI	72
	73	tlb->attr = 0;
	74	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
a1f7f97b	75	tlb->size = 1U << 31; /* up to 0x80000000 */
2c50e26e EI	76	tlb->EPN = va & TARGET_PAGE_MASK;
	77	tlb->RPN = pa & TARGET_PAGE_MASK;
	78	tlb->PID = 0;
	79
1c53accc	80	tlb = &env->tlb.tlbe[1];
2c50e26e EI	81	tlb->attr = 0;
2c50e26e EI	82	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
a1f7f97b	83	tlb->size = 1U << 31; /* up to 0xffffffff */
2c50e26e EI	84	tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
	85	tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
	86	tlb->PID = 0;
	87	}
	88
68281699 AF	89	static PowerPCCPU ppc440_init_xilinx(ram_addr_t ram_size,
	90	int do_init,
	91	const char *cpu_model,
	92	uint32_t sysclk)
2c50e26e	93	{
d1d4938b	94	PowerPCCPU *cpu;
e2684c0b	95	CPUPPCState *env;
2c50e26e EI	96	qemu_irq *irqs;
2c50e26e EI	97
d1d4938b AF	98	cpu = cpu_ppc_init(cpu_model);
d1d4938b AF	99	if (cpu == NULL) {
2c50e26e EI	100	fprintf(stderr, "Unable to initialize CPU!\n");
	101	exit(1);
	102	}
d1d4938b	103	env = &cpu->env;
2c50e26e	104
a34a92b9	105	ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
2c50e26e EI	106
	107	ppc_dcr_init(env, NULL, NULL);
	108
	109	/* interrupt controller */
7267c094	110	irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2c50e26e EI	111	irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2c50e26e EI	112	irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
49a2942d	113	ppcuic_init(env, irqs, 0x0C0, 0, 1);
68281699	114	return cpu;
2c50e26e EI	115	}
	116
	117	static void main_cpu_reset(void *opaque)
	118	{
f8031482 AF	119	PowerPCCPU *cpu = opaque;
f8031482 AF	120	CPUPPCState *env = &cpu->env;
2c50e26e EI	121	struct boot_info *bi = env->load_info;
2c50e26e EI	122
f8031482	123	cpu_reset(CPU(cpu));
2c50e26e EI	124	/* Linux Kernel Parameters (passing device tree):
	125	* r3: pointer to the fdt
	126	* r4: 0
	127	* r5: 0
	128	* r6: epapr magic
	129	* r7: size of IMA in bytes
	130	* r8: 0
	131	* r9: 0
	132	*/
	133	env->gpr[1] = (16<<20) - 8;
	134	/* Provide a device-tree. */
	135	env->gpr[3] = bi->fdt;
	136	env->nip = bi->bootstrap_pc;
	137
	138	/* Create a mapping for the kernel. */
	139	mmubooke_create_initial_mapping(env, 0, 0);
	140	env->gpr[6] = tswap32(EPAPR_MAGIC);
	141	env->gpr[7] = bi->ima_size;
	142	}
	143
	144	#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
a8170e5e	145	static int xilinx_load_device_tree(hwaddr addr,
2c50e26e	146	uint32_t ramsize,
a8170e5e AK	147	hwaddr initrd_base,
a8170e5e AK	148	hwaddr initrd_size,
2c50e26e EI	149	const char *kernel_cmdline)
	150	{
	151	char *path;
	152	int fdt_size;
daf285b6	153	void *fdt = NULL;
2c50e26e	154	int r;
daf285b6	155	const char *dtb_filename;
2c50e26e	156
daf285b6 EV	157	dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
	158	if (dtb_filename) {
	159	fdt = load_device_tree(dtb_filename, &fdt_size);
	160	if (!fdt) {
	161	error_report("Error while loading device tree file '%s'",
	162	dtb_filename);
2c50e26e	163	}
daf285b6 EV	164	} else {
	165	/* Try the local "ppc.dtb" override. */
	166	fdt = load_device_tree("ppc.dtb", &fdt_size);
3b2e3dc9	167	if (!fdt) {
daf285b6 EV	168	path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
	169	if (path) {
	170	fdt = load_device_tree(path, &fdt_size);
	171	g_free(path);
	172	}
3b2e3dc9	173	}
2c50e26e	174	}
daf285b6 EV	175	if (!fdt) {
	176	return 0;
	177	}
0658aa9c EI	178
	179	r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
	180	initrd_base);
	181	if (r < 0) {
	182	error_report("couldn't set /chosen/linux,initrd-start");
	183	}
	184
	185	r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
	186	(initrd_base + initrd_size));
	187	if (r < 0) {
	188	error_report("couldn't set /chosen/linux,initrd-end");
	189	}
	190
5a4348d1	191	r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
2c50e26e EI	192	if (r < 0)
2c50e26e EI	193	fprintf(stderr, "couldn't set /chosen/bootargs\n");
e1fe50dc	194	cpu_physical_memory_write(addr, fdt, fdt_size);
2c50e26e EI	195	return fdt_size;
	196	}
	197
3ef96221	198	static void virtex_init(MachineState *machine)
2c50e26e	199	{
3ef96221	200	ram_addr_t ram_size = machine->ram_size;
3ef96221 MA	201	const char *kernel_filename = machine->kernel_filename;
3ef96221 MA	202	const char *kernel_cmdline = machine->kernel_cmdline;
0658aa9c EI	203	hwaddr initrd_base = 0;
0658aa9c EI	204	int initrd_size = 0;
39186d8a	205	MemoryRegion *address_space_mem = get_system_memory();
2c50e26e	206	DeviceState *dev;
68281699	207	PowerPCCPU *cpu;
e2684c0b	208	CPUPPCState *env;
a8170e5e	209	hwaddr ram_base = 0;
2c50e26e	210	DriveInfo *dinfo;
333b13fc	211	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
2c50e26e	212	qemu_irq irq[32], *cpu_irq;
2c50e26e EI	213	int kernel_size;
	214	int i;
	215
	216	/* init CPUs */
19fb2c36 BR	217	if (machine->cpu_model == NULL) {
19fb2c36 BR	218	machine->cpu_model = "440-Xilinx";
2c50e26e EI	219	}
2c50e26e EI	220
19fb2c36	221	cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_model, 400000000);
68281699	222	env = &cpu->env;
f8031482	223	qemu_register_reset(main_cpu_reset, cpu);
2c50e26e	224
e938ba0c	225	memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
333b13fc	226	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
2c50e26e	227
2c50e26e	228	dinfo = drive_get(IF_PFLASH, 0, 0);
81cce07e	229	pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
4be74634	230	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df	231	(64 * 1024), FLASH_SIZE >> 16,
01e0451a	232	1, 0x89, 0x18, 0x0000, 0x0, 1);
2c50e26e EI	233
2c50e26e EI	234	cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
13c9bfbf PC	235	dev = qdev_create(NULL, "xlnx.xps-intc");
	236	qdev_prop_set_uint32(dev, "kind-of-intr", 0);
	237	qdev_init_nofail(dev);
	238	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
	239	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
2c50e26e EI	240	for (i = 0; i < 32; i++) {
	241	irq[i] = qdev_get_gpio_in(dev, i);
	242	}
	243
81cce07e PC	244	serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
81cce07e PC	245	115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
2c50e26e EI	246
2c50e26e EI	247	/* 2 timers at irq 2 @ 62 Mhz. */
29873712 PC	248	dev = qdev_create(NULL, "xlnx.xps-timer");
	249	qdev_prop_set_uint32(dev, "one-timer-only", 0);
	250	qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
	251	qdev_init_nofail(dev);
	252	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
	253	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
2c50e26e EI	254
	255	if (kernel_filename) {
	256	uint64_t entry, low, high;
a8170e5e	257	hwaddr boot_offset;
2c50e26e EI	258
	259	/* Boots a kernel elf binary. */
	260	kernel_size = load_elf(kernel_filename, NULL, NULL,
4ecd4d16	261	&entry, &low, &high, 1, PPC_ELF_MACHINE, 0);
2c50e26e EI	262	boot_info.bootstrap_pc = entry & 0x00ffffff;
	263
	264	if (kernel_size < 0) {
	265	boot_offset = 0x1200000;
	266	/* If we failed loading ELF's try a raw image. */
	267	kernel_size = load_image_targphys(kernel_filename,
	268	boot_offset,
	269	ram_size);
	270	boot_info.bootstrap_pc = boot_offset;
	271	high = boot_info.bootstrap_pc + kernel_size + 8192;
	272	}
	273
	274	boot_info.ima_size = kernel_size;
	275
0658aa9c	276	/* Load initrd. */
3ef96221	277	if (machine->initrd_filename) {
0658aa9c	278	initrd_base = high = ROUND_UP(high, 4);
3ef96221	279	initrd_size = load_image_targphys(machine->initrd_filename,
0658aa9c EI	280	high, ram_size - high);
	281
	282	if (initrd_size < 0) {
	283	error_report("couldn't load ram disk '%s'",
3ef96221	284	machine->initrd_filename);
0658aa9c EI	285	exit(1);
	286	}
	287	high = ROUND_UP(high + initrd_size, 4);
	288	}
	289
2c50e26e EI	290	/* Provide a device-tree. */
	291	boot_info.fdt = high + (8192 * 2);
	292	boot_info.fdt &= ~8191;
0658aa9c EI	293
	294	xilinx_load_device_tree(boot_info.fdt, ram_size,
	295	initrd_base, initrd_size,
	296	kernel_cmdline);
2c50e26e EI	297	}
	298	env->load_info = &boot_info;
	299	}
	300
e264d29d	301	static void virtex_machine_init(MachineClass *mc)
2c50e26e	302	{
e264d29d EH	303	mc->desc = "Xilinx Virtex ML507 reference design";
e264d29d EH	304	mc->init = virtex_init;
2c50e26e EI	305	}
2c50e26e EI	306
e264d29d	307	DEFINE_MACHINE("virtex-ml507", virtex_machine_init)