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Enable generic accepts-anything cpu by default for usermode emulation.
[qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
2bec46dc 34#include "kvm.h"
e6e5ad80 35
a5082316
FB		 36/*
37 * TODO:
ad81218e 38 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
e36f36e1 43//#define DEBUG_CIRRUS
a21ae81d 44//#define DEBUG_BITBLT
e36f36e1 45
e6e5ad80
FB		 46/***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
e6e5ad80
FB		 52// ID
53#define CIRRUS_ID_CLGD5422 (0x23<<2)
54#define CIRRUS_ID_CLGD5426 (0x24<<2)
55#define CIRRUS_ID_CLGD5424 (0x25<<2)
56#define CIRRUS_ID_CLGD5428 (0x26<<2)
57#define CIRRUS_ID_CLGD5430 (0x28<<2)
58#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 59#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 60#define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62// sequencer 0x07
63#define CIRRUS_SR7_BPP_VGA 0x00
64#define CIRRUS_SR7_BPP_SVGA 0x01
65#define CIRRUS_SR7_BPP_MASK 0x0e
66#define CIRRUS_SR7_BPP_8 0x00
67#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68#define CIRRUS_SR7_BPP_24 0x04
69#define CIRRUS_SR7_BPP_16 0x06
70#define CIRRUS_SR7_BPP_32 0x08
71#define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73// sequencer 0x0f
74#define CIRRUS_MEMSIZE_512k 0x08
75#define CIRRUS_MEMSIZE_1M 0x10
76#define CIRRUS_MEMSIZE_2M 0x18
77#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79// sequencer 0x12
80#define CIRRUS_CURSOR_SHOW 0x01
81#define CIRRUS_CURSOR_HIDDENPEL 0x02
82#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84// sequencer 0x17
85#define CIRRUS_BUSTYPE_VLBFAST 0x10
86#define CIRRUS_BUSTYPE_PCI 0x20
87#define CIRRUS_BUSTYPE_VLBSLOW 0x30
88#define CIRRUS_BUSTYPE_ISA 0x38
89#define CIRRUS_MMIO_ENABLE 0x04
90#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93// control 0x0b
94#define CIRRUS_BANKING_DUAL 0x01
95#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97// control 0x30
98#define CIRRUS_BLTMODE_BACKWARDS 0x01
99#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103#define CIRRUS_BLTMODE_COLOREXPAND 0x80
104#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110// control 0x31
111#define CIRRUS_BLT_BUSY 0x01
112#define CIRRUS_BLT_START 0x02
113#define CIRRUS_BLT_RESET 0x04
114#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 115#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 116
117// control 0x32
118#define CIRRUS_ROP_0 0x00
119#define CIRRUS_ROP_SRC_AND_DST 0x05
120#define CIRRUS_ROP_NOP 0x06
121#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122#define CIRRUS_ROP_NOTDST 0x0b
123#define CIRRUS_ROP_SRC 0x0d
124#define CIRRUS_ROP_1 0x0e
125#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126#define CIRRUS_ROP_SRC_XOR_DST 0x59
127#define CIRRUS_ROP_SRC_OR_DST 0x6d
128#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131#define CIRRUS_ROP_NOTSRC 0xd0
132#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
a5082316
FB		 135#define CIRRUS_ROP_NOP_INDEX 2
136#define CIRRUS_ROP_SRC_INDEX 5
137
a21ae81d 138// control 0x33
a5082316 139#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 140#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 141#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 142
e6e5ad80
FB		 143// memory-mapped IO
144#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153#define CIRRUS_MMIO_BLTMODE 0x18 // byte
154#define CIRRUS_MMIO_BLTROP 0x1a // byte
155#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
e6e5ad80
FB		 174// PCI 0x04: command(word), 0x06(word): status
175#define PCI_COMMAND_IOACCESS 0x0001
176#define PCI_COMMAND_MEMACCESS 0x0002
177#define PCI_COMMAND_BUSMASTER 0x0004
178#define PCI_COMMAND_SPECIALCYCLE 0x0008
179#define PCI_COMMAND_MEMWRITEINVALID 0x0010
180#define PCI_COMMAND_PALETTESNOOPING 0x0020
181#define PCI_COMMAND_PARITYDETECTION 0x0040
182#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
183#define PCI_COMMAND_SERR 0x0100
184#define PCI_COMMAND_BACKTOBACKTRANS 0x0200
185// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
186#define PCI_CLASS_BASE_DISPLAY 0x03
187// PCI 0x08, 0x00ff0000
188#define PCI_CLASS_SUB_VGA 0x00
189// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
190#define PCI_CLASS_HEADERTYPE_00h 0x00
191// 0x10-0x3f (headertype 00h)
192// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
193// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
194#define PCI_MAP_MEM 0x0
195#define PCI_MAP_IO 0x1
196#define PCI_MAP_MEM_ADDR_MASK (~0xf)
197#define PCI_MAP_IO_ADDR_MASK (~0x3)
198#define PCI_MAP_MEMFLAGS_32BIT 0x0
199#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
200#define PCI_MAP_MEMFLAGS_64BIT 0x4
201#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
202// PCI 0x28: cardbus CIS pointer
203// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
204// PCI 0x30: expansion ROM base address
205#define PCI_ROMBIOS_ENABLED 0x1
206// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
207// PCI 0x38: reserved
208// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
209
a21ae81d 210#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80
FB		 211
212
213/* I/O and memory hook */
214#define CIRRUS_HOOK_NOT_HANDLED 0
215#define CIRRUS_HOOK_HANDLED 1
216
b2b183c2
AL		 217#define ABS(a) ((signed)(a) > 0 ? a : -a)
218
b2eb849d
AJ		 219#define BLTUNSAFE(s) \
220 ( \
221 ( /* check dst is within bounds */ \
b2b183c2 222 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d
AJ		 223 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
224 (s)->vram_size \
225 ) || \
226 ( /* check src is within bounds */ \
b2b183c2 227 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d
AJ		 228 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
229 (s)->vram_size \
230 ) \
231 )
232
a5082316
FB		 233struct CirrusVGAState;
234typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
235 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 236 int dstpitch, int srcpitch,
237 int bltwidth, int bltheight);
a5082316
FB		 238typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
239 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 240
241typedef struct CirrusVGAState {
4e3e9d0b 242 VGA_STATE_COMMON
e6e5ad80
FB		 243
244 int cirrus_linear_io_addr;
a5082316 245 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 246 int cirrus_mmio_io_addr;
247 uint32_t cirrus_addr_mask;
78e127ef 248 uint32_t linear_mmio_mask;
e6e5ad80
FB		 249 uint8_t cirrus_shadow_gr0;
250 uint8_t cirrus_shadow_gr1;
251 uint8_t cirrus_hidden_dac_lockindex;
252 uint8_t cirrus_hidden_dac_data;
253 uint32_t cirrus_bank_base[2];
254 uint32_t cirrus_bank_limit[2];
255 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 256 uint32_t hw_cursor_x;
257 uint32_t hw_cursor_y;
e6e5ad80
FB		 258 int cirrus_blt_pixelwidth;
259 int cirrus_blt_width;
260 int cirrus_blt_height;
261 int cirrus_blt_dstpitch;
262 int cirrus_blt_srcpitch;
a5082316
FB		 263 uint32_t cirrus_blt_fgcol;
264 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 265 uint32_t cirrus_blt_dstaddr;
266 uint32_t cirrus_blt_srcaddr;
267 uint8_t cirrus_blt_mode;
a5082316 268 uint8_t cirrus_blt_modeext;
e6e5ad80 269 cirrus_bitblt_rop_t cirrus_rop;
a5082316 270#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 271 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
272 uint8_t *cirrus_srcptr;
273 uint8_t *cirrus_srcptr_end;
274 uint32_t cirrus_srccounter;
a5082316
FB		 275 /* hwcursor display state */
276 int last_hw_cursor_size;
277 int last_hw_cursor_x;
278 int last_hw_cursor_y;
279 int last_hw_cursor_y_start;
280 int last_hw_cursor_y_end;
78e127ef 281 int real_vram_size; /* XXX: suppress that */
8926b517 282 CPUWriteMemoryFunc **cirrus_linear_write;
4abc796d
BS		 283 int device_id;
284 int bustype;
e6e5ad80
FB		 285} CirrusVGAState;
286
287typedef struct PCICirrusVGAState {
288 PCIDevice dev;
289 CirrusVGAState cirrus_vga;
290} PCICirrusVGAState;
291
a5082316 292static uint8_t rop_to_index[256];
3b46e624 293
e6e5ad80
FB		 294/***************************************
295 *
296 * prototypes.
297 *
298 ***************************************/
299
300
8926b517
FB		 301static void cirrus_bitblt_reset(CirrusVGAState *s);
302static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 303
304/***************************************
305 *
306 * raster operations
307 *
308 ***************************************/
309
a5082316
FB		 310static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
311 uint8_t *dst,const uint8_t *src,
312 int dstpitch,int srcpitch,
313 int bltwidth,int bltheight)
314{
e6e5ad80
FB		 315}
316
a5082316
FB		 317static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
318 uint8_t *dst,
319 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 320{
a5082316 321}
e6e5ad80 322
a5082316
FB		 323#define ROP_NAME 0
324#define ROP_OP(d, s) d = 0
325#include "cirrus_vga_rop.h"
e6e5ad80 326
a5082316
FB		 327#define ROP_NAME src_and_dst
328#define ROP_OP(d, s) d = (s) & (d)
329#include "cirrus_vga_rop.h"
e6e5ad80 330
a5082316
FB		 331#define ROP_NAME src_and_notdst
332#define ROP_OP(d, s) d = (s) & (~(d))
333#include "cirrus_vga_rop.h"
e6e5ad80 334
a5082316
FB		 335#define ROP_NAME notdst
336#define ROP_OP(d, s) d = ~(d)
337#include "cirrus_vga_rop.h"
e6e5ad80 338
a5082316
FB		 339#define ROP_NAME src
340#define ROP_OP(d, s) d = s
341#include "cirrus_vga_rop.h"
e6e5ad80 342
a5082316 343#define ROP_NAME 1
4c8732d7 344#define ROP_OP(d, s) d = ~0
a5082316
FB		 345#include "cirrus_vga_rop.h"
346
347#define ROP_NAME notsrc_and_dst
348#define ROP_OP(d, s) d = (~(s)) & (d)
349#include "cirrus_vga_rop.h"
350
351#define ROP_NAME src_xor_dst
352#define ROP_OP(d, s) d = (s) ^ (d)
353#include "cirrus_vga_rop.h"
354
355#define ROP_NAME src_or_dst
356#define ROP_OP(d, s) d = (s) | (d)
357#include "cirrus_vga_rop.h"
358
359#define ROP_NAME notsrc_or_notdst
360#define ROP_OP(d, s) d = (~(s)) | (~(d))
361#include "cirrus_vga_rop.h"
362
363#define ROP_NAME src_notxor_dst
364#define ROP_OP(d, s) d = ~((s) ^ (d))
365#include "cirrus_vga_rop.h"
e6e5ad80 366
a5082316
FB		 367#define ROP_NAME src_or_notdst
368#define ROP_OP(d, s) d = (s) | (~(d))
369#include "cirrus_vga_rop.h"
370
371#define ROP_NAME notsrc
372#define ROP_OP(d, s) d = (~(s))
373#include "cirrus_vga_rop.h"
374
375#define ROP_NAME notsrc_or_dst
376#define ROP_OP(d, s) d = (~(s)) | (d)
377#include "cirrus_vga_rop.h"
378
379#define ROP_NAME notsrc_and_notdst
380#define ROP_OP(d, s) d = (~(s)) & (~(d))
381#include "cirrus_vga_rop.h"
382
383static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
384 cirrus_bitblt_rop_fwd_0,
385 cirrus_bitblt_rop_fwd_src_and_dst,
386 cirrus_bitblt_rop_nop,
387 cirrus_bitblt_rop_fwd_src_and_notdst,
388 cirrus_bitblt_rop_fwd_notdst,
389 cirrus_bitblt_rop_fwd_src,
390 cirrus_bitblt_rop_fwd_1,
391 cirrus_bitblt_rop_fwd_notsrc_and_dst,
392 cirrus_bitblt_rop_fwd_src_xor_dst,
393 cirrus_bitblt_rop_fwd_src_or_dst,
394 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
395 cirrus_bitblt_rop_fwd_src_notxor_dst,
396 cirrus_bitblt_rop_fwd_src_or_notdst,
397 cirrus_bitblt_rop_fwd_notsrc,
398 cirrus_bitblt_rop_fwd_notsrc_or_dst,
399 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
400};
401
402static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
403 cirrus_bitblt_rop_bkwd_0,
404 cirrus_bitblt_rop_bkwd_src_and_dst,
405 cirrus_bitblt_rop_nop,
406 cirrus_bitblt_rop_bkwd_src_and_notdst,
407 cirrus_bitblt_rop_bkwd_notdst,
408 cirrus_bitblt_rop_bkwd_src,
409 cirrus_bitblt_rop_bkwd_1,
410 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
411 cirrus_bitblt_rop_bkwd_src_xor_dst,
412 cirrus_bitblt_rop_bkwd_src_or_dst,
413 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
414 cirrus_bitblt_rop_bkwd_src_notxor_dst,
415 cirrus_bitblt_rop_bkwd_src_or_notdst,
416 cirrus_bitblt_rop_bkwd_notsrc,
417 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
418 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
419};
96cf2df8
TS		 420
421#define TRANSP_ROP(name) {\
422 name ## _8,\
423 name ## _16,\
424 }
425#define TRANSP_NOP(func) {\
426 func,\
427 func,\
428 }
429
430static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
431 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
433 TRANSP_NOP(cirrus_bitblt_rop_nop),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
447};
448
449static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
450 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
452 TRANSP_NOP(cirrus_bitblt_rop_nop),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
466};
467
a5082316
FB		 468#define ROP2(name) {\
469 name ## _8,\
470 name ## _16,\
471 name ## _24,\
472 name ## _32,\
473 }
474
475#define ROP_NOP2(func) {\
476 func,\
477 func,\
478 func,\
479 func,\
480 }
481
e69390ce
FB		 482static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
483 ROP2(cirrus_patternfill_0),
484 ROP2(cirrus_patternfill_src_and_dst),
485 ROP_NOP2(cirrus_bitblt_rop_nop),
486 ROP2(cirrus_patternfill_src_and_notdst),
487 ROP2(cirrus_patternfill_notdst),
488 ROP2(cirrus_patternfill_src),
489 ROP2(cirrus_patternfill_1),
490 ROP2(cirrus_patternfill_notsrc_and_dst),
491 ROP2(cirrus_patternfill_src_xor_dst),
492 ROP2(cirrus_patternfill_src_or_dst),
493 ROP2(cirrus_patternfill_notsrc_or_notdst),
494 ROP2(cirrus_patternfill_src_notxor_dst),
495 ROP2(cirrus_patternfill_src_or_notdst),
496 ROP2(cirrus_patternfill_notsrc),
497 ROP2(cirrus_patternfill_notsrc_or_dst),
498 ROP2(cirrus_patternfill_notsrc_and_notdst),
499};
500
a5082316
FB		 501static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
502 ROP2(cirrus_colorexpand_transp_0),
503 ROP2(cirrus_colorexpand_transp_src_and_dst),
504 ROP_NOP2(cirrus_bitblt_rop_nop),
505 ROP2(cirrus_colorexpand_transp_src_and_notdst),
506 ROP2(cirrus_colorexpand_transp_notdst),
507 ROP2(cirrus_colorexpand_transp_src),
508 ROP2(cirrus_colorexpand_transp_1),
509 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
510 ROP2(cirrus_colorexpand_transp_src_xor_dst),
511 ROP2(cirrus_colorexpand_transp_src_or_dst),
512 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
513 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
514 ROP2(cirrus_colorexpand_transp_src_or_notdst),
515 ROP2(cirrus_colorexpand_transp_notsrc),
516 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
517 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
518};
519
520static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
521 ROP2(cirrus_colorexpand_0),
522 ROP2(cirrus_colorexpand_src_and_dst),
523 ROP_NOP2(cirrus_bitblt_rop_nop),
524 ROP2(cirrus_colorexpand_src_and_notdst),
525 ROP2(cirrus_colorexpand_notdst),
526 ROP2(cirrus_colorexpand_src),
527 ROP2(cirrus_colorexpand_1),
528 ROP2(cirrus_colorexpand_notsrc_and_dst),
529 ROP2(cirrus_colorexpand_src_xor_dst),
530 ROP2(cirrus_colorexpand_src_or_dst),
531 ROP2(cirrus_colorexpand_notsrc_or_notdst),
532 ROP2(cirrus_colorexpand_src_notxor_dst),
533 ROP2(cirrus_colorexpand_src_or_notdst),
534 ROP2(cirrus_colorexpand_notsrc),
535 ROP2(cirrus_colorexpand_notsrc_or_dst),
536 ROP2(cirrus_colorexpand_notsrc_and_notdst),
537};
538
b30d4608
FB		 539static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
540 ROP2(cirrus_colorexpand_pattern_transp_0),
541 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
542 ROP_NOP2(cirrus_bitblt_rop_nop),
543 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
544 ROP2(cirrus_colorexpand_pattern_transp_notdst),
545 ROP2(cirrus_colorexpand_pattern_transp_src),
546 ROP2(cirrus_colorexpand_pattern_transp_1),
547 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
548 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
549 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
550 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
551 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
552 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
553 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
554 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
556};
557
558static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
559 ROP2(cirrus_colorexpand_pattern_0),
560 ROP2(cirrus_colorexpand_pattern_src_and_dst),
561 ROP_NOP2(cirrus_bitblt_rop_nop),
562 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
563 ROP2(cirrus_colorexpand_pattern_notdst),
564 ROP2(cirrus_colorexpand_pattern_src),
565 ROP2(cirrus_colorexpand_pattern_1),
566 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
567 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
568 ROP2(cirrus_colorexpand_pattern_src_or_dst),
569 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
570 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
571 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
572 ROP2(cirrus_colorexpand_pattern_notsrc),
573 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
574 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
575};
576
a5082316
FB		 577static const cirrus_fill_t cirrus_fill[16][4] = {
578 ROP2(cirrus_fill_0),
579 ROP2(cirrus_fill_src_and_dst),
580 ROP_NOP2(cirrus_bitblt_fill_nop),
581 ROP2(cirrus_fill_src_and_notdst),
582 ROP2(cirrus_fill_notdst),
583 ROP2(cirrus_fill_src),
584 ROP2(cirrus_fill_1),
585 ROP2(cirrus_fill_notsrc_and_dst),
586 ROP2(cirrus_fill_src_xor_dst),
587 ROP2(cirrus_fill_src_or_dst),
588 ROP2(cirrus_fill_notsrc_or_notdst),
589 ROP2(cirrus_fill_src_notxor_dst),
590 ROP2(cirrus_fill_src_or_notdst),
591 ROP2(cirrus_fill_notsrc),
592 ROP2(cirrus_fill_notsrc_or_dst),
593 ROP2(cirrus_fill_notsrc_and_notdst),
594};
595
596static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 597{
a5082316
FB		 598 unsigned int color;
599 switch (s->cirrus_blt_pixelwidth) {
600 case 1:
601 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
602 break;
603 case 2:
604 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
605 s->cirrus_blt_fgcol = le16_to_cpu(color);
606 break;
607 case 3:
5fafdf24 608 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
a5082316
FB		 609 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
610 break;
611 default:
612 case 4:
613 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
614 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
615 s->cirrus_blt_fgcol = le32_to_cpu(color);
616 break;
e6e5ad80
FB		 617 }
618}
619
a5082316 620static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 621{
a5082316 622 unsigned int color;
e6e5ad80
FB		 623 switch (s->cirrus_blt_pixelwidth) {
624 case 1:
a5082316
FB		 625 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
626 break;
e6e5ad80 627 case 2:
a5082316
FB		 628 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
629 s->cirrus_blt_bgcol = le16_to_cpu(color);
630 break;
e6e5ad80 631 case 3:
5fafdf24 632 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
a5082316
FB		 633 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
634 break;
e6e5ad80 635 default:
a5082316
FB		 636 case 4:
637 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
638 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
639 s->cirrus_blt_bgcol = le32_to_cpu(color);
640 break;
e6e5ad80
FB		 641 }
642}
643
644static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
645 int off_pitch, int bytesperline,
646 int lines)
647{
648 int y;
649 int off_cur;
650 int off_cur_end;
651
652 for (y = 0; y < lines; y++) {
653 off_cur = off_begin;
b2eb849d 654 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 655 off_cur &= TARGET_PAGE_MASK;
656 while (off_cur < off_cur_end) {
657 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
658 off_cur += TARGET_PAGE_SIZE;
659 }
660 off_begin += off_pitch;
661 }
662}
663
e6e5ad80
FB		 664static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
665 const uint8_t * src)
666{
e6e5ad80 667 uint8_t *dst;
e6e5ad80 668
b2eb849d
AJ		 669 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
670
671 if (BLTUNSAFE(s))
672 return 0;
673
e69390ce 674 (*s->cirrus_rop) (s, dst, src,
5fafdf24 675 s->cirrus_blt_dstpitch, 0,
e69390ce 676 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 677 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 678 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
679 s->cirrus_blt_height);
e6e5ad80
FB		 680 return 1;
681}
682
a21ae81d
FB		 683/* fill */
684
a5082316 685static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 686{
a5082316 687 cirrus_fill_t rop_func;
a21ae81d 688
b2eb849d
AJ		 689 if (BLTUNSAFE(s))
690 return 0;
a5082316 691 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
b2eb849d 692 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 693 s->cirrus_blt_dstpitch,
694 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 695 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
696 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
697 s->cirrus_blt_height);
698 cirrus_bitblt_reset(s);
699 return 1;
700}
701
e6e5ad80
FB		 702/***************************************
703 *
704 * bitblt (video-to-video)
705 *
706 ***************************************/
707
708static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
709{
710 return cirrus_bitblt_common_patterncopy(s,
b2eb849d
AJ		 711 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
712 s->cirrus_addr_mask));
e6e5ad80
FB		 713}
714
24236869 715static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 716{
24236869
FB		 717 int sx, sy;
718 int dx, dy;
719 int width, height;
720 int depth;
721 int notify = 0;
722
723 depth = s->get_bpp((VGAState *)s) / 8;
724 s->get_resolution((VGAState *)s, &width, &height);
725
726 /* extra x, y */
d85d0d38
AL		 727 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
728 sy = (src / ABS(s->cirrus_blt_srcpitch));
729 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
730 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869
FB		 731
732 /* normalize width */
733 w /= depth;
734
735 /* if we're doing a backward copy, we have to adjust
736 our x/y to be the upper left corner (instead of the lower
737 right corner) */
738 if (s->cirrus_blt_dstpitch < 0) {
739 sx -= (s->cirrus_blt_width / depth) - 1;
740 dx -= (s->cirrus_blt_width / depth) - 1;
741 sy -= s->cirrus_blt_height - 1;
742 dy -= s->cirrus_blt_height - 1;
743 }
744
745 /* are we in the visible portion of memory? */
746 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
747 (sx + w) <= width && (sy + h) <= height &&
748 (dx + w) <= width && (dy + h) <= height) {
749 notify = 1;
750 }
751
752 /* make to sure only copy if it's a plain copy ROP */
753 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
754 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
755 notify = 0;
756
757 /* we have to flush all pending changes so that the copy
758 is generated at the appropriate moment in time */
759 if (notify)
760 vga_hw_update();
761
b2eb849d
AJ		 762 (*s->cirrus_rop) (s, s->vram_ptr +
763 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
764 s->vram_ptr +
765 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 766 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
767 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 768
769 if (notify)
3023f332 770 qemu_console_copy(s->ds,
38334f76
AZ		 771 sx, sy, dx, dy,
772 s->cirrus_blt_width / depth,
773 s->cirrus_blt_height);
24236869
FB		 774
775 /* we don't have to notify the display that this portion has
38334f76 776 changed since qemu_console_copy implies this */
24236869 777
31c05501
AL		 778 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
779 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
780 s->cirrus_blt_height);
24236869
FB		 781}
782
783static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
784{
65d35a09
AJ		 785 if (BLTUNSAFE(s))
786 return 0;
787
7d957bd8
AL		 788 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
789 s->cirrus_blt_srcaddr - s->start_addr,
790 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 791
e6e5ad80
FB		 792 return 1;
793}
794
795/***************************************
796 *
797 * bitblt (cpu-to-video)
798 *
799 ***************************************/
800
e6e5ad80
FB		 801static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
802{
803 int copy_count;
a5082316 804 uint8_t *end_ptr;
3b46e624 805
e6e5ad80 806 if (s->cirrus_srccounter > 0) {
a5082316
FB		 807 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
808 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
809 the_end:
810 s->cirrus_srccounter = 0;
811 cirrus_bitblt_reset(s);
812 } else {
813 /* at least one scan line */
814 do {
b2eb849d
AJ		 815 (*s->cirrus_rop)(s, s->vram_ptr +
816 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
817 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 818 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
819 s->cirrus_blt_width, 1);
820 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
821 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
822 if (s->cirrus_srccounter <= 0)
823 goto the_end;
824 /* more bytes than needed can be transfered because of
825 word alignment, so we keep them for the next line */
826 /* XXX: keep alignment to speed up transfer */
827 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
828 copy_count = s->cirrus_srcptr_end - end_ptr;
829 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
830 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
831 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
832 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
833 }
e6e5ad80
FB		 834 }
835}
836
837/***************************************
838 *
839 * bitblt wrapper
840 *
841 ***************************************/
842
843static void cirrus_bitblt_reset(CirrusVGAState * s)
844{
f8b237af
AL		 845 int need_update;
846
e6e5ad80
FB		 847 s->gr[0x31] &=
848 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 849 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
850 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 851 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
852 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
853 s->cirrus_srccounter = 0;
f8b237af
AL		 854 if (!need_update)
855 return;
8926b517 856 cirrus_update_memory_access(s);
e6e5ad80
FB		 857}
858
859static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
860{
a5082316
FB		 861 int w;
862
e6e5ad80
FB		 863 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
864 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
865 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
866
867 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
868 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 869 s->cirrus_blt_srcpitch = 8;
e6e5ad80 870 } else {
b30d4608 871 /* XXX: check for 24 bpp */
a5082316 872 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 873 }
a5082316 874 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 875 } else {
876 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 877 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 878 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 879 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
880 else
881 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 882 } else {
c9c0eae8
FB		 883 /* always align input size to 32 bits */
884 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 885 }
a5082316 886 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 887 }
a5082316
FB		 888 s->cirrus_srcptr = s->cirrus_bltbuf;
889 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 890 cirrus_update_memory_access(s);
e6e5ad80
FB		 891 return 1;
892}
893
894static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
895{
896 /* XXX */
a5082316 897#ifdef DEBUG_BITBLT
e6e5ad80
FB		 898 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
899#endif
900 return 0;
901}
902
903static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
904{
905 int ret;
906
907 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
908 ret = cirrus_bitblt_videotovideo_patterncopy(s);
909 } else {
910 ret = cirrus_bitblt_videotovideo_copy(s);
911 }
e6e5ad80
FB		 912 if (ret)
913 cirrus_bitblt_reset(s);
914 return ret;
915}
916
917static void cirrus_bitblt_start(CirrusVGAState * s)
918{
919 uint8_t blt_rop;
920
a5082316
FB		 921 s->gr[0x31] |= CIRRUS_BLT_BUSY;
922
e6e5ad80
FB		 923 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
924 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
925 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
926 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
927 s->cirrus_blt_dstaddr =
928 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
929 s->cirrus_blt_srcaddr =
930 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
931 s->cirrus_blt_mode = s->gr[0x30];
a5082316 932 s->cirrus_blt_modeext = s->gr[0x33];
e6e5ad80
FB		 933 blt_rop = s->gr[0x32];
934
a21ae81d 935#ifdef DEBUG_BITBLT
0b74ed78 936 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 937 blt_rop,
a21ae81d 938 s->cirrus_blt_mode,
a5082316 939 s->cirrus_blt_modeext,
a21ae81d
FB		 940 s->cirrus_blt_width,
941 s->cirrus_blt_height,
942 s->cirrus_blt_dstpitch,
943 s->cirrus_blt_srcpitch,
944 s->cirrus_blt_dstaddr,
a5082316 945 s->cirrus_blt_srcaddr,
e3a4e4b6 946 s->gr[0x2f]);
a21ae81d
FB		 947#endif
948
e6e5ad80
FB		 949 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
950 case CIRRUS_BLTMODE_PIXELWIDTH8:
951 s->cirrus_blt_pixelwidth = 1;
952 break;
953 case CIRRUS_BLTMODE_PIXELWIDTH16:
954 s->cirrus_blt_pixelwidth = 2;
955 break;
956 case CIRRUS_BLTMODE_PIXELWIDTH24:
957 s->cirrus_blt_pixelwidth = 3;
958 break;
959 case CIRRUS_BLTMODE_PIXELWIDTH32:
960 s->cirrus_blt_pixelwidth = 4;
961 break;
962 default:
a5082316 963#ifdef DEBUG_BITBLT
e6e5ad80
FB		 964 printf("cirrus: bitblt - pixel width is unknown\n");
965#endif
966 goto bitblt_ignore;
967 }
968 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
969
970 if ((s->
971 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
972 CIRRUS_BLTMODE_MEMSYSDEST))
973 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 974#ifdef DEBUG_BITBLT
e6e5ad80
FB		 975 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
976#endif
977 goto bitblt_ignore;
978 }
979
a5082316 980 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 981 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 982 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 983 CIRRUS_BLTMODE_PATTERNCOPY |
984 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 985 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 986 cirrus_bitblt_fgcol(s);
987 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 988 } else {
5fafdf24
TS		 989 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
990 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 991 CIRRUS_BLTMODE_COLOREXPAND) {
992
993 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 994 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 995 cirrus_bitblt_bgcol(s);
b30d4608 996 else
4c8732d7 997 cirrus_bitblt_fgcol(s);
b30d4608 998 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 999 } else {
1000 cirrus_bitblt_fgcol(s);
1001 cirrus_bitblt_bgcol(s);
1002 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1003 }
e69390ce 1004 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 1005 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1006 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1007 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1008 cirrus_bitblt_bgcol(s);
1009 else
1010 cirrus_bitblt_fgcol(s);
1011 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1012 } else {
1013 cirrus_bitblt_fgcol(s);
1014 cirrus_bitblt_bgcol(s);
1015 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1016 }
1017 } else {
1018 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1019 }
a21ae81d 1020 } else {
96cf2df8
TS		 1021 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1022 if (s->cirrus_blt_pixelwidth > 2) {
1023 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1024 goto bitblt_ignore;
1025 }
1026 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1027 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1028 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1029 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030 } else {
1031 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1032 }
1033 } else {
1034 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1035 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1036 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1037 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1038 } else {
1039 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1040 }
1041 }
1042 }
a21ae81d
FB		 1043 // setup bitblt engine.
1044 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1045 if (!cirrus_bitblt_cputovideo(s))
1046 goto bitblt_ignore;
1047 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1048 if (!cirrus_bitblt_videotocpu(s))
1049 goto bitblt_ignore;
1050 } else {
1051 if (!cirrus_bitblt_videotovideo(s))
1052 goto bitblt_ignore;
1053 }
e6e5ad80 1054 }
e6e5ad80
FB		 1055 return;
1056 bitblt_ignore:;
1057 cirrus_bitblt_reset(s);
1058}
1059
1060static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1061{
1062 unsigned old_value;
1063
1064 old_value = s->gr[0x31];
1065 s->gr[0x31] = reg_value;
1066
1067 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1068 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1069 cirrus_bitblt_reset(s);
1070 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1071 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1072 cirrus_bitblt_start(s);
1073 }
1074}
1075
1076
1077/***************************************
1078 *
1079 * basic parameters
1080 *
1081 ***************************************/
1082
5fafdf24 1083static void cirrus_get_offsets(VGAState *s1,
83acc96b
FB		 1084 uint32_t *pline_offset,
1085 uint32_t *pstart_addr,
1086 uint32_t *pline_compare)
e6e5ad80
FB		 1087{
1088 CirrusVGAState * s = (CirrusVGAState *)s1;
83acc96b 1089 uint32_t start_addr, line_offset, line_compare;
e6e5ad80
FB		 1090
1091 line_offset = s->cr[0x13]
e36f36e1 1092 | ((s->cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1093 line_offset <<= 3;
1094 *pline_offset = line_offset;
1095
1096 start_addr = (s->cr[0x0c] << 8)
1097 | s->cr[0x0d]
1098 | ((s->cr[0x1b] & 0x01) << 16)
1099 | ((s->cr[0x1b] & 0x0c) << 15)
1100 | ((s->cr[0x1d] & 0x80) << 12);
1101 *pstart_addr = start_addr;
83acc96b 1102
5fafdf24 1103 line_compare = s->cr[0x18] |
83acc96b
FB		 1104 ((s->cr[0x07] & 0x10) << 4) |
1105 ((s->cr[0x09] & 0x40) << 3);
1106 *pline_compare = line_compare;
e6e5ad80
FB		 1107}
1108
1109static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1110{
1111 uint32_t ret = 16;
1112
1113 switch (s->cirrus_hidden_dac_data & 0xf) {
1114 case 0:
1115 ret = 15;
1116 break; /* Sierra HiColor */
1117 case 1:
1118 ret = 16;
1119 break; /* XGA HiColor */
1120 default:
1121#ifdef DEBUG_CIRRUS
1122 printf("cirrus: invalid DAC value %x in 16bpp\n",
1123 (s->cirrus_hidden_dac_data & 0xf));
1124#endif
1125 ret = 15; /* XXX */
1126 break;
1127 }
1128 return ret;
1129}
1130
1131static int cirrus_get_bpp(VGAState *s1)
1132{
1133 CirrusVGAState * s = (CirrusVGAState *)s1;
1134 uint32_t ret = 8;
1135
1136 if ((s->sr[0x07] & 0x01) != 0) {
1137 /* Cirrus SVGA */
1138 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1139 case CIRRUS_SR7_BPP_8:
1140 ret = 8;
1141 break;
1142 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1143 ret = cirrus_get_bpp16_depth(s);
1144 break;
1145 case CIRRUS_SR7_BPP_24:
1146 ret = 24;
1147 break;
1148 case CIRRUS_SR7_BPP_16:
1149 ret = cirrus_get_bpp16_depth(s);
1150 break;
1151 case CIRRUS_SR7_BPP_32:
1152 ret = 32;
1153 break;
1154 default:
1155#ifdef DEBUG_CIRRUS
1156 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1157#endif
1158 ret = 8;
1159 break;
1160 }
1161 } else {
1162 /* VGA */
aeb3c85f 1163 ret = 0;
e6e5ad80
FB		 1164 }
1165
1166 return ret;
1167}
1168
78e127ef
FB		 1169static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1170{
1171 int width, height;
3b46e624 1172
78e127ef 1173 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1174 height = s->cr[0x12] |
1175 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1176 ((s->cr[0x07] & 0x40) << 3);
1177 height = (height + 1);
1178 /* interlace support */
1179 if (s->cr[0x1a] & 0x01)
1180 height = height * 2;
1181 *pwidth = width;
1182 *pheight = height;
1183}
1184
e6e5ad80
FB		 1185/***************************************
1186 *
1187 * bank memory
1188 *
1189 ***************************************/
1190
1191static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1192{
1193 unsigned offset;
1194 unsigned limit;
1195
1196 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1197 offset = s->gr[0x09 + bank_index];
1198 else /* single bank */
1199 offset = s->gr[0x09];
1200
1201 if ((s->gr[0x0b] & 0x20) != 0)
1202 offset <<= 14;
1203 else
1204 offset <<= 12;
1205
e3a4e4b6 1206 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1207 limit = 0;
1208 else
e3a4e4b6 1209 limit = s->real_vram_size - offset;
e6e5ad80
FB		 1210
1211 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1212 if (limit > 0x8000) {
1213 offset += 0x8000;
1214 limit -= 0x8000;
1215 } else {
1216 limit = 0;
1217 }
1218 }
1219
1220 if (limit > 0) {
2bec46dc
AL		 1221 /* Thinking about changing bank base? First, drop the dirty bitmap information
1222 * on the current location, otherwise we lose this pointer forever */
1223 if (s->lfb_vram_mapped) {
1224 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1225 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1226 }
e6e5ad80
FB		 1227 s->cirrus_bank_base[bank_index] = offset;
1228 s->cirrus_bank_limit[bank_index] = limit;
1229 } else {
1230 s->cirrus_bank_base[bank_index] = 0;
1231 s->cirrus_bank_limit[bank_index] = 0;
1232 }
1233}
1234
1235/***************************************
1236 *
1237 * I/O access between 0x3c4-0x3c5
1238 *
1239 ***************************************/
1240
1241static int
1242cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1243{
1244 switch (reg_index) {
1245 case 0x00: // Standard VGA
1246 case 0x01: // Standard VGA
1247 case 0x02: // Standard VGA
1248 case 0x03: // Standard VGA
1249 case 0x04: // Standard VGA
1250 return CIRRUS_HOOK_NOT_HANDLED;
1251 case 0x06: // Unlock Cirrus extensions
1252 *reg_value = s->sr[reg_index];
1253 break;
e6e5ad80
FB		 1254 case 0x10:
1255 case 0x30:
1256 case 0x50:
1257 case 0x70: // Graphics Cursor X
1258 case 0x90:
1259 case 0xb0:
1260 case 0xd0:
1261 case 0xf0: // Graphics Cursor X
aeb3c85f
FB		 1262 *reg_value = s->sr[0x10];
1263 break;
e6e5ad80
FB		 1264 case 0x11:
1265 case 0x31:
1266 case 0x51:
1267 case 0x71: // Graphics Cursor Y
1268 case 0x91:
1269 case 0xb1:
1270 case 0xd1:
a5082316 1271 case 0xf1: // Graphics Cursor Y
aeb3c85f
FB		 1272 *reg_value = s->sr[0x11];
1273 break;
1274 case 0x05: // ???
1275 case 0x07: // Extended Sequencer Mode
1276 case 0x08: // EEPROM Control
1277 case 0x09: // Scratch Register 0
1278 case 0x0a: // Scratch Register 1
1279 case 0x0b: // VCLK 0
1280 case 0x0c: // VCLK 1
1281 case 0x0d: // VCLK 2
1282 case 0x0e: // VCLK 3
1283 case 0x0f: // DRAM Control
e6e5ad80
FB		 1284 case 0x12: // Graphics Cursor Attribute
1285 case 0x13: // Graphics Cursor Pattern Address
1286 case 0x14: // Scratch Register 2
1287 case 0x15: // Scratch Register 3
1288 case 0x16: // Performance Tuning Register
1289 case 0x17: // Configuration Readback and Extended Control
1290 case 0x18: // Signature Generator Control
1291 case 0x19: // Signal Generator Result
1292 case 0x1a: // Signal Generator Result
1293 case 0x1b: // VCLK 0 Denominator & Post
1294 case 0x1c: // VCLK 1 Denominator & Post
1295 case 0x1d: // VCLK 2 Denominator & Post
1296 case 0x1e: // VCLK 3 Denominator & Post
1297 case 0x1f: // BIOS Write Enable and MCLK select
1298#ifdef DEBUG_CIRRUS
1299 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1300#endif
1301 *reg_value = s->sr[reg_index];
1302 break;
1303 default:
1304#ifdef DEBUG_CIRRUS
1305 printf("cirrus: inport sr_index %02x\n", reg_index);
1306#endif
1307 *reg_value = 0xff;
1308 break;
1309 }
1310
1311 return CIRRUS_HOOK_HANDLED;
1312}
1313
1314static int
1315cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1316{
1317 switch (reg_index) {
1318 case 0x00: // Standard VGA
1319 case 0x01: // Standard VGA
1320 case 0x02: // Standard VGA
1321 case 0x03: // Standard VGA
1322 case 0x04: // Standard VGA
1323 return CIRRUS_HOOK_NOT_HANDLED;
1324 case 0x06: // Unlock Cirrus extensions
1325 reg_value &= 0x17;
1326 if (reg_value == 0x12) {
1327 s->sr[reg_index] = 0x12;
1328 } else {
1329 s->sr[reg_index] = 0x0f;
1330 }
1331 break;
1332 case 0x10:
1333 case 0x30:
1334 case 0x50:
1335 case 0x70: // Graphics Cursor X
1336 case 0x90:
1337 case 0xb0:
1338 case 0xd0:
1339 case 0xf0: // Graphics Cursor X
1340 s->sr[0x10] = reg_value;
a5082316 1341 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1342 break;
1343 case 0x11:
1344 case 0x31:
1345 case 0x51:
1346 case 0x71: // Graphics Cursor Y
1347 case 0x91:
1348 case 0xb1:
1349 case 0xd1:
1350 case 0xf1: // Graphics Cursor Y
1351 s->sr[0x11] = reg_value;
a5082316 1352 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1353 break;
1354 case 0x07: // Extended Sequencer Mode
2bec46dc 1355 cirrus_update_memory_access(s);
e6e5ad80
FB		 1356 case 0x08: // EEPROM Control
1357 case 0x09: // Scratch Register 0
1358 case 0x0a: // Scratch Register 1
1359 case 0x0b: // VCLK 0
1360 case 0x0c: // VCLK 1
1361 case 0x0d: // VCLK 2
1362 case 0x0e: // VCLK 3
1363 case 0x0f: // DRAM Control
1364 case 0x12: // Graphics Cursor Attribute
1365 case 0x13: // Graphics Cursor Pattern Address
1366 case 0x14: // Scratch Register 2
1367 case 0x15: // Scratch Register 3
1368 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1369 case 0x18: // Signature Generator Control
1370 case 0x19: // Signature Generator Result
1371 case 0x1a: // Signature Generator Result
1372 case 0x1b: // VCLK 0 Denominator & Post
1373 case 0x1c: // VCLK 1 Denominator & Post
1374 case 0x1d: // VCLK 2 Denominator & Post
1375 case 0x1e: // VCLK 3 Denominator & Post
1376 case 0x1f: // BIOS Write Enable and MCLK select
1377 s->sr[reg_index] = reg_value;
1378#ifdef DEBUG_CIRRUS
1379 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1380 reg_index, reg_value);
1381#endif
1382 break;
8926b517 1383 case 0x17: // Configuration Readback and Extended Control
e3a4e4b6 1384 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
8926b517
FB		 1385 cirrus_update_memory_access(s);
1386 break;
e6e5ad80
FB		 1387 default:
1388#ifdef DEBUG_CIRRUS
1389 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1390 reg_value);
1391#endif
1392 break;
1393 }
1394
1395 return CIRRUS_HOOK_HANDLED;
1396}
1397
1398/***************************************
1399 *
1400 * I/O access at 0x3c6
1401 *
1402 ***************************************/
1403
1404static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1405{
1406 *reg_value = 0xff;
a21ae81d
FB		 1407 if (++s->cirrus_hidden_dac_lockindex == 5) {
1408 *reg_value = s->cirrus_hidden_dac_data;
1409 s->cirrus_hidden_dac_lockindex = 0;
e6e5ad80
FB		 1410 }
1411}
1412
1413static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1414{
1415 if (s->cirrus_hidden_dac_lockindex == 4) {
1416 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1417#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1418 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1419#endif
1420 }
1421 s->cirrus_hidden_dac_lockindex = 0;
1422}
1423
1424/***************************************
1425 *
1426 * I/O access at 0x3c9
1427 *
1428 ***************************************/
1429
1430static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1431{
1432 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1433 return CIRRUS_HOOK_NOT_HANDLED;
a5082316
FB		 1434 *reg_value =
1435 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1436 s->dac_sub_index];
e6e5ad80
FB		 1437 if (++s->dac_sub_index == 3) {
1438 s->dac_sub_index = 0;
1439 s->dac_read_index++;
1440 }
1441 return CIRRUS_HOOK_HANDLED;
1442}
1443
1444static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1445{
1446 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1447 return CIRRUS_HOOK_NOT_HANDLED;
1448 s->dac_cache[s->dac_sub_index] = reg_value;
1449 if (++s->dac_sub_index == 3) {
a5082316
FB		 1450 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1451 s->dac_cache, 3);
1452 /* XXX update cursor */
e6e5ad80
FB		 1453 s->dac_sub_index = 0;
1454 s->dac_write_index++;
1455 }
1456 return CIRRUS_HOOK_HANDLED;
1457}
1458
1459/***************************************
1460 *
1461 * I/O access between 0x3ce-0x3cf
1462 *
1463 ***************************************/
1464
1465static int
1466cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1467{
1468 switch (reg_index) {
aeb3c85f
FB		 1469 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1470 *reg_value = s->cirrus_shadow_gr0;
1471 return CIRRUS_HOOK_HANDLED;
1472 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1473 *reg_value = s->cirrus_shadow_gr1;
1474 return CIRRUS_HOOK_HANDLED;
e6e5ad80
FB		 1475 case 0x02: // Standard VGA
1476 case 0x03: // Standard VGA
1477 case 0x04: // Standard VGA
1478 case 0x06: // Standard VGA
1479 case 0x07: // Standard VGA
1480 case 0x08: // Standard VGA
1481 return CIRRUS_HOOK_NOT_HANDLED;
1482 case 0x05: // Standard VGA, Cirrus extended mode
1483 default:
1484 break;
1485 }
1486
1487 if (reg_index < 0x3a) {
1488 *reg_value = s->gr[reg_index];
1489 } else {
1490#ifdef DEBUG_CIRRUS
1491 printf("cirrus: inport gr_index %02x\n", reg_index);
1492#endif
1493 *reg_value = 0xff;
1494 }
1495
1496 return CIRRUS_HOOK_HANDLED;
1497}
1498
1499static int
1500cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1501{
a5082316
FB		 1502#if defined(DEBUG_BITBLT) && 0
1503 printf("gr%02x: %02x\n", reg_index, reg_value);
1504#endif
e6e5ad80
FB		 1505 switch (reg_index) {
1506 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
aeb3c85f 1507 s->cirrus_shadow_gr0 = reg_value;
e6e5ad80
FB		 1508 return CIRRUS_HOOK_NOT_HANDLED;
1509 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
aeb3c85f 1510 s->cirrus_shadow_gr1 = reg_value;
e6e5ad80
FB		 1511 return CIRRUS_HOOK_NOT_HANDLED;
1512 case 0x02: // Standard VGA
1513 case 0x03: // Standard VGA
1514 case 0x04: // Standard VGA
1515 case 0x06: // Standard VGA
1516 case 0x07: // Standard VGA
1517 case 0x08: // Standard VGA
1518 return CIRRUS_HOOK_NOT_HANDLED;
1519 case 0x05: // Standard VGA, Cirrus extended mode
1520 s->gr[reg_index] = reg_value & 0x7f;
8926b517 1521 cirrus_update_memory_access(s);
e6e5ad80
FB		 1522 break;
1523 case 0x09: // bank offset #0
1524 case 0x0A: // bank offset #1
8926b517
FB		 1525 s->gr[reg_index] = reg_value;
1526 cirrus_update_bank_ptr(s, 0);
1527 cirrus_update_bank_ptr(s, 1);
2bec46dc 1528 cirrus_update_memory_access(s);
8926b517 1529 break;
e6e5ad80
FB		 1530 case 0x0B:
1531 s->gr[reg_index] = reg_value;
1532 cirrus_update_bank_ptr(s, 0);
1533 cirrus_update_bank_ptr(s, 1);
8926b517 1534 cirrus_update_memory_access(s);
e6e5ad80
FB		 1535 break;
1536 case 0x10: // BGCOLOR 0x0000ff00
1537 case 0x11: // FGCOLOR 0x0000ff00
1538 case 0x12: // BGCOLOR 0x00ff0000
1539 case 0x13: // FGCOLOR 0x00ff0000
1540 case 0x14: // BGCOLOR 0xff000000
1541 case 0x15: // FGCOLOR 0xff000000
1542 case 0x20: // BLT WIDTH 0x0000ff
1543 case 0x22: // BLT HEIGHT 0x0000ff
1544 case 0x24: // BLT DEST PITCH 0x0000ff
1545 case 0x26: // BLT SRC PITCH 0x0000ff
1546 case 0x28: // BLT DEST ADDR 0x0000ff
1547 case 0x29: // BLT DEST ADDR 0x00ff00
1548 case 0x2c: // BLT SRC ADDR 0x0000ff
1549 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1550 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1551 case 0x30: // BLT MODE
1552 case 0x32: // RASTER OP
a21ae81d 1553 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1554 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1555 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1556 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1557 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1558 s->gr[reg_index] = reg_value;
1559 break;
1560 case 0x21: // BLT WIDTH 0x001f00
1561 case 0x23: // BLT HEIGHT 0x001f00
1562 case 0x25: // BLT DEST PITCH 0x001f00
1563 case 0x27: // BLT SRC PITCH 0x001f00
1564 s->gr[reg_index] = reg_value & 0x1f;
1565 break;
1566 case 0x2a: // BLT DEST ADDR 0x3f0000
a5082316
FB		 1567 s->gr[reg_index] = reg_value & 0x3f;
1568 /* if auto start mode, starts bit blt now */
1569 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1570 cirrus_bitblt_start(s);
1571 }
1572 break;
e6e5ad80
FB		 1573 case 0x2e: // BLT SRC ADDR 0x3f0000
1574 s->gr[reg_index] = reg_value & 0x3f;
1575 break;
1576 case 0x31: // BLT STATUS/START
1577 cirrus_write_bitblt(s, reg_value);
1578 break;
1579 default:
1580#ifdef DEBUG_CIRRUS
1581 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1582 reg_value);
1583#endif
1584 break;
1585 }
1586
1587 return CIRRUS_HOOK_HANDLED;
1588}
1589
1590/***************************************
1591 *
1592 * I/O access between 0x3d4-0x3d5
1593 *
1594 ***************************************/
1595
1596static int
1597cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1598{
1599 switch (reg_index) {
1600 case 0x00: // Standard VGA
1601 case 0x01: // Standard VGA
1602 case 0x02: // Standard VGA
1603 case 0x03: // Standard VGA
1604 case 0x04: // Standard VGA
1605 case 0x05: // Standard VGA
1606 case 0x06: // Standard VGA
1607 case 0x07: // Standard VGA
1608 case 0x08: // Standard VGA
1609 case 0x09: // Standard VGA
1610 case 0x0a: // Standard VGA
1611 case 0x0b: // Standard VGA
1612 case 0x0c: // Standard VGA
1613 case 0x0d: // Standard VGA
1614 case 0x0e: // Standard VGA
1615 case 0x0f: // Standard VGA
1616 case 0x10: // Standard VGA
1617 case 0x11: // Standard VGA
1618 case 0x12: // Standard VGA
1619 case 0x13: // Standard VGA
1620 case 0x14: // Standard VGA
1621 case 0x15: // Standard VGA
1622 case 0x16: // Standard VGA
1623 case 0x17: // Standard VGA
1624 case 0x18: // Standard VGA
1625 return CIRRUS_HOOK_NOT_HANDLED;
ca896ef3
AJ		 1626 case 0x24: // Attribute Controller Toggle Readback (R)
1627 *reg_value = (s->ar_flip_flop << 7);
1628 break;
e6e5ad80
FB		 1629 case 0x19: // Interlace End
1630 case 0x1a: // Miscellaneous Control
1631 case 0x1b: // Extended Display Control
1632 case 0x1c: // Sync Adjust and Genlock
1633 case 0x1d: // Overlay Extended Control
1634 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1635 case 0x25: // Part Status
1636 case 0x27: // Part ID (R)
1637 *reg_value = s->cr[reg_index];
1638 break;
1639 case 0x26: // Attribute Controller Index Readback (R)
1640 *reg_value = s->ar_index & 0x3f;
1641 break;
1642 default:
1643#ifdef DEBUG_CIRRUS
1644 printf("cirrus: inport cr_index %02x\n", reg_index);
1645 *reg_value = 0xff;
1646#endif
1647 break;
1648 }
1649
1650 return CIRRUS_HOOK_HANDLED;
1651}
1652
1653static int
1654cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1655{
1656 switch (reg_index) {
1657 case 0x00: // Standard VGA
1658 case 0x01: // Standard VGA
1659 case 0x02: // Standard VGA
1660 case 0x03: // Standard VGA
1661 case 0x04: // Standard VGA
1662 case 0x05: // Standard VGA
1663 case 0x06: // Standard VGA
1664 case 0x07: // Standard VGA
1665 case 0x08: // Standard VGA
1666 case 0x09: // Standard VGA
1667 case 0x0a: // Standard VGA
1668 case 0x0b: // Standard VGA
1669 case 0x0c: // Standard VGA
1670 case 0x0d: // Standard VGA
1671 case 0x0e: // Standard VGA
1672 case 0x0f: // Standard VGA
1673 case 0x10: // Standard VGA
1674 case 0x11: // Standard VGA
1675 case 0x12: // Standard VGA
1676 case 0x13: // Standard VGA
1677 case 0x14: // Standard VGA
1678 case 0x15: // Standard VGA
1679 case 0x16: // Standard VGA
1680 case 0x17: // Standard VGA
1681 case 0x18: // Standard VGA
1682 return CIRRUS_HOOK_NOT_HANDLED;
1683 case 0x19: // Interlace End
1684 case 0x1a: // Miscellaneous Control
1685 case 0x1b: // Extended Display Control
1686 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1687 case 0x1d: // Overlay Extended Control
e6e5ad80
FB		 1688 s->cr[reg_index] = reg_value;
1689#ifdef DEBUG_CIRRUS
1690 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1691 reg_index, reg_value);
1692#endif
1693 break;
1694 case 0x22: // Graphics Data Latches Readback (R)
1695 case 0x24: // Attribute Controller Toggle Readback (R)
1696 case 0x26: // Attribute Controller Index Readback (R)
1697 case 0x27: // Part ID (R)
1698 break;
e6e5ad80
FB		 1699 case 0x25: // Part Status
1700 default:
1701#ifdef DEBUG_CIRRUS
1702 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1703 reg_value);
1704#endif
1705 break;
1706 }
1707
1708 return CIRRUS_HOOK_HANDLED;
1709}
1710
1711/***************************************
1712 *
1713 * memory-mapped I/O (bitblt)
1714 *
1715 ***************************************/
1716
1717static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1718{
1719 int value = 0xff;
1720
1721 switch (address) {
1722 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1723 cirrus_hook_read_gr(s, 0x00, &value);
1724 break;
1725 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1726 cirrus_hook_read_gr(s, 0x10, &value);
1727 break;
1728 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1729 cirrus_hook_read_gr(s, 0x12, &value);
1730 break;
1731 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1732 cirrus_hook_read_gr(s, 0x14, &value);
1733 break;
1734 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1735 cirrus_hook_read_gr(s, 0x01, &value);
1736 break;
1737 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1738 cirrus_hook_read_gr(s, 0x11, &value);
1739 break;
1740 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1741 cirrus_hook_read_gr(s, 0x13, &value);
1742 break;
1743 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1744 cirrus_hook_read_gr(s, 0x15, &value);
1745 break;
1746 case (CIRRUS_MMIO_BLTWIDTH + 0):
1747 cirrus_hook_read_gr(s, 0x20, &value);
1748 break;
1749 case (CIRRUS_MMIO_BLTWIDTH + 1):
1750 cirrus_hook_read_gr(s, 0x21, &value);
1751 break;
1752 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1753 cirrus_hook_read_gr(s, 0x22, &value);
1754 break;
1755 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1756 cirrus_hook_read_gr(s, 0x23, &value);
1757 break;
1758 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1759 cirrus_hook_read_gr(s, 0x24, &value);
1760 break;
1761 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1762 cirrus_hook_read_gr(s, 0x25, &value);
1763 break;
1764 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1765 cirrus_hook_read_gr(s, 0x26, &value);
1766 break;
1767 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1768 cirrus_hook_read_gr(s, 0x27, &value);
1769 break;
1770 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1771 cirrus_hook_read_gr(s, 0x28, &value);
1772 break;
1773 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1774 cirrus_hook_read_gr(s, 0x29, &value);
1775 break;
1776 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1777 cirrus_hook_read_gr(s, 0x2a, &value);
1778 break;
1779 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1780 cirrus_hook_read_gr(s, 0x2c, &value);
1781 break;
1782 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1783 cirrus_hook_read_gr(s, 0x2d, &value);
1784 break;
1785 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1786 cirrus_hook_read_gr(s, 0x2e, &value);
1787 break;
1788 case CIRRUS_MMIO_BLTWRITEMASK:
1789 cirrus_hook_read_gr(s, 0x2f, &value);
1790 break;
1791 case CIRRUS_MMIO_BLTMODE:
1792 cirrus_hook_read_gr(s, 0x30, &value);
1793 break;
1794 case CIRRUS_MMIO_BLTROP:
1795 cirrus_hook_read_gr(s, 0x32, &value);
1796 break;
a21ae81d
FB		 1797 case CIRRUS_MMIO_BLTMODEEXT:
1798 cirrus_hook_read_gr(s, 0x33, &value);
1799 break;
e6e5ad80
FB		 1800 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1801 cirrus_hook_read_gr(s, 0x34, &value);
1802 break;
1803 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1804 cirrus_hook_read_gr(s, 0x35, &value);
1805 break;
1806 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1807 cirrus_hook_read_gr(s, 0x38, &value);
1808 break;
1809 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1810 cirrus_hook_read_gr(s, 0x39, &value);
1811 break;
1812 case CIRRUS_MMIO_BLTSTATUS:
1813 cirrus_hook_read_gr(s, 0x31, &value);
1814 break;
1815 default:
1816#ifdef DEBUG_CIRRUS
1817 printf("cirrus: mmio read - address 0x%04x\n", address);
1818#endif
1819 break;
1820 }
1821
1822 return (uint8_t) value;
1823}
1824
1825static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1826 uint8_t value)
1827{
1828 switch (address) {
1829 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1830 cirrus_hook_write_gr(s, 0x00, value);
1831 break;
1832 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1833 cirrus_hook_write_gr(s, 0x10, value);
1834 break;
1835 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1836 cirrus_hook_write_gr(s, 0x12, value);
1837 break;
1838 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1839 cirrus_hook_write_gr(s, 0x14, value);
1840 break;
1841 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1842 cirrus_hook_write_gr(s, 0x01, value);
1843 break;
1844 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1845 cirrus_hook_write_gr(s, 0x11, value);
1846 break;
1847 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1848 cirrus_hook_write_gr(s, 0x13, value);
1849 break;
1850 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1851 cirrus_hook_write_gr(s, 0x15, value);
1852 break;
1853 case (CIRRUS_MMIO_BLTWIDTH + 0):
1854 cirrus_hook_write_gr(s, 0x20, value);
1855 break;
1856 case (CIRRUS_MMIO_BLTWIDTH + 1):
1857 cirrus_hook_write_gr(s, 0x21, value);
1858 break;
1859 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1860 cirrus_hook_write_gr(s, 0x22, value);
1861 break;
1862 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1863 cirrus_hook_write_gr(s, 0x23, value);
1864 break;
1865 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1866 cirrus_hook_write_gr(s, 0x24, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1869 cirrus_hook_write_gr(s, 0x25, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1872 cirrus_hook_write_gr(s, 0x26, value);
1873 break;
1874 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1875 cirrus_hook_write_gr(s, 0x27, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1878 cirrus_hook_write_gr(s, 0x28, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1881 cirrus_hook_write_gr(s, 0x29, value);
1882 break;
1883 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1884 cirrus_hook_write_gr(s, 0x2a, value);
1885 break;
1886 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1887 /* ignored */
1888 break;
1889 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1890 cirrus_hook_write_gr(s, 0x2c, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1893 cirrus_hook_write_gr(s, 0x2d, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1896 cirrus_hook_write_gr(s, 0x2e, value);
1897 break;
1898 case CIRRUS_MMIO_BLTWRITEMASK:
1899 cirrus_hook_write_gr(s, 0x2f, value);
1900 break;
1901 case CIRRUS_MMIO_BLTMODE:
1902 cirrus_hook_write_gr(s, 0x30, value);
1903 break;
1904 case CIRRUS_MMIO_BLTROP:
1905 cirrus_hook_write_gr(s, 0x32, value);
1906 break;
a21ae81d
FB		 1907 case CIRRUS_MMIO_BLTMODEEXT:
1908 cirrus_hook_write_gr(s, 0x33, value);
1909 break;
e6e5ad80
FB		 1910 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1911 cirrus_hook_write_gr(s, 0x34, value);
1912 break;
1913 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1914 cirrus_hook_write_gr(s, 0x35, value);
1915 break;
1916 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1917 cirrus_hook_write_gr(s, 0x38, value);
1918 break;
1919 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1920 cirrus_hook_write_gr(s, 0x39, value);
1921 break;
1922 case CIRRUS_MMIO_BLTSTATUS:
1923 cirrus_hook_write_gr(s, 0x31, value);
1924 break;
1925 default:
1926#ifdef DEBUG_CIRRUS
1927 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1928 address, value);
1929#endif
1930 break;
1931 }
1932}
1933
e6e5ad80
FB		 1934/***************************************
1935 *
1936 * write mode 4/5
1937 *
1938 * assume TARGET_PAGE_SIZE >= 16
1939 *
1940 ***************************************/
1941
1942static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1943 unsigned mode,
1944 unsigned offset,
1945 uint32_t mem_value)
1946{
1947 int x;
1948 unsigned val = mem_value;
1949 uint8_t *dst;
1950
b2eb849d 1951 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1952 for (x = 0; x < 8; x++) {
1953 if (val & 0x80) {
0b74ed78 1954 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1955 } else if (mode == 5) {
0b74ed78 1956 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1957 }
1958 val <<= 1;
0b74ed78 1959 dst++;
e6e5ad80
FB		 1960 }
1961 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1962 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1963}
1964
1965static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1966 unsigned mode,
1967 unsigned offset,
1968 uint32_t mem_value)
1969{
1970 int x;
1971 unsigned val = mem_value;
1972 uint8_t *dst;
1973
b2eb849d 1974 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1975 for (x = 0; x < 8; x++) {
1976 if (val & 0x80) {
0b74ed78
FB		 1977 *dst = s->cirrus_shadow_gr1;
1978 *(dst + 1) = s->gr[0x11];
e6e5ad80 1979 } else if (mode == 5) {
0b74ed78
FB		 1980 *dst = s->cirrus_shadow_gr0;
1981 *(dst + 1) = s->gr[0x10];
e6e5ad80
FB		 1982 }
1983 val <<= 1;
0b74ed78 1984 dst += 2;
e6e5ad80
FB		 1985 }
1986 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1987 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1988}
1989
1990/***************************************
1991 *
1992 * memory access between 0xa0000-0xbffff
1993 *
1994 ***************************************/
1995
1996static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1997{
1998 CirrusVGAState *s = opaque;
1999 unsigned bank_index;
2000 unsigned bank_offset;
2001 uint32_t val;
2002
2003 if ((s->sr[0x07] & 0x01) == 0) {
2004 return vga_mem_readb(s, addr);
2005 }
2006
aeb3c85f
FB		 2007 addr &= 0x1ffff;
2008
e6e5ad80
FB		 2009 if (addr < 0x10000) {
2010 /* XXX handle bitblt */
2011 /* video memory */
2012 bank_index = addr >> 15;
2013 bank_offset = addr & 0x7fff;
2014 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2015 bank_offset += s->cirrus_bank_base[bank_index];
2016 if ((s->gr[0x0B] & 0x14) == 0x14) {
2017 bank_offset <<= 4;
2018 } else if (s->gr[0x0B] & 0x02) {
2019 bank_offset <<= 3;
2020 }
2021 bank_offset &= s->cirrus_addr_mask;
2022 val = *(s->vram_ptr + bank_offset);
2023 } else
2024 val = 0xff;
2025 } else if (addr >= 0x18000 && addr < 0x18100) {
2026 /* memory-mapped I/O */
2027 val = 0xff;
2028 if ((s->sr[0x17] & 0x44) == 0x04) {
2029 val = cirrus_mmio_blt_read(s, addr & 0xff);
2030 }
2031 } else {
2032 val = 0xff;
2033#ifdef DEBUG_CIRRUS
2034 printf("cirrus: mem_readb %06x\n", addr);
2035#endif
2036 }
2037 return val;
2038}
2039
2040static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2041{
2042 uint32_t v;
2043#ifdef TARGET_WORDS_BIGENDIAN
2044 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2045 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2046#else
2047 v = cirrus_vga_mem_readb(opaque, addr);
2048 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2049#endif
2050 return v;
2051}
2052
2053static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2054{
2055 uint32_t v;
2056#ifdef TARGET_WORDS_BIGENDIAN
2057 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2058 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2059 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2060 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2061#else
2062 v = cirrus_vga_mem_readb(opaque, addr);
2063 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2064 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2065 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2066#endif
2067 return v;
2068}
2069
5fafdf24 2070static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2071 uint32_t mem_value)
2072{
2073 CirrusVGAState *s = opaque;
2074 unsigned bank_index;
2075 unsigned bank_offset;
2076 unsigned mode;
2077
2078 if ((s->sr[0x07] & 0x01) == 0) {
2079 vga_mem_writeb(s, addr, mem_value);
2080 return;
2081 }
2082
aeb3c85f
FB		 2083 addr &= 0x1ffff;
2084
e6e5ad80
FB		 2085 if (addr < 0x10000) {
2086 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2087 /* bitblt */
2088 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2089 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2090 cirrus_bitblt_cputovideo_next(s);
2091 }
2092 } else {
2093 /* video memory */
2094 bank_index = addr >> 15;
2095 bank_offset = addr & 0x7fff;
2096 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2097 bank_offset += s->cirrus_bank_base[bank_index];
2098 if ((s->gr[0x0B] & 0x14) == 0x14) {
2099 bank_offset <<= 4;
2100 } else if (s->gr[0x0B] & 0x02) {
2101 bank_offset <<= 3;
2102 }
2103 bank_offset &= s->cirrus_addr_mask;
2104 mode = s->gr[0x05] & 0x7;
2105 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2106 *(s->vram_ptr + bank_offset) = mem_value;
2107 cpu_physical_memory_set_dirty(s->vram_offset +
2108 bank_offset);
2109 } else {
2110 if ((s->gr[0x0B] & 0x14) != 0x14) {
2111 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2112 bank_offset,
2113 mem_value);
2114 } else {
2115 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2116 bank_offset,
2117 mem_value);
2118 }
2119 }
2120 }
2121 }
2122 } else if (addr >= 0x18000 && addr < 0x18100) {
2123 /* memory-mapped I/O */
2124 if ((s->sr[0x17] & 0x44) == 0x04) {
2125 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2126 }
2127 } else {
2128#ifdef DEBUG_CIRRUS
2129 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2130#endif
2131 }
2132}
2133
2134static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2135{
2136#ifdef TARGET_WORDS_BIGENDIAN
2137 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2138 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2139#else
2140 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2141 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2142#endif
2143}
2144
2145static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2146{
2147#ifdef TARGET_WORDS_BIGENDIAN
2148 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2149 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2150 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2151 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2152#else
2153 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2154 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2155 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2156 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2157#endif
2158}
2159
2160static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2161 cirrus_vga_mem_readb,
2162 cirrus_vga_mem_readw,
2163 cirrus_vga_mem_readl,
2164};
2165
2166static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2167 cirrus_vga_mem_writeb,
2168 cirrus_vga_mem_writew,
2169 cirrus_vga_mem_writel,
2170};
2171
a5082316
FB		 2172/***************************************
2173 *
2174 * hardware cursor
2175 *
2176 ***************************************/
2177
2178static inline void invalidate_cursor1(CirrusVGAState *s)
2179{
2180 if (s->last_hw_cursor_size) {
5fafdf24 2181 vga_invalidate_scanlines((VGAState *)s,
a5082316
FB		 2182 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2183 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2184 }
2185}
2186
2187static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2188{
2189 const uint8_t *src;
2190 uint32_t content;
2191 int y, y_min, y_max;
2192
78e127ef 2193 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2194 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2195 src += (s->sr[0x13] & 0x3c) * 256;
2196 y_min = 64;
2197 y_max = -1;
2198 for(y = 0; y < 64; y++) {
2199 content = ((uint32_t *)src)[0] |
2200 ((uint32_t *)src)[1] |
2201 ((uint32_t *)src)[2] |
2202 ((uint32_t *)src)[3];
2203 if (content) {
2204 if (y < y_min)
2205 y_min = y;
2206 if (y > y_max)
2207 y_max = y;
2208 }
2209 src += 16;
2210 }
2211 } else {
2212 src += (s->sr[0x13] & 0x3f) * 256;
2213 y_min = 32;
2214 y_max = -1;
2215 for(y = 0; y < 32; y++) {
2216 content = ((uint32_t *)src)[0] |
2217 ((uint32_t *)(src + 128))[0];
2218 if (content) {
2219 if (y < y_min)
2220 y_min = y;
2221 if (y > y_max)
2222 y_max = y;
2223 }
2224 src += 4;
2225 }
2226 }
2227 if (y_min > y_max) {
2228 s->last_hw_cursor_y_start = 0;
2229 s->last_hw_cursor_y_end = 0;
2230 } else {
2231 s->last_hw_cursor_y_start = y_min;
2232 s->last_hw_cursor_y_end = y_max + 1;
2233 }
2234}
2235
2236/* NOTE: we do not currently handle the cursor bitmap change, so we
2237 update the cursor only if it moves. */
2238static void cirrus_cursor_invalidate(VGAState *s1)
2239{
2240 CirrusVGAState *s = (CirrusVGAState *)s1;
2241 int size;
2242
70c14705 2243 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2244 size = 0;
2245 } else {
2246 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2247 size = 64;
2248 else
2249 size = 32;
2250 }
2251 /* invalidate last cursor and new cursor if any change */
2252 if (s->last_hw_cursor_size != size ||
2253 s->last_hw_cursor_x != s->hw_cursor_x ||
2254 s->last_hw_cursor_y != s->hw_cursor_y) {
2255
2256 invalidate_cursor1(s);
3b46e624 2257
a5082316
FB		 2258 s->last_hw_cursor_size = size;
2259 s->last_hw_cursor_x = s->hw_cursor_x;
2260 s->last_hw_cursor_y = s->hw_cursor_y;
2261 /* compute the real cursor min and max y */
2262 cirrus_cursor_compute_yrange(s);
2263 invalidate_cursor1(s);
2264 }
2265}
2266
2267static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2268{
2269 CirrusVGAState *s = (CirrusVGAState *)s1;
2270 int w, h, bpp, x1, x2, poffset;
2271 unsigned int color0, color1;
2272 const uint8_t *palette, *src;
2273 uint32_t content;
3b46e624 2274
5fafdf24 2275 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2276 return;
2277 /* fast test to see if the cursor intersects with the scan line */
2278 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2279 h = 64;
2280 } else {
2281 h = 32;
2282 }
2283 if (scr_y < s->hw_cursor_y ||
2284 scr_y >= (s->hw_cursor_y + h))
2285 return;
3b46e624 2286
78e127ef 2287 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2288 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2289 src += (s->sr[0x13] & 0x3c) * 256;
2290 src += (scr_y - s->hw_cursor_y) * 16;
2291 poffset = 8;
2292 content = ((uint32_t *)src)[0] |
2293 ((uint32_t *)src)[1] |
2294 ((uint32_t *)src)[2] |
2295 ((uint32_t *)src)[3];
2296 } else {
2297 src += (s->sr[0x13] & 0x3f) * 256;
2298 src += (scr_y - s->hw_cursor_y) * 4;
2299 poffset = 128;
2300 content = ((uint32_t *)src)[0] |
2301 ((uint32_t *)(src + 128))[0];
2302 }
2303 /* if nothing to draw, no need to continue */
2304 if (!content)
2305 return;
2306 w = h;
2307
2308 x1 = s->hw_cursor_x;
2309 if (x1 >= s->last_scr_width)
2310 return;
2311 x2 = s->hw_cursor_x + w;
2312 if (x2 > s->last_scr_width)
2313 x2 = s->last_scr_width;
2314 w = x2 - x1;
2315 palette = s->cirrus_hidden_palette;
5fafdf24
TS		 2316 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2317 c6_to_8(palette[0x0 * 3 + 1]),
a5082316 2318 c6_to_8(palette[0x0 * 3 + 2]));
5fafdf24
TS		 2319 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2320 c6_to_8(palette[0xf * 3 + 1]),
a5082316 2321 c6_to_8(palette[0xf * 3 + 2]));
0e1f5a0c 2322 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
a5082316 2323 d1 += x1 * bpp;
0e1f5a0c 2324 switch(ds_get_bits_per_pixel(s->ds)) {
a5082316
FB		 2325 default:
2326 break;
2327 case 8:
2328 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2329 break;
2330 case 15:
2331 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2332 break;
2333 case 16:
2334 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2335 break;
2336 case 32:
2337 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2338 break;
2339 }
2340}
2341
e6e5ad80
FB		 2342/***************************************
2343 *
2344 * LFB memory access
2345 *
2346 ***************************************/
2347
2348static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2349{
2350 CirrusVGAState *s = (CirrusVGAState *) opaque;
2351 uint32_t ret;
2352
e6e5ad80
FB		 2353 addr &= s->cirrus_addr_mask;
2354
5fafdf24 2355 if (((s->sr[0x17] & 0x44) == 0x44) &&
78e127ef 2356 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2357 /* memory-mapped I/O */
2358 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2359 } else if (0) {
2360 /* XXX handle bitblt */
2361 ret = 0xff;
2362 } else {
2363 /* video memory */
2364 if ((s->gr[0x0B] & 0x14) == 0x14) {
2365 addr <<= 4;
2366 } else if (s->gr[0x0B] & 0x02) {
2367 addr <<= 3;
2368 }
2369 addr &= s->cirrus_addr_mask;
2370 ret = *(s->vram_ptr + addr);
2371 }
2372
2373 return ret;
2374}
2375
2376static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2377{
2378 uint32_t v;
2379#ifdef TARGET_WORDS_BIGENDIAN
2380 v = cirrus_linear_readb(opaque, addr) << 8;
2381 v |= cirrus_linear_readb(opaque, addr + 1);
2382#else
2383 v = cirrus_linear_readb(opaque, addr);
2384 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2385#endif
2386 return v;
2387}
2388
2389static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2390{
2391 uint32_t v;
2392#ifdef TARGET_WORDS_BIGENDIAN
2393 v = cirrus_linear_readb(opaque, addr) << 24;
2394 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2395 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2396 v |= cirrus_linear_readb(opaque, addr + 3);
2397#else
2398 v = cirrus_linear_readb(opaque, addr);
2399 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2400 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2401 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2402#endif
2403 return v;
2404}
2405
2406static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2407 uint32_t val)
2408{
2409 CirrusVGAState *s = (CirrusVGAState *) opaque;
2410 unsigned mode;
2411
2412 addr &= s->cirrus_addr_mask;
3b46e624 2413
5fafdf24 2414 if (((s->sr[0x17] & 0x44) == 0x44) &&
78e127ef 2415 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2416 /* memory-mapped I/O */
2417 cirrus_mmio_blt_write(s, addr & 0xff, val);
2418 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2419 /* bitblt */
2420 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2421 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2422 cirrus_bitblt_cputovideo_next(s);
2423 }
2424 } else {
2425 /* video memory */
2426 if ((s->gr[0x0B] & 0x14) == 0x14) {
2427 addr <<= 4;
2428 } else if (s->gr[0x0B] & 0x02) {
2429 addr <<= 3;
2430 }
2431 addr &= s->cirrus_addr_mask;
2432
2433 mode = s->gr[0x05] & 0x7;
2434 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2435 *(s->vram_ptr + addr) = (uint8_t) val;
2436 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2437 } else {
2438 if ((s->gr[0x0B] & 0x14) != 0x14) {
2439 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2440 } else {
2441 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2442 }
2443 }
2444 }
2445}
2446
2447static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2448 uint32_t val)
2449{
2450#ifdef TARGET_WORDS_BIGENDIAN
2451 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2452 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2453#else
2454 cirrus_linear_writeb(opaque, addr, val & 0xff);
2455 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2456#endif
2457}
2458
2459static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2460 uint32_t val)
2461{
2462#ifdef TARGET_WORDS_BIGENDIAN
2463 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2464 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2465 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2467#else
2468 cirrus_linear_writeb(opaque, addr, val & 0xff);
2469 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2470 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2471 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2472#endif
2473}
2474
2475
2476static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2477 cirrus_linear_readb,
2478 cirrus_linear_readw,
2479 cirrus_linear_readl,
2480};
2481
2482static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2483 cirrus_linear_writeb,
2484 cirrus_linear_writew,
2485 cirrus_linear_writel,
2486};
2487
8926b517
FB		 2488static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2489 uint32_t val)
2490{
2491 CirrusVGAState *s = (CirrusVGAState *) opaque;
2492
2493 addr &= s->cirrus_addr_mask;
2494 *(s->vram_ptr + addr) = val;
2495 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2496}
2497
2498static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2499 uint32_t val)
2500{
2501 CirrusVGAState *s = (CirrusVGAState *) opaque;
2502
2503 addr &= s->cirrus_addr_mask;
2504 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2505 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2506}
2507
2508static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2509 uint32_t val)
2510{
2511 CirrusVGAState *s = (CirrusVGAState *) opaque;
2512
2513 addr &= s->cirrus_addr_mask;
2514 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2515 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2516}
2517
a5082316
FB		 2518/***************************************
2519 *
2520 * system to screen memory access
2521 *
2522 ***************************************/
2523
2524
2525static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2526{
2527 uint32_t ret;
2528
2529 /* XXX handle bitblt */
2530 ret = 0xff;
2531 return ret;
2532}
2533
2534static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2535{
2536 uint32_t v;
2537#ifdef TARGET_WORDS_BIGENDIAN
2538 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2539 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2540#else
2541 v = cirrus_linear_bitblt_readb(opaque, addr);
2542 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2543#endif
2544 return v;
2545}
2546
2547static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2548{
2549 uint32_t v;
2550#ifdef TARGET_WORDS_BIGENDIAN
2551 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2552 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2553 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2554 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2555#else
2556 v = cirrus_linear_bitblt_readb(opaque, addr);
2557 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2558 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2559 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2560#endif
2561 return v;
2562}
2563
2564static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2565 uint32_t val)
2566{
2567 CirrusVGAState *s = (CirrusVGAState *) opaque;
2568
2569 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2570 /* bitblt */
2571 *s->cirrus_srcptr++ = (uint8_t) val;
2572 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2573 cirrus_bitblt_cputovideo_next(s);
2574 }
2575 }
2576}
2577
2578static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2579 uint32_t val)
2580{
2581#ifdef TARGET_WORDS_BIGENDIAN
2582 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2583 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2584#else
2585 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2586 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2587#endif
2588}
2589
2590static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2591 uint32_t val)
2592{
2593#ifdef TARGET_WORDS_BIGENDIAN
2594 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2595 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2596 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2598#else
2599 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2600 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2601 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2602 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2603#endif
2604}
2605
2606
2607static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2608 cirrus_linear_bitblt_readb,
2609 cirrus_linear_bitblt_readw,
2610 cirrus_linear_bitblt_readl,
2611};
2612
2613static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2614 cirrus_linear_bitblt_writeb,
2615 cirrus_linear_bitblt_writew,
2616 cirrus_linear_bitblt_writel,
2617};
2618
2bec46dc
AL		 2619static void map_linear_vram(CirrusVGAState *s)
2620{
ba7349cd 2621 vga_dirty_log_stop((VGAState *)s);
2bec46dc
AL		 2622
2623 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2624 s->map_addr = s->lfb_addr;
2625 s->map_end = s->lfb_end;
2626 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2bec46dc
AL		 2627 }
2628
2629 if (!s->map_addr)
2630 return;
2631
2632 s->lfb_vram_mapped = 0;
2633
8a93e519
AL		 2634 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2635 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_UNASSIGNED);
2636 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2637 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_UNASSIGNED);
2bec46dc
AL		 2638 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2639 && !((s->sr[0x07] & 0x01) == 0)
2640 && !((s->gr[0x0B] & 0x14) == 0x14)
2641 && !(s->gr[0x0B] & 0x02)) {
2642
8a93e519 2643 vga_dirty_log_stop((VGAState *)s);
2bec46dc
AL		 2644 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2645 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2646 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2647 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2648
2649 s->lfb_vram_mapped = 1;
2bec46dc
AL		 2650 }
2651 else {
7cff316e
AL		 2652 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2653 s->vga_io_memory);
2bec46dc
AL		 2654 }
2655
ba7349cd 2656 vga_dirty_log_start((VGAState *)s);
2bec46dc
AL		 2657}
2658
2659static void unmap_linear_vram(CirrusVGAState *s)
2660{
ba7349cd
AL		 2661 vga_dirty_log_stop((VGAState *)s);
2662
2663 if (s->map_addr && s->lfb_addr && s->lfb_end)
2bec46dc 2664 s->map_addr = s->map_end = 0;
2bec46dc
AL		 2665
2666 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2667 s->vga_io_memory);
ba7349cd
AL		 2668
2669 vga_dirty_log_start((VGAState *)s);
2bec46dc
AL		 2670}
2671
8926b517
FB		 2672/* Compute the memory access functions */
2673static void cirrus_update_memory_access(CirrusVGAState *s)
2674{
2675 unsigned mode;
2676
2677 if ((s->sr[0x17] & 0x44) == 0x44) {
2678 goto generic_io;
2679 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2680 goto generic_io;
2681 } else {
2682 if ((s->gr[0x0B] & 0x14) == 0x14) {
2683 goto generic_io;
2684 } else if (s->gr[0x0B] & 0x02) {
2685 goto generic_io;
2686 }
3b46e624 2687
8926b517
FB		 2688 mode = s->gr[0x05] & 0x7;
2689 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2bec46dc 2690 map_linear_vram(s);
8926b517
FB		 2691 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2692 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2693 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2694 } else {
2695 generic_io:
2bec46dc 2696 unmap_linear_vram(s);
8926b517
FB		 2697 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2698 s->cirrus_linear_write[1] = cirrus_linear_writew;
2699 s->cirrus_linear_write[2] = cirrus_linear_writel;
2700 }
2701 }
2702}
2703
2704
e6e5ad80
FB		 2705/* I/O ports */
2706
2707static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2708{
2709 CirrusVGAState *s = opaque;
2710 int val, index;
2711
2712 /* check port range access depending on color/monochrome mode */
2713 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2714 || (addr >= 0x3d0 && addr <= 0x3df
2715 && !(s->msr & MSR_COLOR_EMULATION))) {
2716 val = 0xff;
2717 } else {
2718 switch (addr) {
2719 case 0x3c0:
2720 if (s->ar_flip_flop == 0) {
2721 val = s->ar_index;
2722 } else {
2723 val = 0;
2724 }
2725 break;
2726 case 0x3c1:
2727 index = s->ar_index & 0x1f;
2728 if (index < 21)
2729 val = s->ar[index];
2730 else
2731 val = 0;
2732 break;
2733 case 0x3c2:
2734 val = s->st00;
2735 break;
2736 case 0x3c4:
2737 val = s->sr_index;
2738 break;
2739 case 0x3c5:
2740 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2741 break;
2742 val = s->sr[s->sr_index];
2743#ifdef DEBUG_VGA_REG
2744 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2745#endif
2746 break;
2747 case 0x3c6:
2748 cirrus_read_hidden_dac(s, &val);
2749 break;
2750 case 0x3c7:
2751 val = s->dac_state;
2752 break;
ae184e4a
FB		 2753 case 0x3c8:
2754 val = s->dac_write_index;
2755 s->cirrus_hidden_dac_lockindex = 0;
2756 break;
2757 case 0x3c9:
e6e5ad80
FB		 2758 if (cirrus_hook_read_palette(s, &val))
2759 break;
2760 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2761 if (++s->dac_sub_index == 3) {
2762 s->dac_sub_index = 0;
2763 s->dac_read_index++;
2764 }
2765 break;
2766 case 0x3ca:
2767 val = s->fcr;
2768 break;
2769 case 0x3cc:
2770 val = s->msr;
2771 break;
2772 case 0x3ce:
2773 val = s->gr_index;
2774 break;
2775 case 0x3cf:
2776 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2777 break;
2778 val = s->gr[s->gr_index];
2779#ifdef DEBUG_VGA_REG
2780 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2781#endif
2782 break;
2783 case 0x3b4:
2784 case 0x3d4:
2785 val = s->cr_index;
2786 break;
2787 case 0x3b5:
2788 case 0x3d5:
2789 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2790 break;
2791 val = s->cr[s->cr_index];
2792#ifdef DEBUG_VGA_REG
2793 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2794#endif
2795 break;
2796 case 0x3ba:
2797 case 0x3da:
2798 /* just toggle to fool polling */
cb5a7aa8 2799 val = s->st01 = s->retrace((VGAState *) s);
e6e5ad80
FB		 2800 s->ar_flip_flop = 0;
2801 break;
2802 default:
2803 val = 0x00;
2804 break;
2805 }
2806 }
2807#if defined(DEBUG_VGA)
2808 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2809#endif
2810 return val;
2811}
2812
2813static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2814{
2815 CirrusVGAState *s = opaque;
2816 int index;
2817
2818 /* check port range access depending on color/monochrome mode */
2819 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2820 || (addr >= 0x3d0 && addr <= 0x3df
2821 && !(s->msr & MSR_COLOR_EMULATION)))
2822 return;
2823
2824#ifdef DEBUG_VGA
2825 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2826#endif
2827
2828 switch (addr) {
2829 case 0x3c0:
2830 if (s->ar_flip_flop == 0) {
2831 val &= 0x3f;
2832 s->ar_index = val;
2833 } else {
2834 index = s->ar_index & 0x1f;
2835 switch (index) {
2836 case 0x00 ... 0x0f:
2837 s->ar[index] = val & 0x3f;
2838 break;
2839 case 0x10:
2840 s->ar[index] = val & ~0x10;
2841 break;
2842 case 0x11:
2843 s->ar[index] = val;
2844 break;
2845 case 0x12:
2846 s->ar[index] = val & ~0xc0;
2847 break;
2848 case 0x13:
2849 s->ar[index] = val & ~0xf0;
2850 break;
2851 case 0x14:
2852 s->ar[index] = val & ~0xf0;
2853 break;
2854 default:
2855 break;
2856 }
2857 }
2858 s->ar_flip_flop ^= 1;
2859 break;
2860 case 0x3c2:
2861 s->msr = val & ~0x10;
cb5a7aa8 2862 s->update_retrace_info((VGAState *) s);
e6e5ad80
FB		 2863 break;
2864 case 0x3c4:
2865 s->sr_index = val;
2866 break;
2867 case 0x3c5:
2868 if (cirrus_hook_write_sr(s, s->sr_index, val))
2869 break;
2870#ifdef DEBUG_VGA_REG
2871 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2872#endif
2873 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
cb5a7aa8 2874 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
e6e5ad80
FB		 2875 break;
2876 case 0x3c6:
2877 cirrus_write_hidden_dac(s, val);
2878 break;
2879 case 0x3c7:
2880 s->dac_read_index = val;
2881 s->dac_sub_index = 0;
2882 s->dac_state = 3;
2883 break;
2884 case 0x3c8:
2885 s->dac_write_index = val;
2886 s->dac_sub_index = 0;
2887 s->dac_state = 0;
2888 break;
2889 case 0x3c9:
2890 if (cirrus_hook_write_palette(s, val))
2891 break;
2892 s->dac_cache[s->dac_sub_index] = val;
2893 if (++s->dac_sub_index == 3) {
2894 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2895 s->dac_sub_index = 0;
2896 s->dac_write_index++;
2897 }
2898 break;
2899 case 0x3ce:
2900 s->gr_index = val;
2901 break;
2902 case 0x3cf:
2903 if (cirrus_hook_write_gr(s, s->gr_index, val))
2904 break;
2905#ifdef DEBUG_VGA_REG
2906 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2907#endif
2908 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2909 break;
2910 case 0x3b4:
2911 case 0x3d4:
2912 s->cr_index = val;
2913 break;
2914 case 0x3b5:
2915 case 0x3d5:
2916 if (cirrus_hook_write_cr(s, s->cr_index, val))
2917 break;
2918#ifdef DEBUG_VGA_REG
2919 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2920#endif
2921 /* handle CR0-7 protection */
9bb34eac 2922 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
e6e5ad80
FB		 2923 /* can always write bit 4 of CR7 */
2924 if (s->cr_index == 7)
2925 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2926 return;
2927 }
2928 switch (s->cr_index) {
2929 case 0x01: /* horizontal display end */
2930 case 0x07:
2931 case 0x09:
2932 case 0x0c:
2933 case 0x0d:
e91c8a77 2934 case 0x12: /* vertical display end */
e6e5ad80
FB		 2935 s->cr[s->cr_index] = val;
2936 break;
2937
2938 default:
2939 s->cr[s->cr_index] = val;
2940 break;
2941 }
cb5a7aa8 2942
2943 switch(s->cr_index) {
2944 case 0x00:
2945 case 0x04:
2946 case 0x05:
2947 case 0x06:
2948 case 0x07:
2949 case 0x11:
2950 case 0x17:
2951 s->update_retrace_info((VGAState *) s);
2952 break;
2953 }
e6e5ad80
FB		 2954 break;
2955 case 0x3ba:
2956 case 0x3da:
2957 s->fcr = val & 0x10;
2958 break;
2959 }
2960}
2961
e36f36e1
FB		 2962/***************************************
2963 *
2964 * memory-mapped I/O access
2965 *
2966 ***************************************/
2967
2968static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2969{
2970 CirrusVGAState *s = (CirrusVGAState *) opaque;
2971
2972 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2973
2974 if (addr >= 0x100) {
2975 return cirrus_mmio_blt_read(s, addr - 0x100);
2976 } else {
2977 return vga_ioport_read(s, addr + 0x3c0);
2978 }
2979}
2980
2981static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2982{
2983 uint32_t v;
2984#ifdef TARGET_WORDS_BIGENDIAN
2985 v = cirrus_mmio_readb(opaque, addr) << 8;
2986 v |= cirrus_mmio_readb(opaque, addr + 1);
2987#else
2988 v = cirrus_mmio_readb(opaque, addr);
2989 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2990#endif
2991 return v;
2992}
2993
2994static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2995{
2996 uint32_t v;
2997#ifdef TARGET_WORDS_BIGENDIAN
2998 v = cirrus_mmio_readb(opaque, addr) << 24;
2999 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3000 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3001 v |= cirrus_mmio_readb(opaque, addr + 3);
3002#else
3003 v = cirrus_mmio_readb(opaque, addr);
3004 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3005 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3006 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3007#endif
3008 return v;
3009}
3010
3011static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3012 uint32_t val)
3013{
3014 CirrusVGAState *s = (CirrusVGAState *) opaque;
3015
3016 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3017
3018 if (addr >= 0x100) {
3019 cirrus_mmio_blt_write(s, addr - 0x100, val);
3020 } else {
3021 vga_ioport_write(s, addr + 0x3c0, val);
3022 }
3023}
3024
3025static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3026 uint32_t val)
3027{
3028#ifdef TARGET_WORDS_BIGENDIAN
3029 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3030 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3031#else
3032 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3033 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3034#endif
3035}
3036
3037static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3038 uint32_t val)
3039{
3040#ifdef TARGET_WORDS_BIGENDIAN
3041 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3042 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3043 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3044 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3045#else
3046 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3047 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3048 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3049 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3050#endif
3051}
3052
3053
3054static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3055 cirrus_mmio_readb,
3056 cirrus_mmio_readw,
3057 cirrus_mmio_readl,
3058};
3059
3060static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3061 cirrus_mmio_writeb,
3062 cirrus_mmio_writew,
3063 cirrus_mmio_writel,
3064};
3065
2c6ab832
FB		 3066/* load/save state */
3067
3068static void cirrus_vga_save(QEMUFile *f, void *opaque)
3069{
3070 CirrusVGAState *s = opaque;
3071
d2269f6f
FB		 3072 if (s->pci_dev)
3073 pci_device_save(s->pci_dev, f);
3074
2c6ab832
FB		 3075 qemu_put_be32s(f, &s->latch);
3076 qemu_put_8s(f, &s->sr_index);
3077 qemu_put_buffer(f, s->sr, 256);
3078 qemu_put_8s(f, &s->gr_index);
3079 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3080 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3081 qemu_put_buffer(f, s->gr + 2, 254);
3082 qemu_put_8s(f, &s->ar_index);
3083 qemu_put_buffer(f, s->ar, 21);
bee8d684 3084 qemu_put_be32(f, s->ar_flip_flop);
2c6ab832
FB		 3085 qemu_put_8s(f, &s->cr_index);
3086 qemu_put_buffer(f, s->cr, 256);
3087 qemu_put_8s(f, &s->msr);
3088 qemu_put_8s(f, &s->fcr);
3089 qemu_put_8s(f, &s->st00);
3090 qemu_put_8s(f, &s->st01);
3091
3092 qemu_put_8s(f, &s->dac_state);
3093 qemu_put_8s(f, &s->dac_sub_index);
3094 qemu_put_8s(f, &s->dac_read_index);
3095 qemu_put_8s(f, &s->dac_write_index);
3096 qemu_put_buffer(f, s->dac_cache, 3);
3097 qemu_put_buffer(f, s->palette, 768);
3098
bee8d684 3099 qemu_put_be32(f, s->bank_offset);
2c6ab832
FB		 3100
3101 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3102 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3103
3104 qemu_put_be32s(f, &s->hw_cursor_x);
3105 qemu_put_be32s(f, &s->hw_cursor_y);
3106 /* XXX: we do not save the bitblt state - we assume we do not save
3107 the state when the blitter is active */
3108}
3109
3110static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3111{
3112 CirrusVGAState *s = opaque;
d2269f6f 3113 int ret;
2c6ab832 3114
d2269f6f 3115 if (version_id > 2)
2c6ab832
FB		 3116 return -EINVAL;
3117
d2269f6f
FB		 3118 if (s->pci_dev && version_id >= 2) {
3119 ret = pci_device_load(s->pci_dev, f);
3120 if (ret < 0)
3121 return ret;
3122 }
3123
2c6ab832
FB		 3124 qemu_get_be32s(f, &s->latch);
3125 qemu_get_8s(f, &s->sr_index);
3126 qemu_get_buffer(f, s->sr, 256);
3127 qemu_get_8s(f, &s->gr_index);
3128 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3129 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3130 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3131 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3132 qemu_get_buffer(f, s->gr + 2, 254);
3133 qemu_get_8s(f, &s->ar_index);
3134 qemu_get_buffer(f, s->ar, 21);
bee8d684 3135 s->ar_flip_flop=qemu_get_be32(f);
2c6ab832
FB		 3136 qemu_get_8s(f, &s->cr_index);
3137 qemu_get_buffer(f, s->cr, 256);
3138 qemu_get_8s(f, &s->msr);
3139 qemu_get_8s(f, &s->fcr);
3140 qemu_get_8s(f, &s->st00);
3141 qemu_get_8s(f, &s->st01);
3142
3143 qemu_get_8s(f, &s->dac_state);
3144 qemu_get_8s(f, &s->dac_sub_index);
3145 qemu_get_8s(f, &s->dac_read_index);
3146 qemu_get_8s(f, &s->dac_write_index);
3147 qemu_get_buffer(f, s->dac_cache, 3);
3148 qemu_get_buffer(f, s->palette, 768);
3149
bee8d684 3150 s->bank_offset=qemu_get_be32(f);
2c6ab832
FB		 3151
3152 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3153 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3154
3155 qemu_get_be32s(f, &s->hw_cursor_x);
3156 qemu_get_be32s(f, &s->hw_cursor_y);
3157
2bec46dc 3158 cirrus_update_memory_access(s);
2c6ab832 3159 /* force refresh */
799e709b 3160 s->graphic_mode = -1;
2c6ab832
FB		 3161 cirrus_update_bank_ptr(s, 0);
3162 cirrus_update_bank_ptr(s, 1);
3163 return 0;
3164}
3165
e6e5ad80
FB		 3166/***************************************
3167 *
3168 * initialize
3169 *
3170 ***************************************/
3171
4abc796d 3172static void cirrus_reset(void *opaque)
e6e5ad80 3173{
4abc796d 3174 CirrusVGAState *s = opaque;
e6e5ad80 3175
4abc796d 3176 vga_reset(s);
ee50c6bc 3177 unmap_linear_vram(s);
e6e5ad80 3178 s->sr[0x06] = 0x0f;
4abc796d 3179 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 3180 /* 4MB 64 bit memory config, always PCI */
b30d4608
FB		 3181 s->sr[0x1F] = 0x2d; // MemClock
3182 s->gr[0x18] = 0x0f; // fastest memory configuration
78e127ef
FB		 3183 s->sr[0x0f] = 0x98;
3184 s->sr[0x17] = 0x20;
3185 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 3186 } else {
b30d4608 3187 s->sr[0x1F] = 0x22; // MemClock
78e127ef 3188 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
4abc796d 3189 s->sr[0x17] = s->bustype;
78e127ef
FB		 3190 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3191 }
4abc796d 3192 s->cr[0x27] = s->device_id;
e6e5ad80 3193
78e127ef
FB		 3194 /* Win2K seems to assume that the pattern buffer is at 0xff
3195 initially ! */
3196 memset(s->vram_ptr, 0xff, s->real_vram_size);
3197
e6e5ad80
FB		 3198 s->cirrus_hidden_dac_lockindex = 5;
3199 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 3200}
3201
3202static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3203{
3204 int i;
3205 static int inited;
3206
3207 if (!inited) {
3208 inited = 1;
3209 for(i = 0;i < 256; i++)
3210 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3211 rop_to_index[CIRRUS_ROP_0] = 0;
3212 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3213 rop_to_index[CIRRUS_ROP_NOP] = 2;
3214 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3215 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3216 rop_to_index[CIRRUS_ROP_SRC] = 5;
3217 rop_to_index[CIRRUS_ROP_1] = 6;
3218 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3219 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3220 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3221 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3222 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3223 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3224 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3225 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3226 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3227 s->device_id = device_id;
3228 if (is_pci)
3229 s->bustype = CIRRUS_BUSTYPE_PCI;
3230 else
3231 s->bustype = CIRRUS_BUSTYPE_ISA;
3232 }
3233
3234 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3235
3236 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3237 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3238 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3239 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3240
3241 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3242
3243 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3244 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3245 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3246 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3247
3248 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3249 cirrus_vga_mem_write, s);
3250 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3251 s->vga_io_memory);
3252 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2c6ab832 3253
fefe54e3
AL		 3254 /* I/O handler for LFB */
3255 s->cirrus_linear_io_addr =
3256 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s);
3257 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3258
3259 /* I/O handler for LFB */
3260 s->cirrus_linear_bitblt_io_addr =
3261 cpu_register_io_memory(0, cirrus_linear_bitblt_read,
3262 cirrus_linear_bitblt_write, s);
3263
3264 /* I/O handler for memory-mapped I/O */
3265 s->cirrus_mmio_io_addr =
3266 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3267
3268 s->real_vram_size =
3269 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3270
3271 /* XXX: s->vram_size must be a power of two */
3272 s->cirrus_addr_mask = s->real_vram_size - 1;
3273 s->linear_mmio_mask = s->real_vram_size - 256;
3274
3275 s->get_bpp = cirrus_get_bpp;
3276 s->get_offsets = cirrus_get_offsets;
3277 s->get_resolution = cirrus_get_resolution;
3278 s->cursor_invalidate = cirrus_cursor_invalidate;
3279 s->cursor_draw_line = cirrus_cursor_draw_line;
3280
4abc796d
BS		 3281 qemu_register_reset(cirrus_reset, s);
3282 cirrus_reset(s);
d2269f6f 3283 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
e6e5ad80
FB		 3284}
3285
3286/***************************************
3287 *
3288 * ISA bus support
3289 *
3290 ***************************************/
3291
3023f332 3292void isa_cirrus_vga_init(uint8_t *vga_ram_base,
4efe2755 3293 ram_addr_t vga_ram_offset, int vga_ram_size)
e6e5ad80
FB		 3294{
3295 CirrusVGAState *s;
3296
3297 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3298
5fafdf24 3299 vga_common_init((VGAState *)s,
3023f332 3300 vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 3301 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3023f332
AL		 3302 s->ds = graphic_console_init(s->update, s->invalidate,
3303 s->screen_dump, s->text_update, s);
e6e5ad80
FB		 3304 /* XXX ISA-LFB support */
3305}
3306
3307/***************************************
3308 *
3309 * PCI bus support
3310 *
3311 ***************************************/
3312
3313static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3314 uint32_t addr, uint32_t size, int type)
3315{
3316 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3317
ba7349cd
AL		 3318 vga_dirty_log_stop((VGAState *)s);
3319
a5082316 3320 /* XXX: add byte swapping apertures */
e6e5ad80
FB		 3321 cpu_register_physical_memory(addr, s->vram_size,
3322 s->cirrus_linear_io_addr);
a5082316
FB		 3323 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3324 s->cirrus_linear_bitblt_io_addr);
2bec46dc
AL		 3325
3326 s->map_addr = s->map_end = 0;
3327 s->lfb_addr = addr & TARGET_PAGE_MASK;
3328 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3329 /* account for overflow */
3330 if (s->lfb_end < addr + VGA_RAM_SIZE)
3331 s->lfb_end = addr + VGA_RAM_SIZE;
ba7349cd
AL		 3332
3333 vga_dirty_log_start((VGAState *)s);
e6e5ad80
FB		 3334}
3335
3336static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3337 uint32_t addr, uint32_t size, int type)
3338{
3339 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3340
3341 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3342 s->cirrus_mmio_io_addr);
3343}
3344
ba7349cd
AL		 3345static void pci_cirrus_write_config(PCIDevice *d,
3346 uint32_t address, uint32_t val, int len)
3347{
3348 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3349 CirrusVGAState *s = &pvs->cirrus_vga;
3350
3351 vga_dirty_log_stop((VGAState *)s);
3352
3353 pci_default_write_config(d, address, val, len);
3354 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
3355 s->map_addr = 0;
3356 cirrus_update_memory_access(s);
3357
3358 vga_dirty_log_start((VGAState *)s);
3359}
3360
3023f332 3361void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
4efe2755 3362 ram_addr_t vga_ram_offset, int vga_ram_size)
e6e5ad80
FB		 3363{
3364 PCICirrusVGAState *d;
3365 uint8_t *pci_conf;
3366 CirrusVGAState *s;
20ba3ae1 3367 int device_id;
3b46e624 3368
20ba3ae1 3369 device_id = CIRRUS_ID_CLGD5446;
e6e5ad80
FB		 3370
3371 /* setup PCI configuration registers */
5fafdf24
TS		 3372 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3373 sizeof(PCICirrusVGAState),
ba7349cd 3374 -1, NULL, pci_cirrus_write_config);
e6e5ad80 3375 pci_conf = d->dev.config;
deb54399
AL		 3376 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3377 pci_config_set_device_id(pci_conf, device_id);
e6e5ad80 3378 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
173a543b 3379 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
e6e5ad80
FB		 3380 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3381
3382 /* setup VGA */
3383 s = &d->cirrus_vga;
5fafdf24 3384 vga_common_init((VGAState *)s,
3023f332 3385 vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 3386 cirrus_init_common(s, device_id, 1);
d34cab9f 3387
3023f332
AL		 3388 s->ds = graphic_console_init(s->update, s->invalidate,
3389 s->screen_dump, s->text_update, s);
d34cab9f 3390
d2269f6f 3391 s->pci_dev = (PCIDevice *)d;
e6e5ad80
FB		 3392
3393 /* setup memory space */
3394 /* memory #0 LFB */
3395 /* memory #1 memory-mapped I/O */
3396 /* XXX: s->vram_size must be a power of two */
a5082316 3397 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
a21ae81d 3398 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
20ba3ae1 3399 if (device_id == CIRRUS_ID_CLGD5446) {
a21ae81d
FB		 3400 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3401 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3402 }
e6e5ad80
FB		 3403 /* XXX: ROM BIOS */
3404}
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