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Commit | Line | Data |
---|---|---|
5fafdf24 | 1 | /* |
423f0742 PB |
2 | * General purpose implementation of a simple periodic countdown timer. |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery. | |
5 | * | |
8e31bf38 | 6 | * This code is licensed under the GNU LGPL. |
423f0742 | 7 | */ |
18c86e2b | 8 | #include "qemu/osdep.h" |
83c9f4ca | 9 | #include "hw/hw.h" |
1de7afc9 | 10 | #include "qemu/timer.h" |
83c9f4ca | 11 | #include "hw/ptimer.h" |
1de7afc9 | 12 | #include "qemu/host-utils.h" |
8a354bd9 | 13 | #include "sysemu/replay.h" |
2a8b5870 | 14 | #include "sysemu/qtest.h" |
072bdb07 | 15 | #include "block/aio.h" |
d2528bdc | 16 | #include "sysemu/cpus.h" |
423f0742 | 17 | |
22471b8a DO |
18 | #define DELTA_ADJUST 1 |
19 | #define DELTA_NO_ADJUST -1 | |
2b5c0322 | 20 | |
423f0742 PB |
21 | struct ptimer_state |
22 | { | |
852f771e | 23 | uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ |
8d05ea8a BS |
24 | uint64_t limit; |
25 | uint64_t delta; | |
423f0742 PB |
26 | uint32_t period_frac; |
27 | int64_t period; | |
28 | int64_t last_event; | |
29 | int64_t next_event; | |
e7ea81c3 | 30 | uint8_t policy_mask; |
423f0742 PB |
31 | QEMUBH *bh; |
32 | QEMUTimer *timer; | |
33 | }; | |
34 | ||
35 | /* Use a bottom-half routine to avoid reentrancy issues. */ | |
36 | static void ptimer_trigger(ptimer_state *s) | |
37 | { | |
38 | if (s->bh) { | |
8a354bd9 | 39 | replay_bh_schedule_event(s->bh); |
423f0742 PB |
40 | } |
41 | } | |
42 | ||
2b5c0322 | 43 | static void ptimer_reload(ptimer_state *s, int delta_adjust) |
423f0742 | 44 | { |
e91171e3 DO |
45 | uint32_t period_frac = s->period_frac; |
46 | uint64_t period = s->period; | |
2b5c0322 | 47 | uint64_t delta = s->delta; |
086ede32 | 48 | bool suppress_trigger = false; |
e91171e3 | 49 | |
086ede32 PM |
50 | /* |
51 | * Note that if delta_adjust is 0 then we must be here because of | |
52 | * a count register write or timer start, not because of timer expiry. | |
53 | * In that case the policy might require us to suppress the timer trigger | |
54 | * that we would otherwise generate for a zero delta. | |
55 | */ | |
56 | if (delta_adjust == 0 && | |
57 | (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { | |
58 | suppress_trigger = true; | |
59 | } | |
60 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) | |
61 | && !suppress_trigger) { | |
423f0742 | 62 | ptimer_trigger(s); |
22471b8a DO |
63 | } |
64 | ||
3f6e6a13 | 65 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
2b5c0322 | 66 | delta = s->delta = s->limit; |
423f0742 | 67 | } |
ef0a9984 DO |
68 | |
69 | if (s->period == 0) { | |
2a8b5870 DO |
70 | if (!qtest_enabled()) { |
71 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
72 | } | |
780d23e5 | 73 | timer_del(s->timer); |
423f0742 PB |
74 | s->enabled = 0; |
75 | return; | |
76 | } | |
77 | ||
2b5c0322 | 78 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { |
22471b8a DO |
79 | if (delta_adjust != DELTA_NO_ADJUST) { |
80 | delta += delta_adjust; | |
81 | } | |
2b5c0322 DO |
82 | } |
83 | ||
ef0a9984 DO |
84 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_CONTINUOUS_TRIGGER)) { |
85 | if (s->enabled == 1 && s->limit == 0) { | |
86 | delta = 1; | |
87 | } | |
88 | } | |
89 | ||
22471b8a DO |
90 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
91 | if (delta_adjust != DELTA_NO_ADJUST) { | |
92 | delta = 1; | |
93 | } | |
94 | } | |
95 | ||
3f6e6a13 DO |
96 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
97 | if (s->enabled == 1 && s->limit != 0) { | |
98 | delta = 1; | |
99 | } | |
100 | } | |
101 | ||
ef0a9984 DO |
102 | if (delta == 0) { |
103 | if (!qtest_enabled()) { | |
104 | fprintf(stderr, "Timer with delta zero, disabling\n"); | |
105 | } | |
106 | timer_del(s->timer); | |
107 | s->enabled = 0; | |
108 | return; | |
109 | } | |
110 | ||
e91171e3 DO |
111 | /* |
112 | * Artificially limit timeout rate to something | |
113 | * achievable under QEMU. Otherwise, QEMU spends all | |
114 | * its time generating timer interrupts, and there | |
115 | * is no forward progress. | |
116 | * About ten microseconds is the fastest that really works | |
117 | * on the current generation of host machines. | |
118 | */ | |
119 | ||
2b5c0322 DO |
120 | if (s->enabled == 1 && (delta * period < 10000) && !use_icount) { |
121 | period = 10000 / delta; | |
e91171e3 DO |
122 | period_frac = 0; |
123 | } | |
124 | ||
423f0742 | 125 | s->last_event = s->next_event; |
2b5c0322 | 126 | s->next_event = s->last_event + delta * period; |
e91171e3 | 127 | if (period_frac) { |
2b5c0322 | 128 | s->next_event += ((int64_t)period_frac * delta) >> 32; |
423f0742 | 129 | } |
bc72ad67 | 130 | timer_mod(s->timer, s->next_event); |
423f0742 PB |
131 | } |
132 | ||
133 | static void ptimer_tick(void *opaque) | |
134 | { | |
135 | ptimer_state *s = (ptimer_state *)opaque; | |
3f6e6a13 DO |
136 | bool trigger = true; |
137 | ||
423f0742 | 138 | if (s->enabled == 2) { |
3f6e6a13 | 139 | s->delta = 0; |
423f0742 PB |
140 | s->enabled = 0; |
141 | } else { | |
ef0a9984 DO |
142 | int delta_adjust = DELTA_ADJUST; |
143 | ||
3f6e6a13 | 144 | if (s->delta == 0 || s->limit == 0) { |
ef0a9984 | 145 | /* If a "continuous trigger" policy is not used and limit == 0, |
3f6e6a13 DO |
146 | we should error out. delta == 0 means that this tick is |
147 | caused by a "no immediate reload" policy, so it shouldn't | |
148 | be adjusted. */ | |
22471b8a | 149 | delta_adjust = DELTA_NO_ADJUST; |
ef0a9984 DO |
150 | } |
151 | ||
3f6e6a13 DO |
152 | if (!(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
153 | /* Avoid re-trigger on deferred reload if "no immediate trigger" | |
154 | policy isn't used. */ | |
155 | trigger = (delta_adjust == DELTA_ADJUST); | |
156 | } | |
157 | ||
158 | s->delta = s->limit; | |
159 | ||
ef0a9984 | 160 | ptimer_reload(s, delta_adjust); |
423f0742 | 161 | } |
3f6e6a13 DO |
162 | |
163 | if (trigger) { | |
164 | ptimer_trigger(s); | |
165 | } | |
423f0742 PB |
166 | } |
167 | ||
8d05ea8a | 168 | uint64_t ptimer_get_count(ptimer_state *s) |
423f0742 | 169 | { |
8d05ea8a | 170 | uint64_t counter; |
423f0742 | 171 | |
ef0a9984 | 172 | if (s->enabled && s->delta != 0) { |
5a50307b DO |
173 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
174 | int64_t next = s->next_event; | |
2b5c0322 | 175 | int64_t last = s->last_event; |
5a50307b DO |
176 | bool expired = (now - next >= 0); |
177 | bool oneshot = (s->enabled == 2); | |
178 | ||
423f0742 | 179 | /* Figure out the current counter value. */ |
56215da3 | 180 | if (expired) { |
423f0742 PB |
181 | /* Prevent timer underflowing if it should already have |
182 | triggered. */ | |
183 | counter = 0; | |
184 | } else { | |
8d05ea8a BS |
185 | uint64_t rem; |
186 | uint64_t div; | |
d0a981b2 PB |
187 | int clz1, clz2; |
188 | int shift; | |
e91171e3 DO |
189 | uint32_t period_frac = s->period_frac; |
190 | uint64_t period = s->period; | |
191 | ||
5a50307b | 192 | if (!oneshot && (s->delta * period < 10000) && !use_icount) { |
e91171e3 DO |
193 | period = 10000 / s->delta; |
194 | period_frac = 0; | |
195 | } | |
d0a981b2 PB |
196 | |
197 | /* We need to divide time by period, where time is stored in | |
198 | rem (64-bit integer) and period is stored in period/period_frac | |
199 | (64.32 fixed point). | |
2b5c0322 | 200 | |
d0a981b2 PB |
201 | Doing full precision division is hard, so scale values and |
202 | do a 64-bit division. The result should be rounded down, | |
203 | so that the rounding error never causes the timer to go | |
204 | backwards. | |
205 | */ | |
423f0742 | 206 | |
56215da3 | 207 | rem = next - now; |
e91171e3 | 208 | div = period; |
d0a981b2 PB |
209 | |
210 | clz1 = clz64(rem); | |
211 | clz2 = clz64(div); | |
212 | shift = clz1 < clz2 ? clz1 : clz2; | |
213 | ||
214 | rem <<= shift; | |
215 | div <<= shift; | |
216 | if (shift >= 32) { | |
e91171e3 | 217 | div |= ((uint64_t)period_frac << (shift - 32)); |
d0a981b2 PB |
218 | } else { |
219 | if (shift != 0) | |
e91171e3 | 220 | div |= (period_frac >> (32 - shift)); |
d0a981b2 PB |
221 | /* Look at remaining bits of period_frac and round div up if |
222 | necessary. */ | |
e91171e3 | 223 | if ((uint32_t)(period_frac << shift)) |
d0a981b2 PB |
224 | div += 1; |
225 | } | |
423f0742 | 226 | counter = rem / div; |
2b5c0322 DO |
227 | |
228 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { | |
229 | /* Before wrapping around, timer should stay with counter = 0 | |
230 | for a one period. */ | |
231 | if (!oneshot && s->delta == s->limit) { | |
232 | if (now == last) { | |
233 | /* Counter == delta here, check whether it was | |
234 | adjusted and if it was, then right now it is | |
235 | that "one period". */ | |
236 | if (counter == s->limit + DELTA_ADJUST) { | |
237 | return 0; | |
238 | } | |
239 | } else if (counter == s->limit) { | |
240 | /* Since the counter is rounded down and now != last, | |
241 | the counter == limit means that delta was adjusted | |
242 | by +1 and right now it is that adjusted period. */ | |
243 | return 0; | |
244 | } | |
245 | } | |
246 | } | |
423f0742 | 247 | } |
5580ea45 DO |
248 | |
249 | if (s->policy_mask & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) { | |
250 | /* If now == last then delta == limit, i.e. the counter already | |
251 | represents the correct value. It would be rounded down a 1ns | |
252 | later. */ | |
253 | if (now != last) { | |
254 | counter += 1; | |
255 | } | |
256 | } | |
423f0742 PB |
257 | } else { |
258 | counter = s->delta; | |
259 | } | |
260 | return counter; | |
261 | } | |
262 | ||
8d05ea8a | 263 | void ptimer_set_count(ptimer_state *s, uint64_t count) |
423f0742 PB |
264 | { |
265 | s->delta = count; | |
266 | if (s->enabled) { | |
bc72ad67 | 267 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 268 | ptimer_reload(s, 0); |
423f0742 PB |
269 | } |
270 | } | |
271 | ||
272 | void ptimer_run(ptimer_state *s, int oneshot) | |
273 | { | |
869e92b5 DO |
274 | bool was_disabled = !s->enabled; |
275 | ||
276 | if (was_disabled && s->period == 0) { | |
2a8b5870 DO |
277 | if (!qtest_enabled()) { |
278 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
279 | } | |
423f0742 PB |
280 | return; |
281 | } | |
282 | s->enabled = oneshot ? 2 : 1; | |
869e92b5 DO |
283 | if (was_disabled) { |
284 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
2b5c0322 | 285 | ptimer_reload(s, 0); |
869e92b5 | 286 | } |
423f0742 PB |
287 | } |
288 | ||
8d05ea8a | 289 | /* Pause a timer. Note that this may cause it to "lose" time, even if it |
423f0742 PB |
290 | is immediately restarted. */ |
291 | void ptimer_stop(ptimer_state *s) | |
292 | { | |
293 | if (!s->enabled) | |
294 | return; | |
295 | ||
296 | s->delta = ptimer_get_count(s); | |
bc72ad67 | 297 | timer_del(s->timer); |
423f0742 PB |
298 | s->enabled = 0; |
299 | } | |
300 | ||
301 | /* Set counter increment interval in nanoseconds. */ | |
302 | void ptimer_set_period(ptimer_state *s, int64_t period) | |
303 | { | |
7ef6e3cf | 304 | s->delta = ptimer_get_count(s); |
423f0742 PB |
305 | s->period = period; |
306 | s->period_frac = 0; | |
8d05ea8a | 307 | if (s->enabled) { |
bc72ad67 | 308 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 309 | ptimer_reload(s, 0); |
8d05ea8a | 310 | } |
423f0742 PB |
311 | } |
312 | ||
313 | /* Set counter frequency in Hz. */ | |
314 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | |
315 | { | |
7ef6e3cf | 316 | s->delta = ptimer_get_count(s); |
423f0742 PB |
317 | s->period = 1000000000ll / freq; |
318 | s->period_frac = (1000000000ll << 32) / freq; | |
8d05ea8a | 319 | if (s->enabled) { |
bc72ad67 | 320 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 321 | ptimer_reload(s, 0); |
8d05ea8a | 322 | } |
423f0742 PB |
323 | } |
324 | ||
325 | /* Set the initial countdown value. If reload is nonzero then also set | |
326 | count = limit. */ | |
8d05ea8a | 327 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) |
423f0742 | 328 | { |
423f0742 PB |
329 | s->limit = limit; |
330 | if (reload) | |
331 | s->delta = limit; | |
62ea5b0b | 332 | if (s->enabled && reload) { |
bc72ad67 | 333 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 334 | ptimer_reload(s, 0); |
8d05ea8a BS |
335 | } |
336 | } | |
337 | ||
578c4b2f DO |
338 | uint64_t ptimer_get_limit(ptimer_state *s) |
339 | { | |
340 | return s->limit; | |
341 | } | |
342 | ||
852f771e | 343 | const VMStateDescription vmstate_ptimer = { |
55a6e51f | 344 | .name = "ptimer", |
852f771e JQ |
345 | .version_id = 1, |
346 | .minimum_version_id = 1, | |
35d08458 | 347 | .fields = (VMStateField[]) { |
852f771e JQ |
348 | VMSTATE_UINT8(enabled, ptimer_state), |
349 | VMSTATE_UINT64(limit, ptimer_state), | |
350 | VMSTATE_UINT64(delta, ptimer_state), | |
351 | VMSTATE_UINT32(period_frac, ptimer_state), | |
352 | VMSTATE_INT64(period, ptimer_state), | |
353 | VMSTATE_INT64(last_event, ptimer_state), | |
354 | VMSTATE_INT64(next_event, ptimer_state), | |
e720677e | 355 | VMSTATE_TIMER_PTR(timer, ptimer_state), |
852f771e JQ |
356 | VMSTATE_END_OF_LIST() |
357 | } | |
55a6e51f BS |
358 | }; |
359 | ||
e7ea81c3 | 360 | ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) |
423f0742 PB |
361 | { |
362 | ptimer_state *s; | |
363 | ||
7267c094 | 364 | s = (ptimer_state *)g_malloc0(sizeof(ptimer_state)); |
423f0742 | 365 | s->bh = bh; |
bc72ad67 | 366 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); |
e7ea81c3 | 367 | s->policy_mask = policy_mask; |
086ede32 PM |
368 | |
369 | /* | |
370 | * These two policies are incompatible -- trigger-on-decrement implies | |
371 | * a timer trigger when the count becomes 0, but no-immediate-trigger | |
372 | * implies a trigger when the count stops being 0. | |
373 | */ | |
374 | assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && | |
375 | (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); | |
423f0742 PB |
376 | return s; |
377 | } | |
072bdb07 MAL |
378 | |
379 | void ptimer_free(ptimer_state *s) | |
380 | { | |
381 | qemu_bh_delete(s->bh); | |
382 | timer_free(s->timer); | |
383 | g_free(s); | |
384 | } |