[qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "isa.h"
#include "sysbus.h"

typedef uint32_t pci_addr_t;
#include "pci_host.h"

typedef PCIHostState I440FXState;

typedef struct PIIX3State {
    PCIDevice dev;
    int pci_irq_levels[4];
} PIIX3State;

typedef struct PIIX3IrqState {
    PIIX3State *piix3;
    qemu_irq *pic;
} PIIX3IrqState;

struct PCII440FXState {
    PCIDevice dev;
    target_phys_addr_t isa_page_descs[384 / 4];
    uint8_t smm_enabled;
    PIIX3IrqState *irq_state;
};

static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
{
    I440FXState *s = opaque;
    s->config_reg = val;
}

static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
{
    I440FXState *s = opaque;
    return s->config_reg;
}

static void piix3_set_irq(void *opaque, int irq_num, int level);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (irq_num + slot_addend) & 3;
}

static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
{
    uint32_t addr;

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        cpu_register_physical_memory(start, end - start,
                                     start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        cpu_register_physical_memory(start, end - start,
                                     start | IO_MEM_ROM);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        for(addr = start; addr < end; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
        break;
    }
}

static void i440fx_update_memory_mappings(PCII440FXState *d)
{
    int i, r;
    uint32_t smram, addr;

    update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
    for(i = 0; i < 12; i++) {
        r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
    }
    smram = d->dev.config[0x72];
    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
    } else {
        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
    }
}

void i440fx_set_smm(PCII440FXState *d, int val)
{
    val = (val != 0);
    if (d->smm_enabled != val) {
        d->smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


/* XXX: suppress when better memory API. We make the assumption that
   no device (in particular the VGA) changes the memory mappings in
   the 0xa0000-0x100000 range */
void i440fx_init_memory_mappings(PCII440FXState *d)
{
    int i;
    for(i = 0; i < 96; i++) {
        d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
    }
}

static void i440fx_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(dev, address, val, len);
    if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
        i440fx_update_memory_mappings(d);
}

static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
    PCII440FXState *d = opaque;
    int ret, i;

    ret = pci_device_load(&d->dev, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &d->smm_enabled);

    if (version_id == 2)
        for (i = 0; i < 4; i++)
            d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);

    return 0;
}

static int i440fx_post_load(void *opaque)
{
    PCII440FXState *d = opaque;

    i440fx_update_memory_mappings(d);
    return 0;
}

static const VMStateDescription vmstate_i440fx = {
    .name = "I440FX",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = i440fx_load_old,
    .post_load = i440fx_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCII440FXState),
        VMSTATE_UINT8(smm_enabled, PCII440FXState),
        VMSTATE_END_OF_LIST()
    }
};

static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
    I440FXState *s = FROM_SYSBUS(I440FXState, dev);

    register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
    register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);

    register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
    register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
    register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
    register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
    return 0;
}

static int i440fx_initfn(PCIDevice *dev)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
    d->dev.config[0x08] = 0x02; // revision
    pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
    d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

    d->dev.config[0x72] = 0x02; /* SMRAM */

    vmstate_register(0, &vmstate_i440fx, d);
    return 0;
}

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
{
    DeviceState *dev;
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;
    PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state));

    irq_state->pic = pic;
    dev = qdev_create(NULL, "i440FX-pcihost");
    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
    b = pci_register_bus(&s->busdev.qdev, "pci.0",
                         piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
    s->bus = b;
    qdev_init(dev);

    d = pci_create_simple(b, 0, "i440FX");
    *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
    (*pi440fx_state)->irq_state = irq_state;

    irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
                                 pci_create_simple(b, -1, "PIIX3"));
    *piix3_devfn = irq_state->piix3->dev.devfn;

    return b;
}

/* PIIX3 PCI to ISA bridge */

static void piix3_set_irq(void *opaque, int irq_num, int level)
{
    int i, pic_irq, pic_level;
    PIIX3IrqState *irq_state = opaque;

    irq_state->piix3->pci_irq_levels[irq_num] = level;

    /* now we change the pic irq level according to the piix irq mappings */
    /* XXX: optimize */
    pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
    if (pic_irq < 16) {
        /* The pic level is the logical OR of all the PCI irqs mapped
           to it */
        pic_level = 0;
        for (i = 0; i < 4; i++) {
            if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
                pic_level |= irq_state->piix3->pci_irq_levels[i];
        }
        qemu_set_irq(irq_state->pic[pic_irq], pic_level);
    }
}

static void piix3_reset(void *opaque)
{
    PIIX3State *d = opaque;
    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
}

static const VMStateDescription vmstate_piix3 = {
    .name = "PIIX3",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX3State),
        VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
        VMSTATE_END_OF_LIST()
    }
};

static int piix3_initfn(PCIDevice *dev)
{
    PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
    uint8_t *pci_conf;

    isa_bus_new(&d->dev.qdev);
    vmstate_register(0, &vmstate_piix3, d);

    pci_conf = d->dev.config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
    pci_conf[PCI_HEADER_TYPE] =
        PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic

    piix3_reset(d);
    qemu_register_reset(piix3_reset, d);
    return 0;
}

static PCIDeviceInfo i440fx_info[] = {
    {
        .qdev.name    = "i440FX",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCII440FXState),
        .qdev.no_user = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config,
    },{
        .qdev.name    = "PIIX3",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PIIX3State),
        .qdev.no_user = 1,
        .init         = piix3_initfn,
    },{
        /* end of list */
    }
};

static SysBusDeviceInfo i440fx_pcihost_info = {
    .init         = i440fx_pcihost_initfn,
    .qdev.name    = "i440FX-pcihost",
    .qdev.size    = sizeof(I440FXState),
    .qdev.no_user = 1,
};

static void i440fx_register(void)
{
    sysbus_register_withprop(&i440fx_pcihost_info);
    pci_qdev_register_many(i440fx_info);
}
device_init(i440fx_register);
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
f75247f1	28	#include "isa.h"
8a14daa5	29	#include "sysbus.h"
87ecb68b	30
502a5395 PB	31	typedef uint32_t pci_addr_t;
	32	#include "pci_host.h"
	33
	34	typedef PCIHostState I440FXState;
	35
fd37d881 JQ	36	typedef struct PIIX3State {
fd37d881 JQ	37	PCIDevice dev;
8372615d	38	int pci_irq_levels[4];
fd37d881 JQ	39	} PIIX3State;
fd37d881 JQ	40
bd7dce87	41	typedef struct PIIX3IrqState {
fd83e9b9	42	PIIX3State *piix3;
bd7dce87 JQ	43	qemu_irq *pic;
	44	} PIIX3IrqState;
	45
0a3bacf3 JQ	46	struct PCII440FXState {
0a3bacf3 JQ	47	PCIDevice dev;
6c009fa4 JQ	48	target_phys_addr_t isa_page_descs[384 / 4];
6c009fa4 JQ	49	uint8_t smm_enabled;
867a0d7d	50	PIIX3IrqState *irq_state;
0a3bacf3 JQ	51	};
0a3bacf3 JQ	52
502a5395 PB	53	static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
	54	{
	55	I440FXState *s = opaque;
	56	s->config_reg = val;
	57	}
	58
	59	static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
	60	{
	61	I440FXState *s = opaque;
	62	return s->config_reg;
	63	}
	64
5d4e84c8	65	static void piix3_set_irq(void *opaque, int irq_num, int level);
d2b59317 PB	66
	67	/* return the global irq number corresponding to a given device irq
	68	pin. We could also use the bus number to have a more precise
	69	mapping. */
	70	static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
	71	{
	72	int slot_addend;
	73	slot_addend = (pci_dev->devfn >> 3) - 1;
	74	return (irq_num + slot_addend) & 3;
	75	}
502a5395	76
0a3bacf3	77	static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
84631fd7 FB	78	{
	79	uint32_t addr;
	80
	81	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	82	switch(r) {
	83	case 3:
	84	/* RAM */
5fafdf24	85	cpu_register_physical_memory(start, end - start,
84631fd7 FB	86	start);
	87	break;
	88	case 1:
	89	/* ROM (XXX: not quite correct) */
5fafdf24	90	cpu_register_physical_memory(start, end - start,
84631fd7 FB	91	start \| IO_MEM_ROM);
	92	break;
	93	case 2:
	94	case 0:
	95	/* XXX: should distinguish read/write cases */
	96	for(addr = start; addr < end; addr += 4096) {
5fafdf24	97	cpu_register_physical_memory(addr, 4096,
6c009fa4	98	d->isa_page_descs[(addr - 0xa0000) >> 12]);
84631fd7 FB	99	}
	100	break;
	101	}
	102	}
ee0ea1d0	103
0a3bacf3	104	static void i440fx_update_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	105	{
ee0ea1d0 FB	106	int i, r;
84631fd7 FB	107	uint32_t smram, addr;
84631fd7 FB	108
0a3bacf3	109	update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
84631fd7	110	for(i = 0; i < 12; i++) {
0a3bacf3	111	r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
84631fd7	112	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0	113	}
0a3bacf3	114	smram = d->dev.config[0x72];
6c009fa4	115	if ((d->smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
84631fd7 FB	116	cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
	117	} else {
	118	for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24	119	cpu_register_physical_memory(addr, 4096,
6c009fa4	120	d->isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0 FB	121	}
	122	}
	123	}
	124
0a3bacf3	125	void i440fx_set_smm(PCII440FXState *d, int val)
ee0ea1d0 FB	126	{
ee0ea1d0 FB	127	val = (val != 0);
6c009fa4 JQ	128	if (d->smm_enabled != val) {
6c009fa4 JQ	129	d->smm_enabled = val;
ee0ea1d0 FB	130	i440fx_update_memory_mappings(d);
	131	}
	132	}
	133
	134
	135	/* XXX: suppress when better memory API. We make the assumption that
	136	no device (in particular the VGA) changes the memory mappings in
	137	the 0xa0000-0x100000 range */
0a3bacf3	138	void i440fx_init_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	139	{
	140	int i;
	141	for(i = 0; i < 96; i++) {
6c009fa4	142	d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
ee0ea1d0 FB	143	}
	144	}
	145
0a3bacf3	146	static void i440fx_write_config(PCIDevice *dev,
ee0ea1d0 FB	147	uint32_t address, uint32_t val, int len)
ee0ea1d0 FB	148	{
0a3bacf3 JQ	149	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
0a3bacf3 JQ	150
ee0ea1d0	151	/* XXX: implement SMRAM.D_LOCK */
0a3bacf3	152	pci_default_write_config(dev, address, val, len);
84631fd7	153	if ((address >= 0x59 && address <= 0x5f) \|\| address == 0x72)
ee0ea1d0 FB	154	i440fx_update_memory_mappings(d);
	155	}
	156
0c7d19e5	157	static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
ee0ea1d0	158	{
0a3bacf3	159	PCII440FXState *d = opaque;
52fc1d83	160	int ret, i;
ee0ea1d0	161
0a3bacf3	162	ret = pci_device_load(&d->dev, f);
ee0ea1d0 FB	163	if (ret < 0)
	164	return ret;
	165	i440fx_update_memory_mappings(d);
6c009fa4	166	qemu_get_8s(f, &d->smm_enabled);
52fc1d83	167
da64182c	168	if (version_id == 2)
52fc1d83	169	for (i = 0; i < 4; i++)
8372615d	170	d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
52fc1d83	171
ee0ea1d0 FB	172	return 0;
	173	}
	174
752ff2fa	175	static int i440fx_post_load(void *opaque)
0c7d19e5 JQ	176	{
	177	PCII440FXState *d = opaque;
	178
	179	i440fx_update_memory_mappings(d);
	180	return 0;
	181	}
	182
	183	static const VMStateDescription vmstate_i440fx = {
	184	.name = "I440FX",
	185	.version_id = 3,
	186	.minimum_version_id = 3,
	187	.minimum_version_id_old = 1,
	188	.load_state_old = i440fx_load_old,
752ff2fa	189	.post_load = i440fx_post_load,
0c7d19e5 JQ	190	.fields = (VMStateField []) {
	191	VMSTATE_PCI_DEVICE(dev, PCII440FXState),
	192	VMSTATE_UINT8(smm_enabled, PCII440FXState),
	193	VMSTATE_END_OF_LIST()
	194	}
	195	};
	196
81a322d4	197	static int i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395	198	{
8a14daa5	199	I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395 PB	200
	201	register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
	202	register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
	203
	204	register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
	205	register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
	206	register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
	207	register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
	208	register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
	209	register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
81a322d4	210	return 0;
8a14daa5	211	}
502a5395	212
0a3bacf3	213	static int i440fx_initfn(PCIDevice *dev)
8a14daa5	214	{
0a3bacf3	215	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
ee0ea1d0	216
0a3bacf3 JQ	217	pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
	218	pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
	219	d->dev.config[0x08] = 0x02; // revision
	220	pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
	221	d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
	222
	223	d->dev.config[0x72] = 0x02; /* SMRAM */
ee0ea1d0	224
0c7d19e5	225	vmstate_register(0, &vmstate_i440fx, d);
81a322d4	226	return 0;
8a14daa5 GH	227	}
8a14daa5 GH	228
85a750ca	229	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix3_devfn, qemu_irq *pic)
8a14daa5 GH	230	{
	231	DeviceState *dev;
	232	PCIBus *b;
	233	PCIDevice *d;
	234	I440FXState *s;
bd7dce87	235	PIIX3IrqState irq_state = qemu_malloc(sizeof(irq_state));
8a14daa5	236
bd7dce87	237	irq_state->pic = pic;
8a14daa5 GH	238	dev = qdev_create(NULL, "i440FX-pcihost");
	239	s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
	240	b = pci_register_bus(&s->busdev.qdev, "pci.0",
bd7dce87	241	piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
8a14daa5 GH	242	s->bus = b;
	243	qdev_init(dev);
	244
	245	d = pci_create_simple(b, 0, "i440FX");
0a3bacf3	246	*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
867a0d7d	247	(*pi440fx_state)->irq_state = irq_state;
8a14daa5	248
fd83e9b9 JQ	249	irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
	250	pci_create_simple(b, -1, "PIIX3"));
	251	*piix3_devfn = irq_state->piix3->dev.devfn;
85a750ca	252
502a5395 PB	253	return b;
	254	}
	255
	256	/* PIIX3 PCI to ISA bridge */
	257
5d4e84c8	258	static void piix3_set_irq(void *opaque, int irq_num, int level)
502a5395	259	{
d2b59317	260	int i, pic_irq, pic_level;
bd7dce87	261	PIIX3IrqState *irq_state = opaque;
502a5395	262
8372615d	263	irq_state->piix3->pci_irq_levels[irq_num] = level;
502a5395 PB	264
	265	/* now we change the pic irq level according to the piix irq mappings */
	266	/* XXX: optimize */
fd83e9b9	267	pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
502a5395	268	if (pic_irq < 16) {
d2b59317	269	/* The pic level is the logical OR of all the PCI irqs mapped
502a5395 PB	270	to it */
502a5395 PB	271	pic_level = 0;
d2b59317	272	for (i = 0; i < 4; i++) {
fd83e9b9	273	if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
8372615d	274	pic_level \|= irq_state->piix3->pci_irq_levels[i];
d2b59317	275	}
bd7dce87	276	qemu_set_irq(irq_state->pic[pic_irq], pic_level);
502a5395 PB	277	}
	278	}
	279
15a1956a	280	static void piix3_reset(void *opaque)
502a5395	281	{
fd37d881 JQ	282	PIIX3State *d = opaque;
fd37d881 JQ	283	uint8_t *pci_conf = d->dev.config;
502a5395 PB	284
	285	pci_conf[0x04] = 0x07; // master, memory and I/O
	286	pci_conf[0x05] = 0x00;
	287	pci_conf[0x06] = 0x00;
	288	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	289	pci_conf[0x4c] = 0x4d;
	290	pci_conf[0x4e] = 0x03;
	291	pci_conf[0x4f] = 0x00;
	292	pci_conf[0x60] = 0x80;
477afee3 AJ	293	pci_conf[0x61] = 0x80;
	294	pci_conf[0x62] = 0x80;
	295	pci_conf[0x63] = 0x80;
502a5395 PB	296	pci_conf[0x69] = 0x02;
	297	pci_conf[0x70] = 0x80;
	298	pci_conf[0x76] = 0x0c;
	299	pci_conf[0x77] = 0x0c;
	300	pci_conf[0x78] = 0x02;
	301	pci_conf[0x79] = 0x00;
	302	pci_conf[0x80] = 0x00;
	303	pci_conf[0x82] = 0x00;
	304	pci_conf[0xa0] = 0x08;
502a5395 PB	305	pci_conf[0xa2] = 0x00;
	306	pci_conf[0xa3] = 0x00;
	307	pci_conf[0xa4] = 0x00;
	308	pci_conf[0xa5] = 0x00;
	309	pci_conf[0xa6] = 0x00;
	310	pci_conf[0xa7] = 0x00;
	311	pci_conf[0xa8] = 0x0f;
	312	pci_conf[0xaa] = 0x00;
	313	pci_conf[0xab] = 0x00;
	314	pci_conf[0xac] = 0x00;
	315	pci_conf[0xae] = 0x00;
15a1956a	316
8372615d	317	memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
502a5395 PB	318	}
502a5395 PB	319
d1f171bd JQ	320	static const VMStateDescription vmstate_piix3 = {
	321	.name = "PIIX3",
	322	.version_id = 3,
	323	.minimum_version_id = 2,
	324	.minimum_version_id_old = 2,
	325	.fields = (VMStateField []) {
	326	VMSTATE_PCI_DEVICE(dev, PIIX3State),
	327	VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
	328	VMSTATE_END_OF_LIST()
da64182c	329	}
d1f171bd	330	};
1941d19c	331
fd37d881	332	static int piix3_initfn(PCIDevice *dev)
502a5395	333	{
fd37d881	334	PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
502a5395 PB	335	uint8_t *pci_conf;
502a5395 PB	336
fd37d881	337	isa_bus_new(&d->dev.qdev);
d1f171bd	338	vmstate_register(0, &vmstate_piix3, d);
502a5395	339
fd37d881	340	pci_conf = d->dev.config;
deb54399 AL	341	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
deb54399 AL	342	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
173a543b	343	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
6407f373 IY	344	pci_conf[PCI_HEADER_TYPE] =
6407f373 IY	345	PCI_HEADER_TYPE_NORMAL \| PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
502a5395 PB	346
502a5395 PB	347	piix3_reset(d);
a08d4367	348	qemu_register_reset(piix3_reset, d);
81a322d4	349	return 0;
502a5395	350	}
5c2b87e3	351
8a14daa5 GH	352	static PCIDeviceInfo i440fx_info[] = {
	353	{
	354	.qdev.name = "i440FX",
	355	.qdev.desc = "Host bridge",
0a3bacf3	356	.qdev.size = sizeof(PCII440FXState),
8a14daa5 GH	357	.qdev.no_user = 1,
	358	.init = i440fx_initfn,
	359	.config_write = i440fx_write_config,
	360	},{
	361	.qdev.name = "PIIX3",
	362	.qdev.desc = "ISA bridge",
fd37d881	363	.qdev.size = sizeof(PIIX3State),
8a14daa5 GH	364	.qdev.no_user = 1,
8a14daa5 GH	365	.init = piix3_initfn,
8a14daa5 GH	366	},{
	367	/* end of list */
	368	}
	369	};
	370
	371	static SysBusDeviceInfo i440fx_pcihost_info = {
	372	.init = i440fx_pcihost_initfn,
	373	.qdev.name = "i440FX-pcihost",
	374	.qdev.size = sizeof(I440FXState),
	375	.qdev.no_user = 1,
	376	};
	377
	378	static void i440fx_register(void)
	379	{
	380	sysbus_register_withprop(&i440fx_pcihost_info);
	381	pci_qdev_register_many(i440fx_info);
	382	}
	383	device_init(i440fx_register);