[qemu.git] / target-cris / mmu.c

/*
 *  CRIS mmu emulation.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "mmu.h"

#ifdef DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x) do { } while (0)
#define D_LOG(...) do { } while (0)
#endif

void cris_mmu_init(CPUCRISState *env)
{
	env->mmu_rand_lfsr = 0xcccc;
}

#define SR_POLYNOM 0x8805
static inline unsigned int compute_polynom(unsigned int sr)
{
	unsigned int i;
	unsigned int f;

	f = 0;
	for (i = 0; i < 16; i++)
		f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);

	return f;
}

static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
{
	unsigned int f;

	/* Update lfsr at every fault.  */
	f = compute_polynom(env->mmu_rand_lfsr);
	env->mmu_rand_lfsr >>= 1;
	env->mmu_rand_lfsr |= (f << 15);
	env->mmu_rand_lfsr &= 0xffff;
}

static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
{
	return (rw_gc_cfg & 12) != 0;
}

static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
{
	return (1 << seg) & rw_mm_cfg;
}

static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
{
	uint32_t base;
	int i;

	if (seg < 8)
		base = env->sregs[SFR_RW_MM_KBASE_LO];
	else
		base = env->sregs[SFR_RW_MM_KBASE_HI];

	i = seg & 7;
	base >>= i * 4;
	base &= 15;

	base <<= 28;
	return base;
}
/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

static inline void set_field(uint32_t *dst, unsigned int val, 
			     unsigned int offset, unsigned int width)
{
	uint32_t mask;

	mask = (1 << width) - 1;
	mask <<= offset;
	val <<= offset;

	val &= mask;
	*dst &= ~(mask);
	*dst |= val;
}

#ifdef DEBUG
static void dump_tlb(CPUCRISState *env, int mmu)
{
	int set;
	int idx;
	uint32_t hi, lo, tlb_vpn, tlb_pfn;

	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
}
#endif

/* rw 0 = read, 1 = write, 2 = exec.  */
static int cris_mmu_translate_page(struct cris_mmu_result *res,
				   CPUCRISState *env, uint32_t vaddr,
				   int rw, int usermode, int debug)
{
	unsigned int vpage;
	unsigned int idx;
	uint32_t pid, lo, hi;
	uint32_t tlb_vpn, tlb_pfn = 0;
	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	int cfg_v, cfg_k, cfg_w, cfg_x;	
	int set, match = 0;
	uint32_t r_cause;
	uint32_t r_cfg;
	int rwcause;
	int mmu = 1; /* Data mmu is default.  */
	int vect_base;

	r_cause = env->sregs[SFR_R_MM_CAUSE];
	r_cfg = env->sregs[SFR_RW_MM_CFG];
	pid = env->pregs[PR_PID] & 0xff;

	switch (rw) {
		case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
		case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
		default:
		case 0: rwcause = CRIS_MMU_ERR_READ; break;
	}

	/* I exception vectors 4 - 7, D 8 - 11.  */
	vect_base = (mmu + 1) * 4;

	vpage = vaddr >> 13;

	/* We know the index which to check on each set.
	   Scan both I and D.  */
#if 0
	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
#endif

	idx = vpage & 15;
	for (set = 0; set < 4; set++)
	{
		lo = env->tlbsets[mmu][set][idx].lo;
		hi = env->tlbsets[mmu][set][idx].hi;

		tlb_vpn = hi >> 13;
		tlb_pid = EXTRACT_FIELD(hi, 0, 7);
		tlb_g  = EXTRACT_FIELD(lo, 4, 4);

		D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", 
			 mmu, set, idx, tlb_vpn, vpage, lo, hi);
		if ((tlb_g || (tlb_pid == pid))
		    && tlb_vpn == vpage) {
			match = 1;
			break;
		}
	}

	res->bf_vec = vect_base;
	if (match) {
		cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
		cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
		cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
		cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);

		tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
		tlb_v = EXTRACT_FIELD(lo, 3, 3);
		tlb_k = EXTRACT_FIELD(lo, 2, 2);
		tlb_w = EXTRACT_FIELD(lo, 1, 1);
		tlb_x = EXTRACT_FIELD(lo, 0, 0);

		/*
		set_exception_vector(0x04, i_mmu_refill);
		set_exception_vector(0x05, i_mmu_invalid);
		set_exception_vector(0x06, i_mmu_access);
		set_exception_vector(0x07, i_mmu_execute);
		set_exception_vector(0x08, d_mmu_refill);
		set_exception_vector(0x09, d_mmu_invalid);
		set_exception_vector(0x0a, d_mmu_access);
		set_exception_vector(0x0b, d_mmu_write);
		*/
		if (cfg_k && tlb_k && usermode) {
			D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 2;
		} else if (rw == 1 && cfg_w && !tlb_w) {
			D(printf ("tlb: write protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			/* write accesses never go through the I mmu.  */
			res->bf_vec = vect_base + 3;
		} else if (rw == 2 && cfg_x && !tlb_x) {
			D(printf ("tlb: exec protected %x lo=%x pc=%x\n", 
				 vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 3;
		} else if (cfg_v && !tlb_v) {
			D(printf ("tlb: invalid %x\n", vaddr));
			match = 0;
			res->bf_vec = vect_base + 1;
		}

		res->prot = 0;
		if (match) {
			res->prot |= PAGE_READ;
			if (tlb_w)
				res->prot |= PAGE_WRITE;
			if (mmu == 0 && (cfg_x || tlb_x))
				res->prot |= PAGE_EXEC;
		}
		else
			D(dump_tlb(env, mmu));
	} else {
		/* If refill, provide a randomized set.  */
		set = env->mmu_rand_lfsr & 3;
	}

	if (!match && !debug) {
		cris_mmu_update_rand_lfsr(env);

		/* Compute index.  */
		idx = vpage & 15;

		/* Update RW_MM_TLB_SEL.  */
		env->sregs[SFR_RW_MM_TLB_SEL] = 0;
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);

		/* Update RW_MM_CAUSE.  */
		set_field(&r_cause, rwcause, 8, 2);
		set_field(&r_cause, vpage, 13, 19);
		set_field(&r_cause, pid, 0, 8);
		env->sregs[SFR_R_MM_CAUSE] = r_cause;
		D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
	}

	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
		  " %x cause=%x sel=%x sp=%x %x %x\n",
		  __func__, rw, match, env->pc,
		  vaddr, vpage,
		  tlb_vpn, tlb_pfn, tlb_pid, 
		  pid,
		  r_cause,
		  env->sregs[SFR_RW_MM_TLB_SEL],
		  env->regs[R_SP], env->pregs[PR_USP], env->ksp));

	res->phy = tlb_pfn << TARGET_PAGE_BITS;
	return !match;
}

void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
{
    CRISCPU *cpu = cris_env_get_cpu(env);
	target_ulong vaddr;
	unsigned int idx;
	uint32_t lo, hi;
	uint32_t tlb_vpn;
	int tlb_pid, tlb_g, tlb_v;
	unsigned int set;
	unsigned int mmu;

	pid &= 0xff;
	for (mmu = 0; mmu < 2; mmu++) {
		for (set = 0; set < 4; set++)
		{
			for (idx = 0; idx < 16; idx++) {
				lo = env->tlbsets[mmu][set][idx].lo;
				hi = env->tlbsets[mmu][set][idx].hi;
				
				tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
				tlb_pid = EXTRACT_FIELD(hi, 0, 7);
				tlb_g  = EXTRACT_FIELD(lo, 4, 4);
				tlb_v = EXTRACT_FIELD(lo, 3, 3);

				if (tlb_v && !tlb_g && (tlb_pid == pid)) {
					vaddr = tlb_vpn << TARGET_PAGE_BITS;
					D_LOG("flush pid=%x vaddr=%x\n", 
						  pid, vaddr);
                    tlb_flush_page(CPU(cpu), vaddr);
				}
			}
		}
	}
}

int cris_mmu_translate(struct cris_mmu_result *res,
		       CPUCRISState *env, uint32_t vaddr,
		       int rw, int mmu_idx, int debug)
{
	int seg;
	int miss = 0;
	int is_user = mmu_idx == MMU_USER_IDX;
	uint32_t old_srs;

	old_srs= env->pregs[PR_SRS];

	/* rw == 2 means exec, map the access to the insn mmu.  */
	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;

	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
		res->phy = vaddr;
		res->prot = PAGE_BITS;
		goto done;
	}

	seg = vaddr >> 28;
	if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	{
		uint32_t base;

		miss = 0;
		base = cris_mmu_translate_seg(env, seg);
                res->phy = base | (0x0fffffff & vaddr);
		res->prot = PAGE_BITS;
	} else {
		miss = cris_mmu_translate_page(res, env, vaddr, rw,
					       is_user, debug);
	}
  done:
	env->pregs[PR_SRS] = old_srs;
	return miss;
}
Commit	Line	Data
94cff60a TS	1	/*
	2	* CRIS mmu emulation.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
94cff60a TS	19	*/
94cff60a TS	20
66d79920	21	#include "qemu/osdep.h"
94cff60a TS	22	#include "cpu.h"
94cff60a TS	23	#include "mmu.h"
94cff60a	24
d297f464 EI	25	#ifdef DEBUG
d297f464 EI	26	#define D(x) x
02021c3f	27	#define D_LOG(...) qemu_log(__VA_ARGS__)
d297f464	28	#else
3ffd710e	29	#define D(x) do { } while (0)
d12d51d5	30	#define D_LOG(...) do { } while (0)
d297f464	31	#endif
94cff60a	32
a1170bfd	33	void cris_mmu_init(CPUCRISState *env)
44cd42ee EI	34	{
	35	env->mmu_rand_lfsr = 0xcccc;
	36	}
	37
	38	#define SR_POLYNOM 0x8805
	39	static inline unsigned int compute_polynom(unsigned int sr)
	40	{
	41	unsigned int i;
	42	unsigned int f;
	43
	44	f = 0;
	45	for (i = 0; i < 16; i++)
	46	f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
	47
	48	return f;
	49	}
	50
a1170bfd	51	static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
253248a3 EI	52	{
	53	unsigned int f;
	54
	55	/* Update lfsr at every fault. */
	56	f = compute_polynom(env->mmu_rand_lfsr);
	57	env->mmu_rand_lfsr >>= 1;
	58	env->mmu_rand_lfsr \|= (f << 15);
	59	env->mmu_rand_lfsr &= 0xffff;
	60	}
	61
ef29a70d	62	static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
94cff60a TS	63	{
	64	return (rw_gc_cfg & 12) != 0;
	65	}
	66
ef29a70d	67	static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
94cff60a TS	68	{
	69	return (1 << seg) & rw_mm_cfg;
	70	}
	71
a1170bfd	72	static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
94cff60a TS	73	{
	74	uint32_t base;
	75	int i;
	76
	77	if (seg < 8)
	78	base = env->sregs[SFR_RW_MM_KBASE_LO];
	79	else
	80	base = env->sregs[SFR_RW_MM_KBASE_HI];
	81
	82	i = seg & 7;
	83	base >>= i * 4;
	84	base &= 15;
	85
	86	base <<= 28;
	87	return base;
	88	}
	89	/* Used by the tlb decoder. */
	90	#define EXTRACT_FIELD(src, start, end) \
786c02f1 EI	91	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	92
	93	static inline void set_field(uint32_t *dst, unsigned int val,
	94	unsigned int offset, unsigned int width)
	95	{
	96	uint32_t mask;
	97
	98	mask = (1 << width) - 1;
	99	mask <<= offset;
	100	val <<= offset;
	101
	102	val &= mask;
786c02f1 EI	103	*dst &= ~(mask);
	104	*dst \|= val;
	105	}
94cff60a	106
d297f464	107	#ifdef DEBUG
a1170bfd	108	static void dump_tlb(CPUCRISState *env, int mmu)
b41f7df0 EI	109	{
	110	int set;
	111	int idx;
	112	uint32_t hi, lo, tlb_vpn, tlb_pfn;
	113
	114	for (set = 0; set < 4; set++) {
	115	for (idx = 0; idx < 16; idx++) {
	116	lo = env->tlbsets[mmu][set][idx].lo;
	117	hi = env->tlbsets[mmu][set][idx].hi;
	118	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	119	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	120
	121	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
	122	set, idx, hi, lo, tlb_vpn, tlb_pfn);
	123	}
	124	}
	125	}
d297f464	126	#endif
b41f7df0 EI	127
b41f7df0 EI	128	/* rw 0 = read, 1 = write, 2 = exec. */
2fa73ec8	129	static int cris_mmu_translate_page(struct cris_mmu_result *res,
a1170bfd	130	CPUCRISState *env, uint32_t vaddr,
9f5a1fae	131	int rw, int usermode, int debug)
94cff60a TS	132	{
	133	unsigned int vpage;
	134	unsigned int idx;
b23761f9	135	uint32_t pid, lo, hi;
786c02f1 EI	136	uint32_t tlb_vpn, tlb_pfn = 0;
	137	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	138	int cfg_v, cfg_k, cfg_w, cfg_x;
b41f7df0	139	int set, match = 0;
786c02f1 EI	140	uint32_t r_cause;
	141	uint32_t r_cfg;
	142	int rwcause;
b41f7df0 EI	143	int mmu = 1; /* Data mmu is default. */
b41f7df0 EI	144	int vect_base;
786c02f1 EI	145
	146	r_cause = env->sregs[SFR_R_MM_CAUSE];
	147	r_cfg = env->sregs[SFR_RW_MM_CFG];
28de16da	148	pid = env->pregs[PR_PID] & 0xff;
b41f7df0 EI	149
	150	switch (rw) {
	151	case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
	152	case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
	153	default:
	154	case 0: rwcause = CRIS_MMU_ERR_READ; break;
	155	}
	156
	157	/* I exception vectors 4 - 7, D 8 - 11. */
	158	vect_base = (mmu + 1) * 4;
94cff60a TS	159
94cff60a TS	160	vpage = vaddr >> 13;
94cff60a TS	161
	162	/* We know the index which to check on each set.
	163	Scan both I and D. */
786c02f1	164	#if 0
b41f7df0 EI	165	for (set = 0; set < 4; set++) {
	166	for (idx = 0; idx < 16; idx++) {
	167	lo = env->tlbsets[mmu][set][idx].lo;
	168	hi = env->tlbsets[mmu][set][idx].hi;
786c02f1 EI	169	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	170	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	171
	172	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
b41f7df0	173	set, idx, hi, lo, tlb_vpn, tlb_pfn);
786c02f1 EI	174	}
	175	}
	176	#endif
b41f7df0 EI	177
	178	idx = vpage & 15;
	179	for (set = 0; set < 4; set++)
94cff60a	180	{
b41f7df0 EI	181	lo = env->tlbsets[mmu][set][idx].lo;
b41f7df0 EI	182	hi = env->tlbsets[mmu][set][idx].hi;
94cff60a	183
b23761f9	184	tlb_vpn = hi >> 13;
44cd42ee	185	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
44cd42ee	186	tlb_g = EXTRACT_FIELD(lo, 4, 4);
94cff60a	187
d12d51d5 AL	188	D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
d12d51d5 AL	189	mmu, set, idx, tlb_vpn, vpage, lo, hi);
b23761f9	190	if ((tlb_g \|\| (tlb_pid == pid))
44cd42ee	191	&& tlb_vpn == vpage) {
94cff60a TS	192	match = 1;
	193	break;
	194	}
	195	}
	196
b41f7df0	197	res->bf_vec = vect_base;
94cff60a	198	if (match) {
786c02f1 EI	199	cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
	200	cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
	201	cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
	202	cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
	203
786c02f1	204	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
786c02f1 EI	205	tlb_v = EXTRACT_FIELD(lo, 3, 3);
	206	tlb_k = EXTRACT_FIELD(lo, 2, 2);
	207	tlb_w = EXTRACT_FIELD(lo, 1, 1);
	208	tlb_x = EXTRACT_FIELD(lo, 0, 0);
	209
	210	/*
	211	set_exception_vector(0x04, i_mmu_refill);
	212	set_exception_vector(0x05, i_mmu_invalid);
	213	set_exception_vector(0x06, i_mmu_access);
	214	set_exception_vector(0x07, i_mmu_execute);
	215	set_exception_vector(0x08, d_mmu_refill);
	216	set_exception_vector(0x09, d_mmu_invalid);
	217	set_exception_vector(0x0a, d_mmu_access);
	218	set_exception_vector(0x0b, d_mmu_write);
	219	*/
44cd42ee	220	if (cfg_k && tlb_k && usermode) {
ef29a70d EI	221	D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
	222	vaddr, lo, env->pc));
	223	match = 0;
	224	res->bf_vec = vect_base + 2;
b41f7df0	225	} else if (rw == 1 && cfg_w && !tlb_w) {
ef29a70d EI	226	D(printf ("tlb: write protected %x lo=%x pc=%x\n",
	227	vaddr, lo, env->pc));
	228	match = 0;
	229	/* write accesses never go through the I mmu. */
	230	res->bf_vec = vect_base + 3;
	231	} else if (rw == 2 && cfg_x && !tlb_x) {
	232	D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
	233	vaddr, lo, env->pc));
786c02f1	234	match = 0;
b41f7df0 EI	235	res->bf_vec = vect_base + 3;
	236	} else if (cfg_v && !tlb_v) {
	237	D(printf ("tlb: invalid %x\n", vaddr));
786c02f1	238	match = 0;
b41f7df0	239	res->bf_vec = vect_base + 1;
786c02f1	240	}
786c02f1	241
b41f7df0 EI	242	res->prot = 0;
	243	if (match) {
	244	res->prot \|= PAGE_READ;
	245	if (tlb_w)
	246	res->prot \|= PAGE_WRITE;
58aebb94	247	if (mmu == 0 && (cfg_x \|\| tlb_x))
b41f7df0 EI	248	res->prot \|= PAGE_EXEC;
	249	}
	250	else
	251	D(dump_tlb(env, mmu));
44cd42ee EI	252	} else {
	253	/* If refill, provide a randomized set. */
	254	set = env->mmu_rand_lfsr & 3;
786c02f1 EI	255	}
786c02f1 EI	256
9f5a1fae	257	if (!match && !debug) {
253248a3 EI	258	cris_mmu_update_rand_lfsr(env);
253248a3 EI	259
44cd42ee	260	/* Compute index. */
b41f7df0	261	idx = vpage & 15;
b41f7df0 EI	262
	263	/* Update RW_MM_TLB_SEL. */
	264	env->sregs[SFR_RW_MM_TLB_SEL] = 0;
	265	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
44cd42ee	266	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
b41f7df0 EI	267
	268	/* Update RW_MM_CAUSE. */
	269	set_field(&r_cause, rwcause, 8, 2);
786c02f1	270	set_field(&r_cause, vpage, 13, 19);
28de16da	271	set_field(&r_cause, pid, 0, 8);
786c02f1	272	env->sregs[SFR_R_MM_CAUSE] = r_cause;
b41f7df0	273	D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
94cff60a	274	}
b41f7df0	275
b41f7df0 EI	276	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
	277	" %x cause=%x sel=%x sp=%x %x %x\n",
	278	__func__, rw, match, env->pc,
786c02f1 EI	279	vaddr, vpage,
786c02f1 EI	280	tlb_vpn, tlb_pfn, tlb_pid,
28de16da	281	pid,
786c02f1 EI	282	r_cause,
786c02f1 EI	283	env->sregs[SFR_RW_MM_TLB_SEL],
b41f7df0	284	env->regs[R_SP], env->pregs[PR_USP], env->ksp));
786c02f1	285
bf91ada5	286	res->phy = tlb_pfn << TARGET_PAGE_BITS;
94cff60a TS	287	return !match;
	288	}
	289
a1170bfd	290	void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
786c02f1	291	{
31b030d4	292	CRISCPU *cpu = cris_env_get_cpu(env);
cf1d97f0 EI	293	target_ulong vaddr;
	294	unsigned int idx;
	295	uint32_t lo, hi;
	296	uint32_t tlb_vpn;
80e1b265	297	int tlb_pid, tlb_g, tlb_v;
cf1d97f0 EI	298	unsigned int set;
	299	unsigned int mmu;
	300
	301	pid &= 0xff;
	302	for (mmu = 0; mmu < 2; mmu++) {
	303	for (set = 0; set < 4; set++)
	304	{
	305	for (idx = 0; idx < 16; idx++) {
	306	lo = env->tlbsets[mmu][set][idx].lo;
	307	hi = env->tlbsets[mmu][set][idx].hi;
	308
	309	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	310	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
	311	tlb_g = EXTRACT_FIELD(lo, 4, 4);
	312	tlb_v = EXTRACT_FIELD(lo, 3, 3);
cf1d97f0	313
80e1b265	314	if (tlb_v && !tlb_g && (tlb_pid == pid)) {
cf1d97f0	315	vaddr = tlb_vpn << TARGET_PAGE_BITS;
d12d51d5 AL	316	D_LOG("flush pid=%x vaddr=%x\n",
d12d51d5 AL	317	pid, vaddr);
31b030d4	318	tlb_flush_page(CPU(cpu), vaddr);
cf1d97f0 EI	319	}
	320	}
	321	}
	322	}
786c02f1 EI	323	}
786c02f1 EI	324
2fa73ec8	325	int cris_mmu_translate(struct cris_mmu_result *res,
a1170bfd	326	CPUCRISState *env, uint32_t vaddr,
9f5a1fae	327	int rw, int mmu_idx, int debug)
94cff60a	328	{
94cff60a TS	329	int seg;
94cff60a TS	330	int miss = 0;
786c02f1	331	int is_user = mmu_idx == MMU_USER_IDX;
b41f7df0 EI	332	uint32_t old_srs;
	333
	334	old_srs= env->pregs[PR_SRS];
	335
	336	/* rw == 2 means exec, map the access to the insn mmu. */
	337	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
94cff60a TS	338
	339	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
	340	res->phy = vaddr;
b23761f9	341	res->prot = PAGE_BITS;
b41f7df0	342	goto done;
94cff60a TS	343	}
	344
	345	seg = vaddr >> 28;
218951ef	346	if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
94cff60a TS	347	{
	348	uint32_t base;
	349
	350	miss = 0;
	351	base = cris_mmu_translate_seg(env, seg);
0d84be5b	352	res->phy = base \| (0x0fffffff & vaddr);
b23761f9	353	res->prot = PAGE_BITS;
9f5a1fae EI	354	} else {
	355	miss = cris_mmu_translate_page(res, env, vaddr, rw,
	356	is_user, debug);
94cff60a	357	}
b41f7df0 EI	358	done:
b41f7df0 EI	359	env->pregs[PR_SRS] = old_srs;
94cff60a TS	360	return miss;
94cff60a TS	361	}