[qemu.git] / target-cris / mmu.c

/*
 *  CRIS mmu emulation.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef CONFIG_USER_ONLY

#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "config.h"
#include "cpu.h"
#include "mmu.h"
#include "exec-all.h"

#ifdef DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x) do { } while (0)
#define D_LOG(...) do { } while (0)
#endif

void cris_mmu_init(CPUState *env)
{
	env->mmu_rand_lfsr = 0xcccc;
}

#define SR_POLYNOM 0x8805
static inline unsigned int compute_polynom(unsigned int sr)
{
	unsigned int i;
	unsigned int f;

	f = 0;
	for (i = 0; i < 16; i++)
		f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);

	return f;
}

static void cris_mmu_update_rand_lfsr(CPUState *env)
{
	unsigned int f;

	/* Update lfsr at every fault.  */
	f = compute_polynom(env->mmu_rand_lfsr);
	env->mmu_rand_lfsr >>= 1;
	env->mmu_rand_lfsr |= (f << 15);
	env->mmu_rand_lfsr &= 0xffff;
}

static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
{
	return (rw_gc_cfg & 12) != 0;
}

static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
{
	return (1 << seg) & rw_mm_cfg;
}

static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
{
	uint32_t base;
	int i;

	if (seg < 8)
		base = env->sregs[SFR_RW_MM_KBASE_LO];
	else
		base = env->sregs[SFR_RW_MM_KBASE_HI];

	i = seg & 7;
	base >>= i * 4;
	base &= 15;

	base <<= 28;
	return base;
}
/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

static inline void set_field(uint32_t *dst, unsigned int val, 
			     unsigned int offset, unsigned int width)
{
	uint32_t mask;

	mask = (1 << width) - 1;
	mask <<= offset;
	val <<= offset;

	val &= mask;
	*dst &= ~(mask);
	*dst |= val;
}

#ifdef DEBUG
static void dump_tlb(CPUState *env, int mmu)
{
	int set;
	int idx;
	uint32_t hi, lo, tlb_vpn, tlb_pfn;

	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
}
#endif

/* rw 0 = read, 1 = write, 2 = exec.  */
static int cris_mmu_translate_page(struct cris_mmu_result *res,
				   CPUState *env, uint32_t vaddr,
				   int rw, int usermode, int debug)
{
	unsigned int vpage;
	unsigned int idx;
	uint32_t pid, lo, hi;
	uint32_t tlb_vpn, tlb_pfn = 0;
	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	int cfg_v, cfg_k, cfg_w, cfg_x;	
	int set, match = 0;
	uint32_t r_cause;
	uint32_t r_cfg;
	int rwcause;
	int mmu = 1; /* Data mmu is default.  */
	int vect_base;

	r_cause = env->sregs[SFR_R_MM_CAUSE];
	r_cfg = env->sregs[SFR_RW_MM_CFG];
	pid = env->pregs[PR_PID] & 0xff;

	switch (rw) {
		case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
		case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
		default:
		case 0: rwcause = CRIS_MMU_ERR_READ; break;
	}

	/* I exception vectors 4 - 7, D 8 - 11.  */
	vect_base = (mmu + 1) * 4;

	vpage = vaddr >> 13;

	/* We know the index which to check on each set.
	   Scan both I and D.  */
#if 0
	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
#endif

	idx = vpage & 15;
	for (set = 0; set < 4; set++)
	{
		lo = env->tlbsets[mmu][set][idx].lo;
		hi = env->tlbsets[mmu][set][idx].hi;

		tlb_vpn = hi >> 13;
		tlb_pid = EXTRACT_FIELD(hi, 0, 7);
		tlb_g  = EXTRACT_FIELD(lo, 4, 4);

		D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", 
			 mmu, set, idx, tlb_vpn, vpage, lo, hi);
		if ((tlb_g || (tlb_pid == pid))
		    && tlb_vpn == vpage) {
			match = 1;
			break;
		}
	}

	res->bf_vec = vect_base;
	if (match) {
		cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
		cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
		cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
		cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);

		tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
		tlb_v = EXTRACT_FIELD(lo, 3, 3);
		tlb_k = EXTRACT_FIELD(lo, 2, 2);
		tlb_w = EXTRACT_FIELD(lo, 1, 1);
		tlb_x = EXTRACT_FIELD(lo, 0, 0);

		/*
		set_exception_vector(0x04, i_mmu_refill);
		set_exception_vector(0x05, i_mmu_invalid);
		set_exception_vector(0x06, i_mmu_access);
		set_exception_vector(0x07, i_mmu_execute);
		set_exception_vector(0x08, d_mmu_refill);
		set_exception_vector(0x09, d_mmu_invalid);
		set_exception_vector(0x0a, d_mmu_access);
		set_exception_vector(0x0b, d_mmu_write);
		*/
		if (cfg_k && tlb_k && usermode) {
			D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 2;
		} else if (rw == 1 && cfg_w && !tlb_w) {
			D(printf ("tlb: write protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			/* write accesses never go through the I mmu.  */
			res->bf_vec = vect_base + 3;
		} else if (rw == 2 && cfg_x && !tlb_x) {
			D(printf ("tlb: exec protected %x lo=%x pc=%x\n", 
				 vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 3;
		} else if (cfg_v && !tlb_v) {
			D(printf ("tlb: invalid %x\n", vaddr));
			match = 0;
			res->bf_vec = vect_base + 1;
		}

		res->prot = 0;
		if (match) {
			res->prot |= PAGE_READ;
			if (tlb_w)
				res->prot |= PAGE_WRITE;
			if (tlb_x)
				res->prot |= PAGE_EXEC;
		}
		else
			D(dump_tlb(env, mmu));
	} else {
		/* If refill, provide a randomized set.  */
		set = env->mmu_rand_lfsr & 3;
	}

	if (!match && !debug) {
		cris_mmu_update_rand_lfsr(env);

		/* Compute index.  */
		idx = vpage & 15;

		/* Update RW_MM_TLB_SEL.  */
		env->sregs[SFR_RW_MM_TLB_SEL] = 0;
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);

		/* Update RW_MM_CAUSE.  */
		set_field(&r_cause, rwcause, 8, 2);
		set_field(&r_cause, vpage, 13, 19);
		set_field(&r_cause, pid, 0, 8);
		env->sregs[SFR_R_MM_CAUSE] = r_cause;
		D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
	}

	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
		  " %x cause=%x sel=%x sp=%x %x %x\n",
		  __func__, rw, match, env->pc,
		  vaddr, vpage,
		  tlb_vpn, tlb_pfn, tlb_pid, 
		  pid,
		  r_cause,
		  env->sregs[SFR_RW_MM_TLB_SEL],
		  env->regs[R_SP], env->pregs[PR_USP], env->ksp));

	res->phy = tlb_pfn << TARGET_PAGE_BITS;
	return !match;
}

void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
{
	target_ulong vaddr;
	unsigned int idx;
	uint32_t lo, hi;
	uint32_t tlb_vpn;
	int tlb_pid, tlb_g, tlb_v;
	unsigned int set;
	unsigned int mmu;

	pid &= 0xff;
	for (mmu = 0; mmu < 2; mmu++) {
		for (set = 0; set < 4; set++)
		{
			for (idx = 0; idx < 16; idx++) {
				lo = env->tlbsets[mmu][set][idx].lo;
				hi = env->tlbsets[mmu][set][idx].hi;
				
				tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
				tlb_pid = EXTRACT_FIELD(hi, 0, 7);
				tlb_g  = EXTRACT_FIELD(lo, 4, 4);
				tlb_v = EXTRACT_FIELD(lo, 3, 3);

				if (tlb_v && !tlb_g && (tlb_pid == pid)) {
					vaddr = tlb_vpn << TARGET_PAGE_BITS;
					D_LOG("flush pid=%x vaddr=%x\n", 
						  pid, vaddr);
					tlb_flush_page(env, vaddr);
				}
			}
		}
	}
}

int cris_mmu_translate(struct cris_mmu_result *res,
		       CPUState *env, uint32_t vaddr,
		       int rw, int mmu_idx, int debug)
{
	int seg;
	int miss = 0;
	int is_user = mmu_idx == MMU_USER_IDX;
	uint32_t old_srs;

	old_srs= env->pregs[PR_SRS];

	/* rw == 2 means exec, map the access to the insn mmu.  */
	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;

	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
		res->phy = vaddr;
		res->prot = PAGE_BITS;
		goto done;
	}

	seg = vaddr >> 28;
	if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	{
		uint32_t base;

		miss = 0;
		base = cris_mmu_translate_seg(env, seg);
                res->phy = base | (0x0fffffff & vaddr);
		res->prot = PAGE_BITS;
	} else {
		miss = cris_mmu_translate_page(res, env, vaddr, rw,
					       is_user, debug);
	}
  done:
	env->pregs[PR_SRS] = old_srs;
	return miss;
}
#endif
Commit	Line	Data
94cff60a TS	1	/*
	2	* CRIS mmu emulation.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
94cff60a TS	19	*/
	20
	21	#ifndef CONFIG_USER_ONLY
	22
	23	#include <stdio.h>
	24	#include <string.h>
	25	#include <stdlib.h>
	26
	27	#include "config.h"
	28	#include "cpu.h"
	29	#include "mmu.h"
	30	#include "exec-all.h"
	31
d297f464 EI	32	#ifdef DEBUG
d297f464 EI	33	#define D(x) x
02021c3f	34	#define D_LOG(...) qemu_log(__VA_ARGS__)
d297f464	35	#else
3ffd710e	36	#define D(x) do { } while (0)
d12d51d5	37	#define D_LOG(...) do { } while (0)
d297f464	38	#endif
94cff60a	39
44cd42ee EI	40	void cris_mmu_init(CPUState *env)
	41	{
	42	env->mmu_rand_lfsr = 0xcccc;
	43	}
	44
	45	#define SR_POLYNOM 0x8805
	46	static inline unsigned int compute_polynom(unsigned int sr)
	47	{
	48	unsigned int i;
	49	unsigned int f;
	50
	51	f = 0;
	52	for (i = 0; i < 16; i++)
	53	f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
	54
	55	return f;
	56	}
	57
253248a3 EI	58	static void cris_mmu_update_rand_lfsr(CPUState *env)
	59	{
	60	unsigned int f;
	61
	62	/* Update lfsr at every fault. */
	63	f = compute_polynom(env->mmu_rand_lfsr);
	64	env->mmu_rand_lfsr >>= 1;
	65	env->mmu_rand_lfsr \|= (f << 15);
	66	env->mmu_rand_lfsr &= 0xffff;
	67	}
	68
ef29a70d	69	static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
94cff60a TS	70	{
	71	return (rw_gc_cfg & 12) != 0;
	72	}
	73
ef29a70d	74	static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
94cff60a TS	75	{
	76	return (1 << seg) & rw_mm_cfg;
	77	}
	78
	79	static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
	80	{
	81	uint32_t base;
	82	int i;
	83
	84	if (seg < 8)
	85	base = env->sregs[SFR_RW_MM_KBASE_LO];
	86	else
	87	base = env->sregs[SFR_RW_MM_KBASE_HI];
	88
	89	i = seg & 7;
	90	base >>= i * 4;
	91	base &= 15;
	92
	93	base <<= 28;
	94	return base;
	95	}
	96	/* Used by the tlb decoder. */
	97	#define EXTRACT_FIELD(src, start, end) \
786c02f1 EI	98	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	99
	100	static inline void set_field(uint32_t *dst, unsigned int val,
	101	unsigned int offset, unsigned int width)
	102	{
	103	uint32_t mask;
	104
	105	mask = (1 << width) - 1;
	106	mask <<= offset;
	107	val <<= offset;
	108
	109	val &= mask;
786c02f1 EI	110	*dst &= ~(mask);
	111	*dst \|= val;
	112	}
94cff60a	113
d297f464	114	#ifdef DEBUG
b41f7df0 EI	115	static void dump_tlb(CPUState *env, int mmu)
	116	{
	117	int set;
	118	int idx;
	119	uint32_t hi, lo, tlb_vpn, tlb_pfn;
	120
	121	for (set = 0; set < 4; set++) {
	122	for (idx = 0; idx < 16; idx++) {
	123	lo = env->tlbsets[mmu][set][idx].lo;
	124	hi = env->tlbsets[mmu][set][idx].hi;
	125	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	126	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	127
	128	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
	129	set, idx, hi, lo, tlb_vpn, tlb_pfn);
	130	}
	131	}
	132	}
d297f464	133	#endif
b41f7df0 EI	134
b41f7df0 EI	135	/* rw 0 = read, 1 = write, 2 = exec. */
2fa73ec8	136	static int cris_mmu_translate_page(struct cris_mmu_result *res,
94cff60a	137	CPUState *env, uint32_t vaddr,
9f5a1fae	138	int rw, int usermode, int debug)
94cff60a TS	139	{
	140	unsigned int vpage;
	141	unsigned int idx;
b23761f9	142	uint32_t pid, lo, hi;
786c02f1 EI	143	uint32_t tlb_vpn, tlb_pfn = 0;
	144	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	145	int cfg_v, cfg_k, cfg_w, cfg_x;
b41f7df0	146	int set, match = 0;
786c02f1 EI	147	uint32_t r_cause;
	148	uint32_t r_cfg;
	149	int rwcause;
b41f7df0 EI	150	int mmu = 1; /* Data mmu is default. */
b41f7df0 EI	151	int vect_base;
786c02f1 EI	152
	153	r_cause = env->sregs[SFR_R_MM_CAUSE];
	154	r_cfg = env->sregs[SFR_RW_MM_CFG];
28de16da	155	pid = env->pregs[PR_PID] & 0xff;
b41f7df0 EI	156
	157	switch (rw) {
	158	case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
	159	case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
	160	default:
	161	case 0: rwcause = CRIS_MMU_ERR_READ; break;
	162	}
	163
	164	/* I exception vectors 4 - 7, D 8 - 11. */
	165	vect_base = (mmu + 1) * 4;
94cff60a TS	166
94cff60a TS	167	vpage = vaddr >> 13;
94cff60a TS	168
	169	/* We know the index which to check on each set.
	170	Scan both I and D. */
786c02f1	171	#if 0
b41f7df0 EI	172	for (set = 0; set < 4; set++) {
	173	for (idx = 0; idx < 16; idx++) {
	174	lo = env->tlbsets[mmu][set][idx].lo;
	175	hi = env->tlbsets[mmu][set][idx].hi;
786c02f1 EI	176	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	177	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	178
	179	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
b41f7df0	180	set, idx, hi, lo, tlb_vpn, tlb_pfn);
786c02f1 EI	181	}
	182	}
	183	#endif
b41f7df0 EI	184
	185	idx = vpage & 15;
	186	for (set = 0; set < 4; set++)
94cff60a	187	{
b41f7df0 EI	188	lo = env->tlbsets[mmu][set][idx].lo;
b41f7df0 EI	189	hi = env->tlbsets[mmu][set][idx].hi;
94cff60a	190
b23761f9	191	tlb_vpn = hi >> 13;
44cd42ee	192	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
44cd42ee	193	tlb_g = EXTRACT_FIELD(lo, 4, 4);
94cff60a	194
d12d51d5 AL	195	D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
d12d51d5 AL	196	mmu, set, idx, tlb_vpn, vpage, lo, hi);
b23761f9	197	if ((tlb_g \|\| (tlb_pid == pid))
44cd42ee	198	&& tlb_vpn == vpage) {
94cff60a TS	199	match = 1;
	200	break;
	201	}
	202	}
	203
b41f7df0	204	res->bf_vec = vect_base;
94cff60a	205	if (match) {
786c02f1 EI	206	cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
	207	cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
	208	cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
	209	cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
	210
786c02f1	211	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
786c02f1 EI	212	tlb_v = EXTRACT_FIELD(lo, 3, 3);
	213	tlb_k = EXTRACT_FIELD(lo, 2, 2);
	214	tlb_w = EXTRACT_FIELD(lo, 1, 1);
	215	tlb_x = EXTRACT_FIELD(lo, 0, 0);
	216
	217	/*
	218	set_exception_vector(0x04, i_mmu_refill);
	219	set_exception_vector(0x05, i_mmu_invalid);
	220	set_exception_vector(0x06, i_mmu_access);
	221	set_exception_vector(0x07, i_mmu_execute);
	222	set_exception_vector(0x08, d_mmu_refill);
	223	set_exception_vector(0x09, d_mmu_invalid);
	224	set_exception_vector(0x0a, d_mmu_access);
	225	set_exception_vector(0x0b, d_mmu_write);
	226	*/
44cd42ee	227	if (cfg_k && tlb_k && usermode) {
ef29a70d EI	228	D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
	229	vaddr, lo, env->pc));
	230	match = 0;
	231	res->bf_vec = vect_base + 2;
b41f7df0	232	} else if (rw == 1 && cfg_w && !tlb_w) {
ef29a70d EI	233	D(printf ("tlb: write protected %x lo=%x pc=%x\n",
	234	vaddr, lo, env->pc));
	235	match = 0;
	236	/* write accesses never go through the I mmu. */
	237	res->bf_vec = vect_base + 3;
	238	} else if (rw == 2 && cfg_x && !tlb_x) {
	239	D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
	240	vaddr, lo, env->pc));
786c02f1	241	match = 0;
b41f7df0 EI	242	res->bf_vec = vect_base + 3;
	243	} else if (cfg_v && !tlb_v) {
	244	D(printf ("tlb: invalid %x\n", vaddr));
786c02f1	245	match = 0;
b41f7df0	246	res->bf_vec = vect_base + 1;
786c02f1	247	}
786c02f1	248
b41f7df0 EI	249	res->prot = 0;
	250	if (match) {
	251	res->prot \|= PAGE_READ;
	252	if (tlb_w)
	253	res->prot \|= PAGE_WRITE;
	254	if (tlb_x)
	255	res->prot \|= PAGE_EXEC;
	256	}
	257	else
	258	D(dump_tlb(env, mmu));
44cd42ee EI	259	} else {
	260	/* If refill, provide a randomized set. */
	261	set = env->mmu_rand_lfsr & 3;
786c02f1 EI	262	}
786c02f1 EI	263
9f5a1fae	264	if (!match && !debug) {
253248a3 EI	265	cris_mmu_update_rand_lfsr(env);
253248a3 EI	266
44cd42ee	267	/* Compute index. */
b41f7df0	268	idx = vpage & 15;
b41f7df0 EI	269
	270	/* Update RW_MM_TLB_SEL. */
	271	env->sregs[SFR_RW_MM_TLB_SEL] = 0;
	272	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
44cd42ee	273	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
b41f7df0 EI	274
	275	/* Update RW_MM_CAUSE. */
	276	set_field(&r_cause, rwcause, 8, 2);
786c02f1	277	set_field(&r_cause, vpage, 13, 19);
28de16da	278	set_field(&r_cause, pid, 0, 8);
786c02f1	279	env->sregs[SFR_R_MM_CAUSE] = r_cause;
b41f7df0	280	D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
94cff60a	281	}
b41f7df0	282
b41f7df0 EI	283	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
	284	" %x cause=%x sel=%x sp=%x %x %x\n",
	285	__func__, rw, match, env->pc,
786c02f1 EI	286	vaddr, vpage,
786c02f1 EI	287	tlb_vpn, tlb_pfn, tlb_pid,
28de16da	288	pid,
786c02f1 EI	289	r_cause,
786c02f1 EI	290	env->sregs[SFR_RW_MM_TLB_SEL],
b41f7df0	291	env->regs[R_SP], env->pregs[PR_USP], env->ksp));
786c02f1	292
bf91ada5	293	res->phy = tlb_pfn << TARGET_PAGE_BITS;
94cff60a TS	294	return !match;
	295	}
	296
cf1d97f0	297	void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
786c02f1	298	{
cf1d97f0 EI	299	target_ulong vaddr;
	300	unsigned int idx;
	301	uint32_t lo, hi;
	302	uint32_t tlb_vpn;
80e1b265	303	int tlb_pid, tlb_g, tlb_v;
cf1d97f0 EI	304	unsigned int set;
	305	unsigned int mmu;
	306
	307	pid &= 0xff;
	308	for (mmu = 0; mmu < 2; mmu++) {
	309	for (set = 0; set < 4; set++)
	310	{
	311	for (idx = 0; idx < 16; idx++) {
	312	lo = env->tlbsets[mmu][set][idx].lo;
	313	hi = env->tlbsets[mmu][set][idx].hi;
	314
	315	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	316	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
	317	tlb_g = EXTRACT_FIELD(lo, 4, 4);
	318	tlb_v = EXTRACT_FIELD(lo, 3, 3);
cf1d97f0	319
80e1b265	320	if (tlb_v && !tlb_g && (tlb_pid == pid)) {
cf1d97f0	321	vaddr = tlb_vpn << TARGET_PAGE_BITS;
d12d51d5 AL	322	D_LOG("flush pid=%x vaddr=%x\n",
d12d51d5 AL	323	pid, vaddr);
cf1d97f0 EI	324	tlb_flush_page(env, vaddr);
	325	}
	326	}
	327	}
	328	}
786c02f1 EI	329	}
786c02f1 EI	330
2fa73ec8	331	int cris_mmu_translate(struct cris_mmu_result *res,
94cff60a	332	CPUState *env, uint32_t vaddr,
9f5a1fae	333	int rw, int mmu_idx, int debug)
94cff60a	334	{
94cff60a TS	335	int seg;
94cff60a TS	336	int miss = 0;
786c02f1	337	int is_user = mmu_idx == MMU_USER_IDX;
b41f7df0 EI	338	uint32_t old_srs;
	339
	340	old_srs= env->pregs[PR_SRS];
	341
	342	/* rw == 2 means exec, map the access to the insn mmu. */
	343	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
94cff60a TS	344
	345	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
	346	res->phy = vaddr;
b23761f9	347	res->prot = PAGE_BITS;
b41f7df0	348	goto done;
94cff60a TS	349	}
	350
	351	seg = vaddr >> 28;
218951ef	352	if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
94cff60a TS	353	{
	354	uint32_t base;
	355
	356	miss = 0;
	357	base = cris_mmu_translate_seg(env, seg);
0d84be5b	358	res->phy = base \| (0x0fffffff & vaddr);
b23761f9	359	res->prot = PAGE_BITS;
9f5a1fae EI	360	} else {
	361	miss = cris_mmu_translate_page(res, env, vaddr, rw,
	362	is_user, debug);
94cff60a	363	}
b41f7df0 EI	364	done:
b41f7df0 EI	365	env->pregs[PR_SRS] = old_srs;
94cff60a TS	366	return miss;
	367	}
	368	#endif