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105 <div class="summary">
106 <a href="#func-members">Functions</a> </div>
107 <div class="headertitle"><div class="title">hardware_riscv_platform_timer<div class="ingroups"><a class="el" href="group__hardware.html">Hardware APIs</a></div></div></div>
109 <div class="contents">
111 <p>Accessors for standard RISC-V platform timer (mtime/mtimecmp), available on Raspberry Pi microcontrollers with RISC-V processors.
112 <a href="#details">More...</a></p>
113 <table class="memberdecls">
114 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
115 Functions</h2></td></tr>
116 <tr class="memitem:ga2afc7ae3feafc019abd3883a3f2fe04f"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga2afc7ae3feafc019abd3883a3f2fe04f">riscv_timer_set_enabled</a> (bool enabled)</td></tr>
117 <tr class="memdesc:ga2afc7ae3feafc019abd3883a3f2fe04f"><td class="mdescLeft"> </td><td class="mdescRight">Enable or disable the RISC-V platform timer. <a href="group__hardware__riscv__platform__timer.html#ga2afc7ae3feafc019abd3883a3f2fe04f">More...</a><br /></td></tr>
118 <tr class="separator:ga2afc7ae3feafc019abd3883a3f2fe04f"><td class="memSeparator" colspan="2"> </td></tr>
119 <tr class="memitem:gacdd646c3b36c51473a16c07a799f9eec"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#gacdd646c3b36c51473a16c07a799f9eec">riscv_timer_set_fullspeed</a> (bool fullspeed)</td></tr>
120 <tr class="memdesc:gacdd646c3b36c51473a16c07a799f9eec"><td class="mdescLeft"> </td><td class="mdescRight">Configure the RISC-V platform timer to run at full system clock speed. <a href="group__hardware__riscv__platform__timer.html#gacdd646c3b36c51473a16c07a799f9eec">More...</a><br /></td></tr>
121 <tr class="separator:gacdd646c3b36c51473a16c07a799f9eec"><td class="memSeparator" colspan="2"> </td></tr>
122 <tr class="memitem:gab016600bb8fc7553da83a90501371693"><td class="memItemLeft" align="right" valign="top">static uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#gab016600bb8fc7553da83a90501371693">riscv_timer_get_mtime</a> (void)</td></tr>
123 <tr class="memdesc:gab016600bb8fc7553da83a90501371693"><td class="mdescLeft"> </td><td class="mdescRight">Read the RISC-V platform timer. <a href="group__hardware__riscv__platform__timer.html#gab016600bb8fc7553da83a90501371693">More...</a><br /></td></tr>
124 <tr class="separator:gab016600bb8fc7553da83a90501371693"><td class="memSeparator" colspan="2"> </td></tr>
125 <tr class="memitem:ga96285c497dceb9126e6ea3130be72bcb"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga96285c497dceb9126e6ea3130be72bcb">riscv_timer_set_mtime</a> (uint64_t mtime)</td></tr>
126 <tr class="memdesc:ga96285c497dceb9126e6ea3130be72bcb"><td class="mdescLeft"> </td><td class="mdescRight">Update the RISC-V platform timer. <a href="group__hardware__riscv__platform__timer.html#ga96285c497dceb9126e6ea3130be72bcb">More...</a><br /></td></tr>
127 <tr class="separator:ga96285c497dceb9126e6ea3130be72bcb"><td class="memSeparator" colspan="2"> </td></tr>
128 <tr class="memitem:ga148695c3ff3dce3222934040cfc77d91"><td class="memItemLeft" align="right" valign="top">static uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga148695c3ff3dce3222934040cfc77d91">riscv_timer_get_mtimecmp</a> (void)</td></tr>
129 <tr class="memdesc:ga148695c3ff3dce3222934040cfc77d91"><td class="mdescLeft"> </td><td class="mdescRight">Get the current RISC-V platform timer mtimecmp value for this core. <a href="group__hardware__riscv__platform__timer.html#ga148695c3ff3dce3222934040cfc77d91">More...</a><br /></td></tr>
130 <tr class="separator:ga148695c3ff3dce3222934040cfc77d91"><td class="memSeparator" colspan="2"> </td></tr>
131 <tr class="memitem:ga7003005e0d2142e95ce53f2ceee29fdd"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__riscv__platform__timer.html#ga7003005e0d2142e95ce53f2ceee29fdd">riscv_timer_set_mtimecmp</a> (uint64_t mtimecmp)</td></tr>
132 <tr class="memdesc:ga7003005e0d2142e95ce53f2ceee29fdd"><td class="mdescLeft"> </td><td class="mdescRight">Set a new RISC-V platform timer interrupt comparison value (mtimecmp) for this core. <a href="group__hardware__riscv__platform__timer.html#ga7003005e0d2142e95ce53f2ceee29fdd">More...</a><br /></td></tr>
133 <tr class="separator:ga7003005e0d2142e95ce53f2ceee29fdd"><td class="memSeparator" colspan="2"> </td></tr>
135 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
136 <p >Accessors for standard RISC-V platform timer (mtime/mtimecmp), available on Raspberry Pi microcontrollers with RISC-V processors. </p>
137 <p >Note this header can be used by Arm as well as RISC-V processors, as the timer is a memory-mapped peripheral external to the processors. The name refers to this timer being a standard RISC-V peripheral. </p>
138 <h2 class="groupheader">Function Documentation</h2>
139 <a id="gab016600bb8fc7553da83a90501371693" name="gab016600bb8fc7553da83a90501371693"></a>
140 <h2 class="memtitle"><span class="permalink"><a href="#gab016600bb8fc7553da83a90501371693">◆ </a></span>riscv_timer_get_mtime()</h2>
142 <div class="memitem">
143 <div class="memproto">
144 <table class="mlabels">
146 <td class="mlabels-left">
147 <table class="memname">
149 <td class="memname">static uint64_t riscv_timer_get_mtime </td>
151 <td class="paramtype">void </td>
152 <td class="paramname"></td><td>)</td>
157 <td class="mlabels-right">
158 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
161 </div><div class="memdoc">
163 <p>Read the RISC-V platform timer. </p>
164 <dl class="section return"><dt>Returns</dt><dd>Current 64-bit mtime value </dd></dl>
168 <a id="ga148695c3ff3dce3222934040cfc77d91" name="ga148695c3ff3dce3222934040cfc77d91"></a>
169 <h2 class="memtitle"><span class="permalink"><a href="#ga148695c3ff3dce3222934040cfc77d91">◆ </a></span>riscv_timer_get_mtimecmp()</h2>
171 <div class="memitem">
172 <div class="memproto">
173 <table class="mlabels">
175 <td class="mlabels-left">
176 <table class="memname">
178 <td class="memname">static uint64_t riscv_timer_get_mtimecmp </td>
180 <td class="paramtype">void </td>
181 <td class="paramname"></td><td>)</td>
186 <td class="mlabels-right">
187 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
190 </div><div class="memdoc">
192 <p>Get the current RISC-V platform timer mtimecmp value for this core. </p>
193 <p >Get the current mtimecmp value for the calling core. This function is interrupt-safe as long as timer interrupts only increase the value of mtimecmp. Otherwise, it must be called with timer interrupts disabled.</p>
194 <dl class="section return"><dt>Returns</dt><dd>Current value of mtimecmp </dd></dl>
198 <a id="ga2afc7ae3feafc019abd3883a3f2fe04f" name="ga2afc7ae3feafc019abd3883a3f2fe04f"></a>
199 <h2 class="memtitle"><span class="permalink"><a href="#ga2afc7ae3feafc019abd3883a3f2fe04f">◆ </a></span>riscv_timer_set_enabled()</h2>
201 <div class="memitem">
202 <div class="memproto">
203 <table class="mlabels">
205 <td class="mlabels-left">
206 <table class="memname">
208 <td class="memname">static void riscv_timer_set_enabled </td>
210 <td class="paramtype">bool </td>
211 <td class="paramname"><em>enabled</em></td><td>)</td>
216 <td class="mlabels-right">
217 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
220 </div><div class="memdoc">
222 <p>Enable or disable the RISC-V platform timer. </p>
223 <p >This enables and disables the counting of the RISC-V platform timer. It does not enable or disable the interrupts, which are asserted unconditionally when a given core's mtimecmp/mtimecmph registers are greater than the current 64-bit value of the mtime/mtimeh registers.</p>
224 <dl class="params"><dt>Parameters</dt><dd>
225 <table class="params">
226 <tr><td class="paramname">enabled</td><td>Pass true to enable, false to disable </td></tr>
233 <a id="gacdd646c3b36c51473a16c07a799f9eec" name="gacdd646c3b36c51473a16c07a799f9eec"></a>
234 <h2 class="memtitle"><span class="permalink"><a href="#gacdd646c3b36c51473a16c07a799f9eec">◆ </a></span>riscv_timer_set_fullspeed()</h2>
236 <div class="memitem">
237 <div class="memproto">
238 <table class="mlabels">
240 <td class="mlabels-left">
241 <table class="memname">
243 <td class="memname">static void riscv_timer_set_fullspeed </td>
245 <td class="paramtype">bool </td>
246 <td class="paramname"><em>fullspeed</em></td><td>)</td>
251 <td class="mlabels-right">
252 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
255 </div><div class="memdoc">
257 <p>Configure the RISC-V platform timer to run at full system clock speed. </p>
258 <dl class="params"><dt>Parameters</dt><dd>
259 <table class="params">
260 <tr><td class="paramname">fullspeed</td><td>Pass true to increment at system clock speed, false to increment at the frequency defined by the system tick generator (the <code>ticks</code> block) </td></tr>
267 <a id="ga96285c497dceb9126e6ea3130be72bcb" name="ga96285c497dceb9126e6ea3130be72bcb"></a>
268 <h2 class="memtitle"><span class="permalink"><a href="#ga96285c497dceb9126e6ea3130be72bcb">◆ </a></span>riscv_timer_set_mtime()</h2>
270 <div class="memitem">
271 <div class="memproto">
272 <table class="mlabels">
274 <td class="mlabels-left">
275 <table class="memname">
277 <td class="memname">static void riscv_timer_set_mtime </td>
279 <td class="paramtype">uint64_t </td>
280 <td class="paramname"><em>mtime</em></td><td>)</td>
285 <td class="mlabels-right">
286 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
289 </div><div class="memdoc">
291 <p>Update the RISC-V platform timer. </p>
292 <p >This function should only be called when the timer is disabled via <a class="el" href="group__hardware__riscv__platform__timer.html#ga2afc7ae3feafc019abd3883a3f2fe04f" title="Enable or disable the RISC-V platform timer.">riscv_timer_set_enabled()</a>. Note also that unlike the mtimecmp comparison values, mtime is <em>not</em> core-local, so updates on one core will be visible to the other core.</p>
293 <dl class="params"><dt>Parameters</dt><dd>
294 <table class="params">
295 <tr><td class="paramname">mtime</td><td>New value to set the RISC-V platform timer to </td></tr>
302 <a id="ga7003005e0d2142e95ce53f2ceee29fdd" name="ga7003005e0d2142e95ce53f2ceee29fdd"></a>
303 <h2 class="memtitle"><span class="permalink"><a href="#ga7003005e0d2142e95ce53f2ceee29fdd">◆ </a></span>riscv_timer_set_mtimecmp()</h2>
305 <div class="memitem">
306 <div class="memproto">
307 <table class="mlabels">
309 <td class="mlabels-left">
310 <table class="memname">
312 <td class="memname">static void riscv_timer_set_mtimecmp </td>
314 <td class="paramtype">uint64_t </td>
315 <td class="paramname"><em>mtimecmp</em></td><td>)</td>
320 <td class="mlabels-right">
321 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
324 </div><div class="memdoc">
326 <p>Set a new RISC-V platform timer interrupt comparison value (mtimecmp) for this core. </p>
327 <p >This function updates the mtimecmp value for the current core. The calling core's RISC-V platform timer interrupt is asserted whenever the 64-bit mtime value (stored in 32-bit mtime/mtimeh registers) is greater than or equal to this core's current mtime/mtimecmph value.</p>
328 <dl class="params"><dt>Parameters</dt><dd>
329 <table class="params">
330 <tr><td class="paramname">mtime</td><td>New value to set the RISC-V platform timer to </td></tr>
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