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 104 <div class="header">
 105   <div class="headertitle"><div class="title">uart.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_UART_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_UART_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/uart.h&quot;</span></div>
 115 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
 116 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart</span></div>
 117 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
 118 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 119 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.</span></div>
 120 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
 121 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 122 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 123 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
 124 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structuart__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 125 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    _REG_(UART_UARTDR_OFFSET) <span class="comment">// UART_UARTDR</span></div>
 126 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    <span class="comment">// Data Register, UARTDR</span></div>
 127 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// 0x00000800 [11]    OE           (-) Overrun error</span></div>
 128 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0x00000400 [10]    BE           (-) Break error</span></div>
 129 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// 0x00000200 [9]     PE           (-) Parity error</span></div>
 130 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    <span class="comment">// 0x00000100 [8]     FE           (-) Framing error</span></div>
 131 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    <span class="comment">// 0x000000ff [7:0]   DATA         (-) Receive (read) data character</span></div>
 132 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    io_rw_32 dr;</div>
 133 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span> </div>
 134 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    _REG_(UART_UARTRSR_OFFSET) <span class="comment">// UART_UARTRSR</span></div>
 135 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    <span class="comment">// Receive Status Register/Error Clear Register, UARTRSR/UARTECR</span></div>
 136 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    <span class="comment">// 0x00000008 [3]     OE           (0) Overrun error</span></div>
 137 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// 0x00000004 [2]     BE           (0) Break error</span></div>
 138 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// 0x00000002 [1]     PE           (0) Parity error</span></div>
 139 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// 0x00000001 [0]     FE           (0) Framing error</span></div>
 140 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    io_rw_32 rsr;</div>
 141 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span> </div>
 142 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    uint32_t _pad0[4];</div>
 143 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span> </div>
 144 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    _REG_(UART_UARTFR_OFFSET) <span class="comment">// UART_UARTFR</span></div>
 145 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// Flag Register, UARTFR</span></div>
 146 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0x00000100 [8]     RI           (-) Ring indicator</span></div>
 147 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    <span class="comment">// 0x00000080 [7]     TXFE         (1) Transmit FIFO empty</span></div>
 148 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>    <span class="comment">// 0x00000040 [6]     RXFF         (0) Receive FIFO full</span></div>
 149 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// 0x00000020 [5]     TXFF         (0) Transmit FIFO full</span></div>
 150 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    <span class="comment">// 0x00000010 [4]     RXFE         (1) Receive FIFO empty</span></div>
 151 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// 0x00000008 [3]     BUSY         (0) UART busy</span></div>
 152 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0x00000004 [2]     DCD          (-) Data carrier detect</span></div>
 153 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x00000002 [1]     DSR          (-) Data set ready</span></div>
 154 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0x00000001 [0]     CTS          (-) Clear to send</span></div>
 155 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    io_ro_32 fr;</div>
 156 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span> </div>
 157 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    uint32_t _pad1;</div>
 158 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span> </div>
 159 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    _REG_(UART_UARTILPR_OFFSET) <span class="comment">// UART_UARTILPR</span></div>
 160 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    <span class="comment">// IrDA Low-Power Counter Register, UARTILPR</span></div>
 161 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    <span class="comment">// 0x000000ff [7:0]   ILPDVSR      (0x00) 8-bit low-power divisor value</span></div>
 162 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    io_rw_32 ilpr;</div>
 163 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span> </div>
 164 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    _REG_(UART_UARTIBRD_OFFSET) <span class="comment">// UART_UARTIBRD</span></div>
 165 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    <span class="comment">// Integer Baud Rate Register, UARTIBRD</span></div>
 166 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    <span class="comment">// 0x0000ffff [15:0]  BAUD_DIVINT  (0x0000) The integer baud rate divisor</span></div>
 167 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    io_rw_32 ibrd;</div>
 168 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span> </div>
 169 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    _REG_(UART_UARTFBRD_OFFSET) <span class="comment">// UART_UARTFBRD</span></div>
 170 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// Fractional Baud Rate Register, UARTFBRD</span></div>
 171 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    <span class="comment">// 0x0000003f [5:0]   BAUD_DIVFRAC (0x00) The fractional baud rate divisor</span></div>
 172 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    io_rw_32 fbrd;</div>
 173 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span> </div>
 174 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    _REG_(UART_UARTLCR_H_OFFSET) <span class="comment">// UART_UARTLCR_H</span></div>
 175 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    <span class="comment">// Line Control Register, UARTLCR_H</span></div>
 176 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// 0x00000080 [7]     SPS          (0) Stick parity select</span></div>
 177 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// 0x00000060 [6:5]   WLEN         (0x0) Word length</span></div>
 178 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    <span class="comment">// 0x00000010 [4]     FEN          (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)...</span></div>
 179 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    <span class="comment">// 0x00000008 [3]     STP2         (0) Two stop bits select</span></div>
 180 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    <span class="comment">// 0x00000004 [2]     EPS          (0) Even parity select</span></div>
 181 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    <span class="comment">// 0x00000002 [1]     PEN          (0) Parity enable: 0 = parity is disabled and no parity bit...</span></div>
 182 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    <span class="comment">// 0x00000001 [0]     BRK          (0) Send break</span></div>
 183 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    io_rw_32 lcr_h;</div>
 184 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span> </div>
 185 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    _REG_(UART_UARTCR_OFFSET) <span class="comment">// UART_UARTCR</span></div>
 186 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    <span class="comment">// Control Register, UARTCR</span></div>
 187 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// 0x00008000 [15]    CTSEN        (0) CTS hardware flow control enable</span></div>
 188 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    <span class="comment">// 0x00004000 [14]    RTSEN        (0) RTS hardware flow control enable</span></div>
 189 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>    <span class="comment">// 0x00002000 [13]    OUT2         (0) This bit is the complement of the UART Out2 (nUARTOut2)...</span></div>
 190 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    <span class="comment">// 0x00001000 [12]    OUT1         (0) This bit is the complement of the UART Out1 (nUARTOut1)...</span></div>
 191 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    <span class="comment">// 0x00000800 [11]    RTS          (0) Request to send</span></div>
 192 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// 0x00000400 [10]    DTR          (0) Data transmit ready</span></div>
 193 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    <span class="comment">// 0x00000200 [9]     RXE          (1) Receive enable</span></div>
 194 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    <span class="comment">// 0x00000100 [8]     TXE          (1) Transmit enable</span></div>
 195 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    <span class="comment">// 0x00000080 [7]     LBE          (0) Loopback enable</span></div>
 196 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    <span class="comment">// 0x00000004 [2]     SIRLP        (0) SIR low-power IrDA mode</span></div>
 197 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    <span class="comment">// 0x00000002 [1]     SIREN        (0) SIR enable: 0 = IrDA SIR ENDEC is disabled</span></div>
 198 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    <span class="comment">// 0x00000001 [0]     UARTEN       (0) UART enable: 0 = UART is disabled</span></div>
 199 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    io_rw_32 cr;</div>
 200 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span> </div>
 201 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    _REG_(UART_UARTIFLS_OFFSET) <span class="comment">// UART_UARTIFLS</span></div>
 202 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    <span class="comment">// Interrupt FIFO Level Select Register, UARTIFLS</span></div>
 203 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>    <span class="comment">// 0x00000038 [5:3]   RXIFLSEL     (0x2) Receive interrupt FIFO level select</span></div>
 204 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    <span class="comment">// 0x00000007 [2:0]   TXIFLSEL     (0x2) Transmit interrupt FIFO level select</span></div>
 205 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    io_rw_32 ifls;</div>
 206 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span> </div>
 207 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    _REG_(UART_UARTIMSC_OFFSET) <span class="comment">// UART_UARTIMSC</span></div>
 208 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    <span class="comment">// Interrupt Mask Set/Clear Register, UARTIMSC</span></div>
 209 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    <span class="comment">// 0x00000400 [10]    OEIM         (0) Overrun error interrupt mask</span></div>
 210 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    <span class="comment">// 0x00000200 [9]     BEIM         (0) Break error interrupt mask</span></div>
 211 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    <span class="comment">// 0x00000100 [8]     PEIM         (0) Parity error interrupt mask</span></div>
 212 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    <span class="comment">// 0x00000080 [7]     FEIM         (0) Framing error interrupt mask</span></div>
 213 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    <span class="comment">// 0x00000040 [6]     RTIM         (0) Receive timeout interrupt mask</span></div>
 214 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    <span class="comment">// 0x00000020 [5]     TXIM         (0) Transmit interrupt mask</span></div>
 215 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// 0x00000010 [4]     RXIM         (0) Receive interrupt mask</span></div>
 216 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    <span class="comment">// 0x00000008 [3]     DSRMIM       (0) nUARTDSR modem interrupt mask</span></div>
 217 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    <span class="comment">// 0x00000004 [2]     DCDMIM       (0) nUARTDCD modem interrupt mask</span></div>
 218 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    <span class="comment">// 0x00000002 [1]     CTSMIM       (0) nUARTCTS modem interrupt mask</span></div>
 219 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span>    <span class="comment">// 0x00000001 [0]     RIMIM        (0) nUARTRI modem interrupt mask</span></div>
 220 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    io_rw_32 imsc;</div>
 221 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span> </div>
 222 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span>    _REG_(UART_UARTRIS_OFFSET) <span class="comment">// UART_UARTRIS</span></div>
 223 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    <span class="comment">// Raw Interrupt Status Register, UARTRIS</span></div>
 224 <div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    <span class="comment">// 0x00000400 [10]    OERIS        (0) Overrun error interrupt status</span></div>
 225 <div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    <span class="comment">// 0x00000200 [9]     BERIS        (0) Break error interrupt status</span></div>
 226 <div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    <span class="comment">// 0x00000100 [8]     PERIS        (0) Parity error interrupt status</span></div>
 227 <div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span>    <span class="comment">// 0x00000080 [7]     FERIS        (0) Framing error interrupt status</span></div>
 228 <div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    <span class="comment">// 0x00000040 [6]     RTRIS        (0) Receive timeout interrupt status</span></div>
 229 <div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    <span class="comment">// 0x00000020 [5]     TXRIS        (0) Transmit interrupt status</span></div>
 230 <div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span>    <span class="comment">// 0x00000010 [4]     RXRIS        (0) Receive interrupt status</span></div>
 231 <div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    <span class="comment">// 0x00000008 [3]     DSRRMIS      (-) nUARTDSR modem interrupt status</span></div>
 232 <div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span>    <span class="comment">// 0x00000004 [2]     DCDRMIS      (-) nUARTDCD modem interrupt status</span></div>
 233 <div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    <span class="comment">// 0x00000002 [1]     CTSRMIS      (-) nUARTCTS modem interrupt status</span></div>
 234 <div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span>    <span class="comment">// 0x00000001 [0]     RIRMIS       (-) nUARTRI modem interrupt status</span></div>
 235 <div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    io_ro_32 ris;</div>
 236 <div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span> </div>
 237 <div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    _REG_(UART_UARTMIS_OFFSET) <span class="comment">// UART_UARTMIS</span></div>
 238 <div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span>    <span class="comment">// Masked Interrupt Status Register, UARTMIS</span></div>
 239 <div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    <span class="comment">// 0x00000400 [10]    OEMIS        (0) Overrun error masked interrupt status</span></div>
 240 <div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    <span class="comment">// 0x00000200 [9]     BEMIS        (0) Break error masked interrupt status</span></div>
 241 <div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    <span class="comment">// 0x00000100 [8]     PEMIS        (0) Parity error masked interrupt status</span></div>
 242 <div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span>    <span class="comment">// 0x00000080 [7]     FEMIS        (0) Framing error masked interrupt status</span></div>
 243 <div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>    <span class="comment">// 0x00000040 [6]     RTMIS        (0) Receive timeout masked interrupt status</span></div>
 244 <div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span>    <span class="comment">// 0x00000020 [5]     TXMIS        (0) Transmit masked interrupt status</span></div>
 245 <div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>    <span class="comment">// 0x00000010 [4]     RXMIS        (0) Receive masked interrupt status</span></div>
 246 <div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span>    <span class="comment">// 0x00000008 [3]     DSRMMIS      (-) nUARTDSR modem masked interrupt status</span></div>
 247 <div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    <span class="comment">// 0x00000004 [2]     DCDMMIS      (-) nUARTDCD modem masked interrupt status</span></div>
 248 <div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span>    <span class="comment">// 0x00000002 [1]     CTSMMIS      (-) nUARTCTS modem masked interrupt status</span></div>
 249 <div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    <span class="comment">// 0x00000001 [0]     RIMMIS       (-) nUARTRI modem masked interrupt status</span></div>
 250 <div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>    io_ro_32 mis;</div>
 251 <div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span> </div>
 252 <div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    _REG_(UART_UARTICR_OFFSET) <span class="comment">// UART_UARTICR</span></div>
 253 <div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>    <span class="comment">// Interrupt Clear Register, UARTICR</span></div>
 254 <div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span>    <span class="comment">// 0x00000400 [10]    OEIC         (-) Overrun error interrupt clear</span></div>
 255 <div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span>    <span class="comment">// 0x00000200 [9]     BEIC         (-) Break error interrupt clear</span></div>
 256 <div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    <span class="comment">// 0x00000100 [8]     PEIC         (-) Parity error interrupt clear</span></div>
 257 <div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span>    <span class="comment">// 0x00000080 [7]     FEIC         (-) Framing error interrupt clear</span></div>
 258 <div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span>    <span class="comment">// 0x00000040 [6]     RTIC         (-) Receive timeout interrupt clear</span></div>
 259 <div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    <span class="comment">// 0x00000020 [5]     TXIC         (-) Transmit interrupt clear</span></div>
 260 <div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// 0x00000010 [4]     RXIC         (-) Receive interrupt clear</span></div>
 261 <div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    <span class="comment">// 0x00000008 [3]     DSRMIC       (-) nUARTDSR modem interrupt clear</span></div>
 262 <div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>    <span class="comment">// 0x00000004 [2]     DCDMIC       (-) nUARTDCD modem interrupt clear</span></div>
 263 <div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    <span class="comment">// 0x00000002 [1]     CTSMIC       (-) nUARTCTS modem interrupt clear</span></div>
 264 <div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>    <span class="comment">// 0x00000001 [0]     RIMIC        (-) nUARTRI modem interrupt clear</span></div>
 265 <div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span>    io_rw_32 icr;</div>
 266 <div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span> </div>
 267 <div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    _REG_(UART_UARTDMACR_OFFSET) <span class="comment">// UART_UARTDMACR</span></div>
 268 <div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    <span class="comment">// DMA Control Register, UARTDMACR</span></div>
 269 <div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>    <span class="comment">// 0x00000004 [2]     DMAONERR     (0) DMA on error</span></div>
 270 <div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>    <span class="comment">// 0x00000002 [1]     TXDMAE       (0) Transmit DMA enable</span></div>
 271 <div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>    <span class="comment">// 0x00000001 [0]     RXDMAE       (0) Receive DMA enable</span></div>
 272 <div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span>    io_rw_32 dmacr;</div>
 273 <div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span>} <a class="code hl_struct" href="structuart__hw__t.html">uart_hw_t</a>;</div>
 274 <div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span> </div>
 275 <div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span><span class="preprocessor">#define uart0_hw ((uart_hw_t *)UART0_BASE)</span></div>
 276 <div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span><span class="preprocessor">#define uart1_hw ((uart_hw_t *)UART1_BASE)</span></div>
 277 <div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structuart__hw__t.html">uart_hw_t</a>) == 0x004c, <span class="stringliteral">&quot;&quot;</span>);</div>
 278 <div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span> </div>
 279 <div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_UART_H</span></div>
 280 <div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span> </div>
 281 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 282 <div class="ttc" id="astructuart__hw__t_html"><div class="ttname"><a href="structuart__hw__t.html">uart_hw_t</a></div><div class="ttdef"><b>Definition:</b> uart.h:26</div></div>
 283 </div><!-- fragment --></div><!-- contents -->
 284 </div><!-- doc-content -->
 285
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