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 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">interp.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_INTERP_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_INTERP_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/sio.h&quot;</span></div>
 115 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
 116 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio</span></div>
 117 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
 118 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 119 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.</span></div>
 120 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
 121 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 122 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 123 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
 124 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structinterp__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 125 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    <span class="comment">// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)</span></div>
 126 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    _REG_(SIO_INTERP0_ACCUM0_OFFSET) <span class="comment">// SIO_INTERP0_ACCUM0</span></div>
 127 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// Read/write access to accumulator 0</span></div>
 128 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0xffffffff [31:0]  INTERP0_ACCUM0 (0x00000000) </span></div>
 129 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    io_rw_32 accum[2];</div>
 130 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span> </div>
 131 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    <span class="comment">// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)</span></div>
 132 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    _REG_(SIO_INTERP0_BASE0_OFFSET) <span class="comment">// SIO_INTERP0_BASE0</span></div>
 133 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    <span class="comment">// Read/write access to BASE0 register</span></div>
 134 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    <span class="comment">// 0xffffffff [31:0]  INTERP0_BASE0 (0x00000000) </span></div>
 135 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    io_rw_32 base[3];</div>
 136 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span> </div>
 137 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)</span></div>
 138 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    _REG_(SIO_INTERP0_POP_LANE0_OFFSET) <span class="comment">// SIO_INTERP0_POP_LANE0</span></div>
 139 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)</span></div>
 140 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// 0xffffffff [31:0]  INTERP0_POP_LANE0 (0x00000000) </span></div>
 141 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    io_ro_32 pop[3];</div>
 142 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span> </div>
 143 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)</span></div>
 144 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) <span class="comment">// SIO_INTERP0_PEEK_LANE0</span></div>
 145 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// Read LANE0 result, without altering any internal state (PEEK)</span></div>
 146 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0xffffffff [31:0]  INTERP0_PEEK_LANE0 (0x00000000) </span></div>
 147 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    io_ro_32 peek[3];</div>
 148 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span> </div>
 149 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)</span></div>
 150 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) <span class="comment">// SIO_INTERP0_CTRL_LANE0</span></div>
 151 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// Control register for lane 0</span></div>
 152 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0x02000000 [25]    OVERF        (0) Set if either OVERF0 or OVERF1 is set</span></div>
 153 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x01000000 [24]    OVERF1       (0) Indicates if any masked-off MSBs in ACCUM1 are set</span></div>
 154 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0x00800000 [23]    OVERF0       (0) Indicates if any masked-off MSBs in ACCUM0 are set</span></div>
 155 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// 0x00200000 [21]    BLEND        (0) Only present on INTERP0 on each core</span></div>
 156 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x00180000 [20:19] FORCE_MSB    (0x0) ORed into bits 29:28 of the lane result presented to the...</span></div>
 157 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x00040000 [18]    ADD_RAW      (0) If 1, mask + shift is bypassed for LANE0 result</span></div>
 158 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    <span class="comment">// 0x00020000 [17]    CROSS_RESULT (0) If 1, feed the opposite lane&#39;s result into this lane&#39;s...</span></div>
 159 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    <span class="comment">// 0x00010000 [16]    CROSS_INPUT  (0) If 1, feed the opposite lane&#39;s accumulator into this...</span></div>
 160 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    <span class="comment">// 0x00008000 [15]    SIGNED       (0) If SIGNED is set, the shifted and masked accumulator...</span></div>
 161 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    <span class="comment">// 0x00007c00 [14:10] MASK_MSB     (0x00) The most-significant bit allowed to pass by the mask...</span></div>
 162 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// 0x000003e0 [9:5]   MASK_LSB     (0x00) The least-significant bit allowed to pass by the mask (inclusive)</span></div>
 163 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    <span class="comment">// 0x0000001f [4:0]   SHIFT        (0x00) Logical right-shift applied to accumulator before masking</span></div>
 164 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    io_rw_32 ctrl[2];</div>
 165 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span> </div>
 166 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    <span class="comment">// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)</span></div>
 167 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) <span class="comment">// SIO_INTERP0_ACCUM0_ADD</span></div>
 168 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    <span class="comment">// Values written here are atomically added to ACCUM0</span></div>
 169 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    <span class="comment">// 0x00ffffff [23:0]  INTERP0_ACCUM0_ADD (0x000000) </span></div>
 170 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    io_rw_32 add_raw[2];</div>
 171 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span> </div>
 172 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) <span class="comment">// SIO_INTERP0_BASE_1AND0</span></div>
 173 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    <span class="comment">// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.</span></div>
 174 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    <span class="comment">// 0xffffffff [31:0]  INTERP0_BASE_1AND0 (0x00000000) </span></div>
 175 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    io_wo_32 base01;</div>
 176 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>} <a class="code hl_struct" href="structinterp__hw__t.html">interp_hw_t</a>;</div>
 177 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span> </div>
 178 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span><span class="preprocessor">#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))</span></div>
 179 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structinterp__hw__t.html">interp_hw_t</a>) == 0x0040, <span class="stringliteral">&quot;&quot;</span>);</div>
 180 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span><span class="preprocessor">#define interp0_hw (&amp;interp_hw_array[0])</span></div>
 181 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span><span class="preprocessor">#define interp1_hw (&amp;interp_hw_array[1])</span></div>
 182 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span> </div>
 183 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_INTERP_H</span></div>
 184 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span> </div>
 185 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 186 <div class="ttc" id="astructinterp__hw__t_html"><div class="ttname"><a href="structinterp__hw__t.html">interp_hw_t</a></div><div class="ttdef"><b>Definition:</b> interp.h:26</div></div>
 187 </div><!-- fragment --></div><!-- contents -->
 188 </div><!-- doc-content -->
 189
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