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 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">dma.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_DMA_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_DMA_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/dma.h&quot;</span></div>
 115 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span><span class="preprocessor">#include &quot;hardware/structs/dma_debug.h&quot;</span></div>
 116 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span> </div>
 117 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma</span></div>
 118 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">//</span></div>
 119 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 120 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.</span></div>
 121 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">//</span></div>
 122 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 123 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 124 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno">   26</span> </div>
 125 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno"><a class="line" href="structdma__channel__hw__t.html">   27</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 126 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    _REG_(DMA_CH0_READ_ADDR_OFFSET) <span class="comment">// DMA_CH0_READ_ADDR</span></div>
 127 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// DMA Channel 0 Read Address pointer</span></div>
 128 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0xffffffff [31:0]  CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes</span></div>
 129 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    io_rw_32 read_addr;</div>
 130 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span> </div>
 131 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    _REG_(DMA_CH0_WRITE_ADDR_OFFSET) <span class="comment">// DMA_CH0_WRITE_ADDR</span></div>
 132 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    <span class="comment">// DMA Channel 0 Write Address pointer</span></div>
 133 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    <span class="comment">// 0xffffffff [31:0]  CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes</span></div>
 134 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    io_rw_32 write_addr;</div>
 135 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span> </div>
 136 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    _REG_(DMA_CH0_TRANS_COUNT_OFFSET) <span class="comment">// DMA_CH0_TRANS_COUNT</span></div>
 137 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// DMA Channel 0 Transfer Count</span></div>
 138 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// 0xffffffff [31:0]  CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will...</span></div>
 139 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    io_rw_32 transfer_count;</div>
 140 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span> </div>
 141 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    _REG_(DMA_CH0_CTRL_TRIG_OFFSET) <span class="comment">// DMA_CH0_CTRL_TRIG</span></div>
 142 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    <span class="comment">// DMA Channel 0 Control and Status</span></div>
 143 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// 0x80000000 [31]    AHB_ERROR    (0) Logical OR of the READ_ERROR and WRITE_ERROR flags</span></div>
 144 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    <span class="comment">// 0x40000000 [30]    READ_ERROR   (0) If 1, the channel received a read bus error</span></div>
 145 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// 0x20000000 [29]    WRITE_ERROR  (0) If 1, the channel received a write bus error</span></div>
 146 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0x01000000 [24]    BUSY         (0) This flag goes high when the channel starts a new...</span></div>
 147 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    <span class="comment">// 0x00800000 [23]    SNIFF_EN     (0) If 1, this channel&#39;s data transfers are visible to the...</span></div>
 148 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>    <span class="comment">// 0x00400000 [22]    BSWAP        (0) Apply byte-swap transformation to DMA data</span></div>
 149 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// 0x00200000 [21]    IRQ_QUIET    (0) In QUIET mode, the channel does not generate IRQs at the...</span></div>
 150 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    <span class="comment">// 0x001f8000 [20:15] TREQ_SEL     (0x00) Select a Transfer Request signal</span></div>
 151 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// 0x00007800 [14:11] CHAIN_TO     (0x0) When this channel completes, it will trigger the channel...</span></div>
 152 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0x00000400 [10]    RING_SEL     (0) Select whether RING_SIZE applies to read or write addresses</span></div>
 153 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x000003c0 [9:6]   RING_SIZE    (0x0) Size of address wrap region</span></div>
 154 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0x00000020 [5]     INCR_WRITE   (0) If 1, the write address increments with each transfer</span></div>
 155 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// 0x00000010 [4]     INCR_READ    (0) If 1, the read address increments with each transfer</span></div>
 156 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x0000000c [3:2]   DATA_SIZE    (0x0) Set the size of each bus transfer (byte/halfword/word)</span></div>
 157 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x00000002 [1]     HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in...</span></div>
 158 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    <span class="comment">// 0x00000001 [0]     EN           (0) DMA Channel Enable</span></div>
 159 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    io_rw_32 ctrl_trig;</div>
 160 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span> </div>
 161 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    _REG_(DMA_CH0_AL1_CTRL_OFFSET) <span class="comment">// DMA_CH0_AL1_CTRL</span></div>
 162 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// Alias for channel 0 CTRL register</span></div>
 163 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL1_CTRL (-) </span></div>
 164 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    io_rw_32 al1_ctrl;</div>
 165 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span> </div>
 166 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) <span class="comment">// DMA_CH0_AL1_READ_ADDR</span></div>
 167 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    <span class="comment">// Alias for channel 0 READ_ADDR register</span></div>
 168 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL1_READ_ADDR (-) </span></div>
 169 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    io_rw_32 al1_read_addr;</div>
 170 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span> </div>
 171 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) <span class="comment">// DMA_CH0_AL1_WRITE_ADDR</span></div>
 172 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    <span class="comment">// Alias for channel 0 WRITE_ADDR register</span></div>
 173 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL1_WRITE_ADDR (-) </span></div>
 174 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    io_rw_32 al1_write_addr;</div>
 175 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span> </div>
 176 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) <span class="comment">// DMA_CH0_AL1_TRANS_COUNT_TRIG</span></div>
 177 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// Alias for channel 0 TRANS_COUNT register +</span></div>
 178 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL1_TRANS_COUNT_TRIG (-) </span></div>
 179 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    io_rw_32 al1_transfer_count_trig;</div>
 180 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span> </div>
 181 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    _REG_(DMA_CH0_AL2_CTRL_OFFSET) <span class="comment">// DMA_CH0_AL2_CTRL</span></div>
 182 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    <span class="comment">// Alias for channel 0 CTRL register</span></div>
 183 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL2_CTRL (-) </span></div>
 184 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    io_rw_32 al2_ctrl;</div>
 185 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span> </div>
 186 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) <span class="comment">// DMA_CH0_AL2_TRANS_COUNT</span></div>
 187 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// Alias for channel 0 TRANS_COUNT register</span></div>
 188 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL2_TRANS_COUNT (-) </span></div>
 189 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>    io_rw_32 al2_transfer_count;</div>
 190 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span> </div>
 191 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) <span class="comment">// DMA_CH0_AL2_READ_ADDR</span></div>
 192 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// Alias for channel 0 READ_ADDR register</span></div>
 193 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL2_READ_ADDR (-) </span></div>
 194 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    io_rw_32 al2_read_addr;</div>
 195 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span> </div>
 196 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) <span class="comment">// DMA_CH0_AL2_WRITE_ADDR_TRIG</span></div>
 197 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    <span class="comment">// Alias for channel 0 WRITE_ADDR register +</span></div>
 198 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL2_WRITE_ADDR_TRIG (-) </span></div>
 199 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    io_rw_32 al2_write_addr_trig;</div>
 200 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span> </div>
 201 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    _REG_(DMA_CH0_AL3_CTRL_OFFSET) <span class="comment">// DMA_CH0_AL3_CTRL</span></div>
 202 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    <span class="comment">// Alias for channel 0 CTRL register</span></div>
 203 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL3_CTRL (-) </span></div>
 204 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    io_rw_32 al3_ctrl;</div>
 205 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span> </div>
 206 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) <span class="comment">// DMA_CH0_AL3_WRITE_ADDR</span></div>
 207 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    <span class="comment">// Alias for channel 0 WRITE_ADDR register</span></div>
 208 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL3_WRITE_ADDR (-) </span></div>
 209 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    io_rw_32 al3_write_addr;</div>
 210 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span> </div>
 211 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) <span class="comment">// DMA_CH0_AL3_TRANS_COUNT</span></div>
 212 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    <span class="comment">// Alias for channel 0 TRANS_COUNT register</span></div>
 213 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL3_TRANS_COUNT (-) </span></div>
 214 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    io_rw_32 al3_transfer_count;</div>
 215 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span> </div>
 216 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) <span class="comment">// DMA_CH0_AL3_READ_ADDR_TRIG</span></div>
 217 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    <span class="comment">// Alias for channel 0 READ_ADDR register +</span></div>
 218 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    <span class="comment">// 0xffffffff [31:0]  CH0_AL3_READ_ADDR_TRIG (-) </span></div>
 219 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span>    io_rw_32 al3_read_addr_trig;</div>
 220 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>} <a class="code hl_struct" href="structdma__channel__hw__t.html">dma_channel_hw_t</a>;</div>
 221 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span> </div>
 222 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno"><a class="line" href="structdma__irq__ctrl__hw__t.html">  124</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 223 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    _REG_(DMA_INTR_OFFSET) <span class="comment">// DMA_INTR</span></div>
 224 <div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    <span class="comment">// Interrupt Status (raw)</span></div>
 225 <div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    <span class="comment">// 0x0000ffff [15:0]  INTR         (0x0000) Raw interrupt status for DMA Channels 0</span></div>
 226 <div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    io_rw_32 intr;</div>
 227 <div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span> </div>
 228 <div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    _REG_(DMA_INTE0_OFFSET) <span class="comment">// DMA_INTE0</span></div>
 229 <div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    <span class="comment">// Interrupt Enables for IRQ 0</span></div>
 230 <div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span>    <span class="comment">// 0x0000ffff [15:0]  INTE0        (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0</span></div>
 231 <div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    io_rw_32 inte;</div>
 232 <div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span> </div>
 233 <div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    _REG_(DMA_INTF0_OFFSET) <span class="comment">// DMA_INTF0</span></div>
 234 <div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span>    <span class="comment">// Force Interrupts</span></div>
 235 <div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    <span class="comment">// 0x0000ffff [15:0]  INTF0        (0x0000) Write 1s to force the corresponding bits in INTE0</span></div>
 236 <div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span>    io_rw_32 intf;</div>
 237 <div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span> </div>
 238 <div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span>    _REG_(DMA_INTS0_OFFSET) <span class="comment">// DMA_INTS0</span></div>
 239 <div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    <span class="comment">// Interrupt Status for IRQ 0</span></div>
 240 <div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    <span class="comment">// 0x0000ffff [15:0]  INTS0        (0x0000) Indicates active channel interrupt requests which are...</span></div>
 241 <div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    io_rw_32 ints;</div>
 242 <div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span>} <a class="code hl_struct" href="structdma__irq__ctrl__hw__t.html">dma_irq_ctrl_hw_t</a>;</div>
 243 <div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span> </div>
 244 <div class="line"><a id="l00146" name="l00146"></a><span class="lineno"><a class="line" href="structdma__hw__t.html">  146</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 245 <div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>    <a class="code hl_struct" href="structdma__channel__hw__t.html">dma_channel_hw_t</a> ch[12];</div>
 246 <div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span> </div>
 247 <div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    uint32_t _pad0[64];</div>
 248 <div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span> </div>
 249 <div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    <span class="keyword">union </span>{</div>
 250 <div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>        <span class="keyword">struct </span>{</div>
 251 <div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span>            _REG_(DMA_INTR_OFFSET) <span class="comment">// DMA_INTR</span></div>
 252 <div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>            <span class="comment">// Interrupt Status (raw)</span></div>
 253 <div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>            <span class="comment">// 0x0000ffff [15:0]  INTR         (0x0000) Raw interrupt status for DMA Channels 0</span></div>
 254 <div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span>            io_rw_32 intr;</div>
 255 <div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span> </div>
 256 <div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>            _REG_(DMA_INTE0_OFFSET) <span class="comment">// DMA_INTE0</span></div>
 257 <div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span>            <span class="comment">// Interrupt Enables for IRQ 0</span></div>
 258 <div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span>            <span class="comment">// 0x0000ffff [15:0]  INTE0        (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0</span></div>
 259 <div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>            io_rw_32 inte0;</div>
 260 <div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span> </div>
 261 <div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>            _REG_(DMA_INTF0_OFFSET) <span class="comment">// DMA_INTF0</span></div>
 262 <div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>            <span class="comment">// Force Interrupts</span></div>
 263 <div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>            <span class="comment">// 0x0000ffff [15:0]  INTF0        (0x0000) Write 1s to force the corresponding bits in INTE0                  </span></div>
 264 <div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>            io_rw_32 intf0;</div>
 265 <div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span> </div>
 266 <div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span>            _REG_(DMA_INTS0_OFFSET) <span class="comment">// DMA_INTS0</span></div>
 267 <div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>            <span class="comment">// Interrupt Status for IRQ 0</span></div>
 268 <div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>            <span class="comment">// 0x0000ffff [15:0]  INTS0        (0x0000) Indicates active channel interrupt requests which are...</span></div>
 269 <div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>            io_rw_32 ints0;</div>
 270 <div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span> </div>
 271 <div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>            uint32_t __pad0;</div>
 272 <div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span> </div>
 273 <div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span>            _REG_(DMA_INTE1_OFFSET) <span class="comment">// DMA_INTE1</span></div>
 274 <div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span>            <span class="comment">// Interrupt Enables for IRQ 1</span></div>
 275 <div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span>            <span class="comment">// 0x0000ffff [15:0]  INTE1        (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1</span></div>
 276 <div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span>            io_rw_32 inte1;</div>
 277 <div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span> </div>
 278 <div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>            _REG_(DMA_INTF1_OFFSET) <span class="comment">// DMA_INTF1</span></div>
 279 <div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span>            <span class="comment">// Force Interrupts for IRQ 1</span></div>
 280 <div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span>            <span class="comment">// 0x0000ffff [15:0]  INTF1        (0x0000) Write 1s to force the corresponding bits in INTF1</span></div>
 281 <div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span>            io_rw_32 intf1;</div>
 282 <div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span> </div>
 283 <div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span>            _REG_(DMA_INTS1_OFFSET) <span class="comment">// DMA_INTS1</span></div>
 284 <div class="line"><a id="l00186" name="l00186"></a><span class="lineno">  186</span>            <span class="comment">// Interrupt Status (masked) for IRQ 1</span></div>
 285 <div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span>            <span class="comment">// 0x0000ffff [15:0]  INTS1        (0x0000) Indicates active channel interrupt requests which are...</span></div>
 286 <div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span>            io_rw_32 ints1;</div>
 287 <div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span>        };</div>
 288 <div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span>        <a class="code hl_struct" href="structdma__irq__ctrl__hw__t.html">dma_irq_ctrl_hw_t</a> irq_ctrl[2];</div>
 289 <div class="line"><a id="l00191" name="l00191"></a><span class="lineno">  191</span>    };</div>
 290 <div class="line"><a id="l00192" name="l00192"></a><span class="lineno">  192</span> </div>
 291 <div class="line"><a id="l00193" name="l00193"></a><span class="lineno">  193</span>    <span class="comment">// (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)</span></div>
 292 <div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span>    _REG_(DMA_TIMER0_OFFSET) <span class="comment">// DMA_TIMER0</span></div>
 293 <div class="line"><a id="l00195" name="l00195"></a><span class="lineno">  195</span>    <span class="comment">// Pacing (X/Y) Fractional Timer +</span></div>
 294 <div class="line"><a id="l00196" name="l00196"></a><span class="lineno">  196</span>    <span class="comment">// 0xffff0000 [31:16] X            (0x0000) Pacing Timer Dividend</span></div>
 295 <div class="line"><a id="l00197" name="l00197"></a><span class="lineno">  197</span>    <span class="comment">// 0x0000ffff [15:0]  Y            (0x0000) Pacing Timer Divisor</span></div>
 296 <div class="line"><a id="l00198" name="l00198"></a><span class="lineno">  198</span>    io_rw_32 timer[4];</div>
 297 <div class="line"><a id="l00199" name="l00199"></a><span class="lineno">  199</span> </div>
 298 <div class="line"><a id="l00200" name="l00200"></a><span class="lineno">  200</span>    _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) <span class="comment">// DMA_MULTI_CHAN_TRIGGER</span></div>
 299 <div class="line"><a id="l00201" name="l00201"></a><span class="lineno">  201</span>    <span class="comment">// Trigger one or more channels simultaneously</span></div>
 300 <div class="line"><a id="l00202" name="l00202"></a><span class="lineno">  202</span>    <span class="comment">// 0x0000ffff [15:0]  MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel</span></div>
 301 <div class="line"><a id="l00203" name="l00203"></a><span class="lineno">  203</span>    io_wo_32 multi_channel_trigger;</div>
 302 <div class="line"><a id="l00204" name="l00204"></a><span class="lineno">  204</span> </div>
 303 <div class="line"><a id="l00205" name="l00205"></a><span class="lineno">  205</span>    _REG_(DMA_SNIFF_CTRL_OFFSET) <span class="comment">// DMA_SNIFF_CTRL</span></div>
 304 <div class="line"><a id="l00206" name="l00206"></a><span class="lineno">  206</span>    <span class="comment">// Sniffer Control</span></div>
 305 <div class="line"><a id="l00207" name="l00207"></a><span class="lineno">  207</span>    <span class="comment">// 0x00000800 [11]    OUT_INV      (0) If set, the result appears inverted (bitwise complement)...</span></div>
 306 <div class="line"><a id="l00208" name="l00208"></a><span class="lineno">  208</span>    <span class="comment">// 0x00000400 [10]    OUT_REV      (0) If set, the result appears bit-reversed when read</span></div>
 307 <div class="line"><a id="l00209" name="l00209"></a><span class="lineno">  209</span>    <span class="comment">// 0x00000200 [9]     BSWAP        (0) Locally perform a byte reverse on the sniffed data,...</span></div>
 308 <div class="line"><a id="l00210" name="l00210"></a><span class="lineno">  210</span>    <span class="comment">// 0x000001e0 [8:5]   CALC         (0x0) </span></div>
 309 <div class="line"><a id="l00211" name="l00211"></a><span class="lineno">  211</span>    <span class="comment">// 0x0000001e [4:1]   DMACH        (0x0) DMA channel for Sniffer to observe</span></div>
 310 <div class="line"><a id="l00212" name="l00212"></a><span class="lineno">  212</span>    <span class="comment">// 0x00000001 [0]     EN           (0) Enable sniffer</span></div>
 311 <div class="line"><a id="l00213" name="l00213"></a><span class="lineno">  213</span>    io_rw_32 sniff_ctrl;</div>
 312 <div class="line"><a id="l00214" name="l00214"></a><span class="lineno">  214</span> </div>
 313 <div class="line"><a id="l00215" name="l00215"></a><span class="lineno">  215</span>    _REG_(DMA_SNIFF_DATA_OFFSET) <span class="comment">// DMA_SNIFF_DATA</span></div>
 314 <div class="line"><a id="l00216" name="l00216"></a><span class="lineno">  216</span>    <span class="comment">// Data accumulator for sniff hardware</span></div>
 315 <div class="line"><a id="l00217" name="l00217"></a><span class="lineno">  217</span>    <span class="comment">// 0xffffffff [31:0]  SNIFF_DATA   (0x00000000) Write an initial seed value here before starting a DMA...</span></div>
 316 <div class="line"><a id="l00218" name="l00218"></a><span class="lineno">  218</span>    io_rw_32 sniff_data;</div>
 317 <div class="line"><a id="l00219" name="l00219"></a><span class="lineno">  219</span> </div>
 318 <div class="line"><a id="l00220" name="l00220"></a><span class="lineno">  220</span>    uint32_t _pad1;</div>
 319 <div class="line"><a id="l00221" name="l00221"></a><span class="lineno">  221</span> </div>
 320 <div class="line"><a id="l00222" name="l00222"></a><span class="lineno">  222</span>    _REG_(DMA_FIFO_LEVELS_OFFSET) <span class="comment">// DMA_FIFO_LEVELS</span></div>
 321 <div class="line"><a id="l00223" name="l00223"></a><span class="lineno">  223</span>    <span class="comment">// Debug RAF, WAF, TDF levels</span></div>
 322 <div class="line"><a id="l00224" name="l00224"></a><span class="lineno">  224</span>    <span class="comment">// 0x00ff0000 [23:16] RAF_LVL      (0x00) Current Read-Address-FIFO fill level</span></div>
 323 <div class="line"><a id="l00225" name="l00225"></a><span class="lineno">  225</span>    <span class="comment">// 0x0000ff00 [15:8]  WAF_LVL      (0x00) Current Write-Address-FIFO fill level</span></div>
 324 <div class="line"><a id="l00226" name="l00226"></a><span class="lineno">  226</span>    <span class="comment">// 0x000000ff [7:0]   TDF_LVL      (0x00) Current Transfer-Data-FIFO fill level</span></div>
 325 <div class="line"><a id="l00227" name="l00227"></a><span class="lineno">  227</span>    io_ro_32 fifo_levels;</div>
 326 <div class="line"><a id="l00228" name="l00228"></a><span class="lineno">  228</span> </div>
 327 <div class="line"><a id="l00229" name="l00229"></a><span class="lineno">  229</span>    _REG_(DMA_CHAN_ABORT_OFFSET) <span class="comment">// DMA_CHAN_ABORT</span></div>
 328 <div class="line"><a id="l00230" name="l00230"></a><span class="lineno">  230</span>    <span class="comment">// Abort an in-progress transfer sequence on one or more channels</span></div>
 329 <div class="line"><a id="l00231" name="l00231"></a><span class="lineno">  231</span>    <span class="comment">// 0x0000ffff [15:0]  CHAN_ABORT   (0x0000) Each bit corresponds to a channel</span></div>
 330 <div class="line"><a id="l00232" name="l00232"></a><span class="lineno">  232</span>    io_wo_32 abort;</div>
 331 <div class="line"><a id="l00233" name="l00233"></a><span class="lineno">  233</span>} <a class="code hl_struct" href="structdma__hw__t.html">dma_hw_t</a>;</div>
 332 <div class="line"><a id="l00234" name="l00234"></a><span class="lineno">  234</span> </div>
 333 <div class="line"><a id="l00235" name="l00235"></a><span class="lineno">  235</span><span class="preprocessor">#define dma_hw ((dma_hw_t *)DMA_BASE)</span></div>
 334 <div class="line"><a id="l00236" name="l00236"></a><span class="lineno">  236</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structdma__hw__t.html">dma_hw_t</a>) == 0x0448, <span class="stringliteral">&quot;&quot;</span>);</div>
 335 <div class="line"><a id="l00237" name="l00237"></a><span class="lineno">  237</span> </div>
 336 <div class="line"><a id="l00238" name="l00238"></a><span class="lineno">  238</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_DMA_H</span></div>
 337 <div class="line"><a id="l00239" name="l00239"></a><span class="lineno">  239</span> </div>
 338 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 339 <div class="ttc" id="astructdma__channel__hw__t_html"><div class="ttname"><a href="structdma__channel__hw__t.html">dma_channel_hw_t</a></div><div class="ttdef"><b>Definition:</b> dma.h:27</div></div>
 340 <div class="ttc" id="astructdma__hw__t_html"><div class="ttname"><a href="structdma__hw__t.html">dma_hw_t</a></div><div class="ttdef"><b>Definition:</b> dma.h:146</div></div>
 341 <div class="ttc" id="astructdma__irq__ctrl__hw__t_html"><div class="ttname"><a href="structdma__irq__ctrl__hw__t.html">dma_irq_ctrl_hw_t</a></div><div class="ttdef"><b>Definition:</b> dma.h:124</div></div>
 342 </div><!-- fragment --></div><!-- contents -->
 343 </div><!-- doc-content -->
 344
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