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 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">qmi.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_QMI_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_QMI_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/qmi.h&quot;</span></div>
 115 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
 116 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi</span></div>
 117 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
 118 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 119 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/qmi.h.</span></div>
 120 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
 121 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 122 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 123 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
 124 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structqmi__mem__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 125 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    _REG_(QMI_M0_TIMING_OFFSET) <span class="comment">// QMI_M0_TIMING</span></div>
 126 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    <span class="comment">// Timing configuration register for memory address window 0</span></div>
 127 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// 0xc0000000 [31:30] COOLDOWN     (0x1) Chip select cooldown period</span></div>
 128 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0x30000000 [29:28] PAGEBREAK    (0x0) When page break is enabled, chip select will...</span></div>
 129 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// 0x02000000 [25]    SELECT_SETUP (0) Add up to one additional system clock cycle of setup...</span></div>
 130 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    <span class="comment">// 0x01800000 [24:23] SELECT_HOLD  (0x0) Add up to three additional system clock cycles of active...</span></div>
 131 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    <span class="comment">// 0x007e0000 [22:17] MAX_SELECT   (0x00) Enforce a maximum assertion duration for this window&#39;s...</span></div>
 132 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    <span class="comment">// 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window&#39;s chip select is deasserted, it...</span></div>
 133 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    <span class="comment">// 0x00000700 [10:8]  RXDELAY      (0x0) Delay the read data sample timing, in units of one half...</span></div>
 134 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    <span class="comment">// 0x000000ff [7:0]   CLKDIV       (0x04) Clock divisor</span></div>
 135 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    io_rw_32 timing;</div>
 136 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span> </div>
 137 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    _REG_(QMI_M0_RFMT_OFFSET) <span class="comment">// QMI_M0_RFMT</span></div>
 138 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// Read transfer format configuration for memory address window 0.</span></div>
 139 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// 0x10000000 [28]    DTR          (0) Enable double transfer rate (DTR) for read commands:...</span></div>
 140 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// 0x00070000 [18:16] DUMMY_LEN    (0x0) Length of dummy phase between command suffix and data...</span></div>
 141 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    <span class="comment">// 0x0000c000 [15:14] SUFFIX_LEN   (0x0) Length of post-address command suffix, in units of 4 bits</span></div>
 142 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    <span class="comment">// 0x00001000 [12]    PREFIX_LEN   (1) Length of command prefix, in units of 8 bits</span></div>
 143 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// 0x00000300 [9:8]   DATA_WIDTH   (0x0) The width used for the data transfer</span></div>
 144 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    <span class="comment">// 0x000000c0 [7:6]   DUMMY_WIDTH  (0x0) The width used for the dummy phase, if any</span></div>
 145 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// 0x00000030 [5:4]   SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any</span></div>
 146 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0x0000000c [3:2]   ADDR_WIDTH   (0x0) The transfer width used for the address</span></div>
 147 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    <span class="comment">// 0x00000003 [1:0]   PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any</span></div>
 148 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>    io_rw_32 rfmt;</div>
 149 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span> </div>
 150 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    _REG_(QMI_M0_RCMD_OFFSET) <span class="comment">// QMI_M0_RCMD</span></div>
 151 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// Command constants used for reads from memory address window 0.</span></div>
 152 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0x0000ff00 [15:8]  SUFFIX       (0xa0) The command suffix bits following the address, if...</span></div>
 153 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x000000ff [7:0]   PREFIX       (0x03) The command prefix bits to prepend on each new transfer,...</span></div>
 154 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    io_rw_32 rcmd;</div>
 155 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span> </div>
 156 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    _REG_(QMI_M0_WFMT_OFFSET) <span class="comment">// QMI_M0_WFMT</span></div>
 157 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// Write transfer format configuration for memory address window 0.</span></div>
 158 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    <span class="comment">// 0x10000000 [28]    DTR          (0) Enable double transfer rate (DTR) for write commands:...</span></div>
 159 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    <span class="comment">// 0x00070000 [18:16] DUMMY_LEN    (0x0) Length of dummy phase between command suffix and data...</span></div>
 160 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    <span class="comment">// 0x0000c000 [15:14] SUFFIX_LEN   (0x0) Length of post-address command suffix, in units of 4 bits</span></div>
 161 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    <span class="comment">// 0x00001000 [12]    PREFIX_LEN   (1) Length of command prefix, in units of 8 bits</span></div>
 162 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// 0x00000300 [9:8]   DATA_WIDTH   (0x0) The width used for the data transfer</span></div>
 163 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    <span class="comment">// 0x000000c0 [7:6]   DUMMY_WIDTH  (0x0) The width used for the dummy phase, if any</span></div>
 164 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    <span class="comment">// 0x00000030 [5:4]   SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any</span></div>
 165 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    <span class="comment">// 0x0000000c [3:2]   ADDR_WIDTH   (0x0) The transfer width used for the address</span></div>
 166 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    <span class="comment">// 0x00000003 [1:0]   PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any</span></div>
 167 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    io_rw_32 wfmt;</div>
 168 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span> </div>
 169 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    _REG_(QMI_M0_WCMD_OFFSET) <span class="comment">// QMI_M0_WCMD</span></div>
 170 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// Command constants used for writes to memory address window 0.</span></div>
 171 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    <span class="comment">// 0x0000ff00 [15:8]  SUFFIX       (0xa0) The command suffix bits following the address, if...</span></div>
 172 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    <span class="comment">// 0x000000ff [7:0]   PREFIX       (0x02) The command prefix bits to prepend on each new transfer,...</span></div>
 173 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    io_rw_32 wcmd;</div>
 174 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>} <a class="code hl_struct" href="structqmi__mem__hw__t.html">qmi_mem_hw_t</a>;</div>
 175 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span> </div>
 176 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno"><a class="line" href="structqmi__hw__t.html">   78</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 177 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    _REG_(QMI_DIRECT_CSR_OFFSET) <span class="comment">// QMI_DIRECT_CSR</span></div>
 178 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    <span class="comment">// Control and status for direct serial mode</span></div>
 179 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    <span class="comment">// 0xc0000000 [31:30] RXDELAY      (0x0) Delay the read data sample timing, in units of one half...</span></div>
 180 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    <span class="comment">// 0x3fc00000 [29:22] CLKDIV       (0x06) Clock divisor for direct serial mode</span></div>
 181 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    <span class="comment">// 0x001c0000 [20:18] RXLEVEL      (0x0) Current level of DIRECT_RX FIFO</span></div>
 182 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    <span class="comment">// 0x00020000 [17]    RXFULL       (0) When 1, the DIRECT_RX FIFO is currently full</span></div>
 183 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    <span class="comment">// 0x00010000 [16]    RXEMPTY      (0) When 1, the DIRECT_RX FIFO is currently empty</span></div>
 184 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    <span class="comment">// 0x00007000 [14:12] TXLEVEL      (0x0) Current level of DIRECT_TX FIFO</span></div>
 185 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    <span class="comment">// 0x00000800 [11]    TXEMPTY      (0) When 1, the DIRECT_TX FIFO is currently empty</span></div>
 186 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    <span class="comment">// 0x00000400 [10]    TXFULL       (0) When 1, the DIRECT_TX FIFO is currently full</span></div>
 187 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// 0x00000080 [7]     AUTO_CS1N    (0) When 1, automatically assert the CS1n chip select line...</span></div>
 188 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    <span class="comment">// 0x00000040 [6]     AUTO_CS0N    (0) When 1, automatically assert the CS0n chip select line...</span></div>
 189 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>    <span class="comment">// 0x00000008 [3]     ASSERT_CS1N  (0) When 1, assert (i</span></div>
 190 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    <span class="comment">// 0x00000004 [2]     ASSERT_CS0N  (0) When 1, assert (i</span></div>
 191 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    <span class="comment">// 0x00000002 [1]     BUSY         (0) Direct mode busy flag</span></div>
 192 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// 0x00000001 [0]     EN           (0) Enable direct mode</span></div>
 193 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    io_rw_32 direct_csr;</div>
 194 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span> </div>
 195 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    _REG_(QMI_DIRECT_TX_OFFSET) <span class="comment">// QMI_DIRECT_TX</span></div>
 196 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    <span class="comment">// Transmit FIFO for direct mode</span></div>
 197 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    <span class="comment">// 0x00100000 [20]    NOPUSH       (0) Inhibit the RX FIFO push that would correspond to this...</span></div>
 198 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    <span class="comment">// 0x00080000 [19]    OE           (0) Output enable (active-high)</span></div>
 199 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    <span class="comment">// 0x00040000 [18]    DWIDTH       (0) Data width</span></div>
 200 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>    <span class="comment">// 0x00030000 [17:16] IWIDTH       (0x0) Configure whether this FIFO record is transferred with...</span></div>
 201 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    <span class="comment">// 0x0000ffff [15:0]  DATA         (0x0000) Data pushed here will be clocked out falling edges of...</span></div>
 202 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    io_wo_32 direct_tx;</div>
 203 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span> </div>
 204 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    _REG_(QMI_DIRECT_RX_OFFSET) <span class="comment">// QMI_DIRECT_RX</span></div>
 205 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    <span class="comment">// Receive FIFO for direct mode</span></div>
 206 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    <span class="comment">// 0x0000ffff [15:0]  DIRECT_RX    (0x0000) With each byte clocked out on the serial interface, one...</span></div>
 207 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    io_ro_32 direct_rx;</div>
 208 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span> </div>
 209 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    <a class="code hl_struct" href="structqmi__mem__hw__t.html">qmi_mem_hw_t</a> m[2];</div>
 210 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span> </div>
 211 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    <span class="comment">// (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes)</span></div>
 212 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    _REG_(QMI_ATRANS0_OFFSET) <span class="comment">// QMI_ATRANS0</span></div>
 213 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    <span class="comment">// Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB).</span></div>
 214 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    <span class="comment">// 0x07ff0000 [26:16] SIZE         (0x400) Translation aperture size for this virtual address...</span></div>
 215 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// 0x00000fff [11:0]  BASE         (0x000) Physical address base for this virtual address range, in...</span></div>
 216 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    io_rw_32 atrans[8];</div>
 217 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>} <a class="code hl_struct" href="structqmi__hw__t.html">qmi_hw_t</a>;</div>
 218 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span> </div>
 219 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span><span class="preprocessor">#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE)</span></div>
 220 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structqmi__hw__t.html">qmi_hw_t</a>) == 0x0054, <span class="stringliteral">&quot;&quot;</span>);</div>
 221 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span> </div>
 222 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_QMI_H</span></div>
 223 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span> </div>
 224 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 225 <div class="ttc" id="astructqmi__hw__t_html"><div class="ttname"><a href="structqmi__hw__t.html">qmi_hw_t</a></div><div class="ttdef"><b>Definition:</b> qmi.h:78</div></div>
 226 <div class="ttc" id="astructqmi__mem__hw__t_html"><div class="ttname"><a href="structqmi__mem__hw__t.html">qmi_mem_hw_t</a></div><div class="ttdef"><b>Definition:</b> qmi.h:26</div></div>
 227 </div><!-- fragment --></div><!-- contents -->
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 229
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