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 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">otp.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_OTP_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_OTP_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/otp.h&quot;</span></div>
 115 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
 116 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_otp</span></div>
 117 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
 118 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 119 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/otp.h.</span></div>
 120 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
 121 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 122 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 123 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
 124 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structotp__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 125 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    <span class="comment">// (Description copied from array index 0 register OTP_SW_LOCK0 applies similarly to other array indexes)</span></div>
 126 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    _REG_(OTP_SW_LOCK0_OFFSET) <span class="comment">// OTP_SW_LOCK0</span></div>
 127 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// Software lock register for page 0.</span></div>
 128 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0x0000000c [3:2]   NSEC         (-) Non-secure lock status</span></div>
 129 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// 0x00000003 [1:0]   SEC          (-) Secure lock status</span></div>
 130 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    io_rw_32 sw_lock[64];</div>
 131 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span> </div>
 132 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    _REG_(OTP_SBPI_INSTR_OFFSET) <span class="comment">// OTP_SBPI_INSTR</span></div>
 133 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    <span class="comment">// Dispatch instructions to the SBPI interface, used for programming the OTP fuses</span></div>
 134 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    <span class="comment">// 0x40000000 [30]    EXEC         (0) Execute instruction</span></div>
 135 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    <span class="comment">// 0x20000000 [29]    IS_WR        (0) Payload type is write</span></div>
 136 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    <span class="comment">// 0x10000000 [28]    HAS_PAYLOAD  (0) Instruction has payload (data to be written or to be read)</span></div>
 137 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// 0x0f000000 [27:24] PAYLOAD_SIZE_M1 (0x0) Instruction payload size in bytes minus 1</span></div>
 138 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// 0x00ff0000 [23:16] TARGET       (0x00) Instruction target, it can be PMC (0x3a) or DAP (0x02)</span></div>
 139 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// 0x0000ff00 [15:8]  CMD          (0x00) </span></div>
 140 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// 0x000000ff [7:0]   SHORT_WDATA  (0x00) wdata to be used only when payload_size_m1=0</span></div>
 141 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    io_rw_32 sbpi_instr;</div>
 142 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span> </div>
 143 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// (Description copied from array index 0 register OTP_SBPI_WDATA_0 applies similarly to other array indexes)</span></div>
 144 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    _REG_(OTP_SBPI_WDATA_0_OFFSET) <span class="comment">// OTP_SBPI_WDATA_0</span></div>
 145 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// SBPI write payload bytes 3</span></div>
 146 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0xffffffff [31:0]  SBPI_WDATA_0 (0x00000000) </span></div>
 147 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    io_rw_32 sbpi_wdata[4];</div>
 148 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span> </div>
 149 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// (Description copied from array index 0 register OTP_SBPI_RDATA_0 applies similarly to other array indexes)</span></div>
 150 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    _REG_(OTP_SBPI_RDATA_0_OFFSET) <span class="comment">// OTP_SBPI_RDATA_0</span></div>
 151 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// Read payload bytes 3</span></div>
 152 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0xffffffff [31:0]  SBPI_RDATA_0 (0x00000000) </span></div>
 153 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    io_ro_32 sbpi_rdata[4];</div>
 154 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span> </div>
 155 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    _REG_(OTP_SBPI_STATUS_OFFSET) <span class="comment">// OTP_SBPI_STATUS</span></div>
 156 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x00ff0000 [23:16] MISO         (-) SBPI MISO (master in - slave out): response from SBPI</span></div>
 157 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x00001000 [12]    FLAG         (-) SBPI flag</span></div>
 158 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    <span class="comment">// 0x00000100 [8]     INSTR_MISS   (0) Last instruction missed (dropped), as the previous has...</span></div>
 159 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    <span class="comment">// 0x00000010 [4]     INSTR_DONE   (0) Last instruction done</span></div>
 160 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    <span class="comment">// 0x00000001 [0]     RDATA_VLD    (0) Read command has returned data</span></div>
 161 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    io_rw_32 sbpi_status;</div>
 162 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span> </div>
 163 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    _REG_(OTP_USR_OFFSET) <span class="comment">// OTP_USR</span></div>
 164 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    <span class="comment">// Controls for APB data read interface (USER interface)</span></div>
 165 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    <span class="comment">// 0x00000010 [4]     PD           (0) Power-down; 1 disables current reference</span></div>
 166 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    <span class="comment">// 0x00000001 [0]     DCTRL        (1) 1 enables USER interface; 0 disables USER interface...</span></div>
 167 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    io_rw_32 usr;</div>
 168 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span> </div>
 169 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    _REG_(OTP_DBG_OFFSET) <span class="comment">// OTP_DBG</span></div>
 170 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// Debug for OTP power-on state machine</span></div>
 171 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    <span class="comment">// 0x00001000 [12]    CUSTOMER_RMA_FLAG (-) The chip is in RMA mode</span></div>
 172 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    <span class="comment">// 0x000000f0 [7:4]   PSM_STATE    (-) Monitor the PSM FSM&#39;s state</span></div>
 173 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    <span class="comment">// 0x00000008 [3]     ROSC_UP      (-) Ring oscillator is up and running</span></div>
 174 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    <span class="comment">// 0x00000004 [2]     ROSC_UP_SEEN (0) Ring oscillator was seen up and running</span></div>
 175 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    <span class="comment">// 0x00000002 [1]     BOOT_DONE    (-) PSM boot done status flag</span></div>
 176 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// 0x00000001 [0]     PSM_DONE     (-) PSM done status flag</span></div>
 177 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    io_rw_32 dbg;</div>
 178 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span> </div>
 179 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    uint32_t _pad0;</div>
 180 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span> </div>
 181 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    _REG_(OTP_BIST_OFFSET) <span class="comment">// OTP_BIST</span></div>
 182 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    <span class="comment">// During BIST, count address locations that have at least one leaky bit</span></div>
 183 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    <span class="comment">// 0x40000000 [30]    CNT_FAIL     (-) Flag if the count of address locations with at least one...</span></div>
 184 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    <span class="comment">// 0x20000000 [29]    CNT_CLR      (0) Clear counter before use</span></div>
 185 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    <span class="comment">// 0x10000000 [28]    CNT_ENA      (0) Enable the counter before the BIST function is initiated</span></div>
 186 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    <span class="comment">// 0x0fff0000 [27:16] CNT_MAX      (0xfff) The cnt_fail flag will be set if the number of leaky...</span></div>
 187 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// 0x00001fff [12:0]  CNT          (-) Number of locations that have at least one leaky bit</span></div>
 188 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    io_rw_32 bist;</div>
 189 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span> </div>
 190 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    <span class="comment">// (Description copied from array index 0 register OTP_CRT_KEY_W0 applies similarly to other array indexes)</span></div>
 191 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    _REG_(OTP_CRT_KEY_W0_OFFSET) <span class="comment">// OTP_CRT_KEY_W0</span></div>
 192 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// Word 0 (bits 31</span></div>
 193 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    <span class="comment">// 0xffffffff [31:0]  CRT_KEY_W0   (0x00000000) </span></div>
 194 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    io_wo_32 crt_key_w[4];</div>
 195 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span> </div>
 196 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    _REG_(OTP_CRITICAL_OFFSET) <span class="comment">// OTP_CRITICAL</span></div>
 197 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    <span class="comment">// Quickly check values of critical flags read during boot up</span></div>
 198 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    <span class="comment">// 0x00020000 [17]    RISCV_DISABLE (0) </span></div>
 199 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    <span class="comment">// 0x00010000 [16]    ARM_DISABLE  (0) </span></div>
 200 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>    <span class="comment">// 0x00000060 [6:5]   GLITCH_DETECTOR_SENS (0x0) </span></div>
 201 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    <span class="comment">// 0x00000010 [4]     GLITCH_DETECTOR_ENABLE (0) </span></div>
 202 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    <span class="comment">// 0x00000008 [3]     DEFAULT_ARCHSEL (0) </span></div>
 203 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>    <span class="comment">// 0x00000004 [2]     DEBUG_DISABLE (0) </span></div>
 204 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    <span class="comment">// 0x00000002 [1]     SECURE_DEBUG_DISABLE (0) </span></div>
 205 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    <span class="comment">// 0x00000001 [0]     SECURE_BOOT_ENABLE (0) </span></div>
 206 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    io_ro_32 critical;</div>
 207 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span> </div>
 208 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    _REG_(OTP_KEY_VALID_OFFSET) <span class="comment">// OTP_KEY_VALID</span></div>
 209 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    <span class="comment">// Which keys were valid (enrolled) at boot time</span></div>
 210 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    <span class="comment">// 0x000000ff [7:0]   KEY_VALID    (0x00) </span></div>
 211 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    io_ro_32 key_valid;</div>
 212 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span> </div>
 213 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    _REG_(OTP_DEBUGEN_OFFSET) <span class="comment">// OTP_DEBUGEN</span></div>
 214 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    <span class="comment">// Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD.</span></div>
 215 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// 0x00000100 [8]     MISC         (0) Enable other debug components</span></div>
 216 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    <span class="comment">// 0x00000008 [3]     PROC1_SECURE (0) Permit core 1&#39;s Mem-AP to generate Secure accesses,...</span></div>
 217 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    <span class="comment">// 0x00000004 [2]     PROC1        (0) Enable core 1&#39;s Mem-AP if it is currently disabled</span></div>
 218 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    <span class="comment">// 0x00000002 [1]     PROC0_SECURE (0) Permit core 0&#39;s Mem-AP to generate Secure accesses,...</span></div>
 219 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span>    <span class="comment">// 0x00000001 [0]     PROC0        (0) Enable core 0&#39;s Mem-AP if it is currently disabled</span></div>
 220 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    io_rw_32 debugen;</div>
 221 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span> </div>
 222 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span>    _REG_(OTP_DEBUGEN_LOCK_OFFSET) <span class="comment">// OTP_DEBUGEN_LOCK</span></div>
 223 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    <span class="comment">// Write 1s to lock corresponding bits in DEBUGEN</span></div>
 224 <div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    <span class="comment">// 0x00000100 [8]     MISC         (0) Write 1 to lock the MISC bit of DEBUGEN</span></div>
 225 <div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    <span class="comment">// 0x00000008 [3]     PROC1_SECURE (0) Write 1 to lock the PROC1_SECURE bit of DEBUGEN</span></div>
 226 <div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    <span class="comment">// 0x00000004 [2]     PROC1        (0) Write 1 to lock the PROC1 bit of DEBUGEN</span></div>
 227 <div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span>    <span class="comment">// 0x00000002 [1]     PROC0_SECURE (0) Write 1 to lock the PROC0_SECURE bit of DEBUGEN</span></div>
 228 <div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    <span class="comment">// 0x00000001 [0]     PROC0        (0) Write 1 to lock the PROC0 bit of DEBUGEN</span></div>
 229 <div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    io_rw_32 debugen_lock;</div>
 230 <div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span> </div>
 231 <div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    _REG_(OTP_ARCHSEL_OFFSET) <span class="comment">// OTP_ARCHSEL</span></div>
 232 <div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span>    <span class="comment">// Architecture select (Arm/RISC-V), applied on next processor reset. The default and allowable values of this register are constrained by the critical boot flags.</span></div>
 233 <div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    <span class="comment">// 0x00000002 [1]     CORE1        (0) Select architecture for core 1</span></div>
 234 <div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span>    <span class="comment">// 0x00000001 [0]     CORE0        (0) Select architecture for core 0</span></div>
 235 <div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    io_rw_32 archsel;</div>
 236 <div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span> </div>
 237 <div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    _REG_(OTP_ARCHSEL_STATUS_OFFSET) <span class="comment">// OTP_ARCHSEL_STATUS</span></div>
 238 <div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span>    <span class="comment">// Get the current architecture select state of each core</span></div>
 239 <div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    <span class="comment">// 0x00000002 [1]     CORE1        (0) Current architecture for core 0</span></div>
 240 <div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    <span class="comment">// 0x00000001 [0]     CORE0        (0) Current architecture for core 0</span></div>
 241 <div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    io_ro_32 archsel_status;</div>
 242 <div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span> </div>
 243 <div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>    _REG_(OTP_BOOTDIS_OFFSET) <span class="comment">// OTP_BOOTDIS</span></div>
 244 <div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span>    <span class="comment">// Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up.</span></div>
 245 <div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>    <span class="comment">// 0x00000002 [1]     NEXT         (0) This flag always ORs writes into its current contents</span></div>
 246 <div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span>    <span class="comment">// 0x00000001 [0]     NOW          (0) When the core is powered down, the current value of...</span></div>
 247 <div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    io_rw_32 bootdis;</div>
 248 <div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span> </div>
 249 <div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    _REG_(OTP_INTR_OFFSET) <span class="comment">// OTP_INTR</span></div>
 250 <div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>    <span class="comment">// Raw Interrupts</span></div>
 251 <div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span>    <span class="comment">// 0x00000010 [4]     APB_RD_NSEC_FAIL (0) </span></div>
 252 <div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    <span class="comment">// 0x00000008 [3]     APB_RD_SEC_FAIL (0) </span></div>
 253 <div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>    <span class="comment">// 0x00000004 [2]     APB_DCTRL_FAIL (0) </span></div>
 254 <div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span>    <span class="comment">// 0x00000002 [1]     SBPI_WR_FAIL (0) </span></div>
 255 <div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span>    <span class="comment">// 0x00000001 [0]     SBPI_FLAG_N  (0) </span></div>
 256 <div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    io_rw_32 intr;</div>
 257 <div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span> </div>
 258 <div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span>    _REG_(OTP_INTE_OFFSET) <span class="comment">// OTP_INTE</span></div>
 259 <div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    <span class="comment">// Interrupt Enable</span></div>
 260 <div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// 0x00000010 [4]     APB_RD_NSEC_FAIL (0) </span></div>
 261 <div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    <span class="comment">// 0x00000008 [3]     APB_RD_SEC_FAIL (0) </span></div>
 262 <div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>    <span class="comment">// 0x00000004 [2]     APB_DCTRL_FAIL (0) </span></div>
 263 <div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    <span class="comment">// 0x00000002 [1]     SBPI_WR_FAIL (0) </span></div>
 264 <div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>    <span class="comment">// 0x00000001 [0]     SBPI_FLAG_N  (0) </span></div>
 265 <div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span>    io_rw_32 inte;</div>
 266 <div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span> </div>
 267 <div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    _REG_(OTP_INTF_OFFSET) <span class="comment">// OTP_INTF</span></div>
 268 <div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    <span class="comment">// Interrupt Force</span></div>
 269 <div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>    <span class="comment">// 0x00000010 [4]     APB_RD_NSEC_FAIL (0) </span></div>
 270 <div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>    <span class="comment">// 0x00000008 [3]     APB_RD_SEC_FAIL (0) </span></div>
 271 <div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>    <span class="comment">// 0x00000004 [2]     APB_DCTRL_FAIL (0) </span></div>
 272 <div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span>    <span class="comment">// 0x00000002 [1]     SBPI_WR_FAIL (0) </span></div>
 273 <div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span>    <span class="comment">// 0x00000001 [0]     SBPI_FLAG_N  (0) </span></div>
 274 <div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span>    io_rw_32 intf;</div>
 275 <div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span> </div>
 276 <div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span>    _REG_(OTP_INTS_OFFSET) <span class="comment">// OTP_INTS</span></div>
 277 <div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span>    <span class="comment">// Interrupt status after masking &amp; forcing</span></div>
 278 <div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>    <span class="comment">// 0x00000010 [4]     APB_RD_NSEC_FAIL (0) </span></div>
 279 <div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span>    <span class="comment">// 0x00000008 [3]     APB_RD_SEC_FAIL (0) </span></div>
 280 <div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span>    <span class="comment">// 0x00000004 [2]     APB_DCTRL_FAIL (0) </span></div>
 281 <div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span>    <span class="comment">// 0x00000002 [1]     SBPI_WR_FAIL (0) </span></div>
 282 <div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span>    <span class="comment">// 0x00000001 [0]     SBPI_FLAG_N  (0) </span></div>
 283 <div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span>    io_ro_32 ints;</div>
 284 <div class="line"><a id="l00186" name="l00186"></a><span class="lineno">  186</span>} <a class="code hl_struct" href="structotp__hw__t.html">otp_hw_t</a>;</div>
 285 <div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span> </div>
 286 <div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span><span class="preprocessor">#define otp_hw ((otp_hw_t *)OTP_BASE)</span></div>
 287 <div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structotp__hw__t.html">otp_hw_t</a>) == 0x0174, <span class="stringliteral">&quot;&quot;</span>);</div>
 288 <div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span> </div>
 289 <div class="line"><a id="l00191" name="l00191"></a><span class="lineno">  191</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_OTP_H</span></div>
 290 <div class="line"><a id="l00192" name="l00192"></a><span class="lineno">  192</span> </div>
 291 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 292 <div class="ttc" id="astructotp__hw__t_html"><div class="ttname"><a href="structotp__hw__t.html">otp_hw_t</a></div><div class="ttdef"><b>Definition:</b> otp.h:26</div></div>
 293 </div><!-- fragment --></div><!-- contents -->
 294 </div><!-- doc-content -->
 295
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