web/docs/m0plus_8h_source.html

   1 <!-- HTML header for doxygen 1.8.20-->
   2 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
   3 <html xmlns="http://www.w3.org/1999/xhtml">
   4 <head>
   5         <meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
   6         <meta http-equiv="X-UA-Compatible" content="IE=9"/>
   7         <meta name="generator" content="Doxygen 1.9.4"/>
   8         <meta name="viewport" content="width=device-width, initial-scale=1"/>
   9         <title>Raspberry Pi Pico SDK: include/hardware/structs/m0plus.h Source File</title>
  10         <!-- <link href="tabs.css" rel="stylesheet" type="text/css"/> -->
  11         <script type="text/javascript" src="jquery.js"></script>
  12         <script type="text/javascript" src="dynsections.js"></script>
  13         <link href="navtree.css" rel="stylesheet" type="text/css"/>
  14 <script type="text/javascript" src="resize.js"></script>
  15 <script type="text/javascript" src="navtreedata.js"></script>
  16 <script type="text/javascript" src="navtree.js"></script>
  17         <link href="search/search.css" rel="stylesheet" type="text/css"/>
  18 <script type="text/javascript" src="search/searchdata.js"></script>
  19 <script type="text/javascript" src="search/search.js"></script>
  20     <link href="https://fonts.googleapis.com/css2?family=Roboto:wght@300;400;500&display=swap" rel="stylesheet">
  21         <link href="doxygen.css" rel="stylesheet" type="text/css" />
  22         <link href="normalise.css" rel="stylesheet" type="text/css"/>
  23 <link href="main.css" rel="stylesheet" type="text/css"/>
  24 <link href="styles.css" rel="stylesheet" type="text/css"/>
  25 </head>
  26 <body>
  27         <div class="navigation-mobile">
  28                 <div class="logo--mobile">
  29                         <a href="/"><img src="logo-mobile.svg" alt="Raspberry Pi"></a>
  30                 </div>
  31                 <div class="navigation-toggle">
  32                         <span class="line-1"></span>
  33                         <span class="line-2">
  34                                 <p>Menu Toggle</p>
  35                         </span>
  36                         <span class="line-3"></span>
  37                 </div>
  38         </div>
  39         <div id="top"><!-- do not remove this div, it is closed by doxygen! -->
  40                 <div class="logo">
  41                         <a href="index.html"> <img src="logo.svg" alt="Raspberry Pi"></a>
  42                         <span style="display: inline-block; margin-top: 10px;">
  43                                 v2.0.0
  44                         </span>
  45                 </div>
  46                 <div class="navigation-footer">
  47                         <img src="logo-mobile.svg" alt="Raspberry Pi">
  48                         <a href="https://www.raspberrypi.com/" target="_blank">By Raspberry Pi Ltd</a>
  49                 </div>
  50 <!--            <div class="search">
  51                         <form>
  52                                 <input type="search" name="search" id="search" placeholder="Search">
  53                                 <input type="submit" value="Search">
  54                         </form>
  55                 </div> -->
  56 <!-- Generated by Doxygen 1.9.4 -->
  57 <script type="text/javascript">
  58 /* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */
  59 var searchBox = new SearchBox("searchBox", "search",'Search','.html');
  60 /* @license-end */
  61 </script>
  62 <script type="text/javascript" src="menudata.js"></script>
  63 <script type="text/javascript" src="menu.js"></script>
  64 <script type="text/javascript">
  65 /* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */
  66 $(function() {
  67   initMenu('',true,false,'search.php','Search');
  68   $(document).ready(function() { init_search(); });
  69 });
  70 /* @license-end */
  71 </script>
  72 <div id="main-nav"></div>
  73 </div><!-- top -->
  74 <div id="side-nav" class="ui-resizable side-nav-resizable">
  75   <div id="nav-tree">
  76     <div id="nav-tree-contents">
  77       <div id="nav-sync" class="sync"></div>
  78     </div>
  79   </div>
  80   <div id="splitbar" style="-moz-user-select:none;"
  81        class="ui-resizable-handle">
  82   </div>
  83 </div>
  84 <script type="text/javascript">
  85 /* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */
  86 $(document).ready(function(){initNavTree('m0plus_8h_source.html',''); initResizable(); });
  87 /* @license-end */
  88 </script>
  89 <div id="doc-content">
  90 <!-- window showing the filter options -->
  91 <div id="MSearchSelectWindow"
  92      onmouseover="return searchBox.OnSearchSelectShow()"
  93      onmouseout="return searchBox.OnSearchSelectHide()"
  94      onkeydown="return searchBox.OnSearchSelectKey(event)">
  95 </div>
  96
  97 <!-- iframe showing the search results (closed by default) -->
  98 <div id="MSearchResultsWindow">
  99 <iframe src="javascript:void(0)" frameborder="0"
 100         name="MSearchResults" id="MSearchResults">
 101 </iframe>
 102 </div>
 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">m0plus.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_M0PLUS_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_M0PLUS_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/m0plus.h&quot;</span></div>
 115 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
 116 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus</span></div>
 117 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
 118 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 119 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.</span></div>
 120 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
 121 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 122 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 123 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
 124 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structm0plus__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 125 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    uint32_t _pad0[14340];</div>
 126 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span> </div>
 127 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    _REG_(M0PLUS_SYST_CSR_OFFSET) <span class="comment">// M0PLUS_SYST_CSR</span></div>
 128 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// SysTick Control and Status Register</span></div>
 129 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// 0x00010000 [16]    COUNTFLAG    (0) Returns 1 if timer counted to 0 since last time this was read</span></div>
 130 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    <span class="comment">// 0x00000004 [2]     CLKSOURCE    (0) SysTick clock source</span></div>
 131 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    <span class="comment">// 0x00000002 [1]     TICKINT      (0) Enables SysTick exception request: +</span></div>
 132 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) Enable SysTick counter: +</span></div>
 133 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    io_rw_32 syst_csr;</div>
 134 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span> </div>
 135 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    _REG_(M0PLUS_SYST_RVR_OFFSET) <span class="comment">// M0PLUS_SYST_RVR</span></div>
 136 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    <span class="comment">// SysTick Reload Value Register</span></div>
 137 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// 0x00ffffff [23:0]  RELOAD       (0x000000) Value to load into the SysTick Current Value Register...</span></div>
 138 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    io_rw_32 syst_rvr;</div>
 139 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span> </div>
 140 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    _REG_(M0PLUS_SYST_CVR_OFFSET) <span class="comment">// M0PLUS_SYST_CVR</span></div>
 141 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    <span class="comment">// SysTick Current Value Register</span></div>
 142 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    <span class="comment">// 0x00ffffff [23:0]  CURRENT      (0x000000) Reads return the current value of the SysTick counter</span></div>
 143 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    io_rw_32 syst_cvr;</div>
 144 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span> </div>
 145 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    _REG_(M0PLUS_SYST_CALIB_OFFSET) <span class="comment">// M0PLUS_SYST_CALIB</span></div>
 146 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// SysTick Calibration Value Register</span></div>
 147 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    <span class="comment">// 0x80000000 [31]    NOREF        (0) If reads as 1, the Reference clock is not provided - the...</span></div>
 148 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>    <span class="comment">// 0x40000000 [30]    SKEW         (0) If reads as 1, the calibration value for 10ms is inexact...</span></div>
 149 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// 0x00ffffff [23:0]  TENMS        (0x000000) An optional Reload value to be used for 10ms (100Hz)...</span></div>
 150 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    io_ro_32 syst_calib;</div>
 151 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span> </div>
 152 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    uint32_t _pad1[56];</div>
 153 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span> </div>
 154 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    _REG_(M0PLUS_NVIC_ISER_OFFSET) <span class="comment">// M0PLUS_NVIC_ISER</span></div>
 155 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// Interrupt Set-Enable Register</span></div>
 156 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0xffffffff [31:0]  SETENA       (0x00000000) Interrupt set-enable bits</span></div>
 157 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    io_rw_32 nvic_iser;</div>
 158 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span> </div>
 159 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    uint32_t _pad2[31];</div>
 160 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span> </div>
 161 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    _REG_(M0PLUS_NVIC_ICER_OFFSET) <span class="comment">// M0PLUS_NVIC_ICER</span></div>
 162 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// Interrupt Clear-Enable Register</span></div>
 163 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    <span class="comment">// 0xffffffff [31:0]  CLRENA       (0x00000000) Interrupt clear-enable bits</span></div>
 164 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    io_rw_32 nvic_icer;</div>
 165 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span> </div>
 166 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    uint32_t _pad3[31];</div>
 167 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span> </div>
 168 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    _REG_(M0PLUS_NVIC_ISPR_OFFSET) <span class="comment">// M0PLUS_NVIC_ISPR</span></div>
 169 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    <span class="comment">// Interrupt Set-Pending Register</span></div>
 170 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// 0xffffffff [31:0]  SETPEND      (0x00000000) Interrupt set-pending bits</span></div>
 171 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    io_rw_32 nvic_ispr;</div>
 172 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span> </div>
 173 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    uint32_t _pad4[31];</div>
 174 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span> </div>
 175 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    _REG_(M0PLUS_NVIC_ICPR_OFFSET) <span class="comment">// M0PLUS_NVIC_ICPR</span></div>
 176 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// Interrupt Clear-Pending Register</span></div>
 177 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// 0xffffffff [31:0]  CLRPEND      (0x00000000) Interrupt clear-pending bits</span></div>
 178 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    io_rw_32 nvic_icpr;</div>
 179 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span> </div>
 180 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    uint32_t _pad5[95];</div>
 181 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span> </div>
 182 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    <span class="comment">// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)</span></div>
 183 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    _REG_(M0PLUS_NVIC_IPR0_OFFSET) <span class="comment">// M0PLUS_NVIC_IPR0</span></div>
 184 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    <span class="comment">// Interrupt Priority Register 0</span></div>
 185 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    <span class="comment">// 0xc0000000 [31:30] IP_3         (0x0) Priority of interrupt 3</span></div>
 186 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    <span class="comment">// 0x00c00000 [23:22] IP_2         (0x0) Priority of interrupt 2</span></div>
 187 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// 0x0000c000 [15:14] IP_1         (0x0) Priority of interrupt 1</span></div>
 188 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    <span class="comment">// 0x000000c0 [7:6]   IP_0         (0x0) Priority of interrupt 0</span></div>
 189 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>    io_rw_32 nvic_ipr[8];</div>
 190 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span> </div>
 191 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    uint32_t _pad6[568];</div>
 192 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span> </div>
 193 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    _REG_(M0PLUS_CPUID_OFFSET) <span class="comment">// M0PLUS_CPUID</span></div>
 194 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    <span class="comment">// CPUID Base Register</span></div>
 195 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    <span class="comment">// 0xff000000 [31:24] IMPLEMENTER  (0x41) Implementor code: 0x41 = ARM</span></div>
 196 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    <span class="comment">// 0x00f00000 [23:20] VARIANT      (0x0) Major revision number n in the rnpm revision status: +</span></div>
 197 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    <span class="comment">// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +</span></div>
 198 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    <span class="comment">// 0x0000fff0 [15:4]  PARTNO       (0xc60) Number of processor within family: 0xC60 = Cortex-M0+</span></div>
 199 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    <span class="comment">// 0x0000000f [3:0]   REVISION     (0x1) Minor revision number m in the rnpm revision status: +</span></div>
 200 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>    io_ro_32 cpuid;</div>
 201 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span> </div>
 202 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    _REG_(M0PLUS_ICSR_OFFSET) <span class="comment">// M0PLUS_ICSR</span></div>
 203 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>    <span class="comment">// Interrupt Control and State Register</span></div>
 204 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    <span class="comment">// 0x80000000 [31]    NMIPENDSET   (0) Setting this bit will activate an NMI</span></div>
 205 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    <span class="comment">// 0x10000000 [28]    PENDSVSET    (0) PendSV set-pending bit</span></div>
 206 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    <span class="comment">// 0x08000000 [27]    PENDSVCLR    (0) PendSV clear-pending bit</span></div>
 207 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    <span class="comment">// 0x04000000 [26]    PENDSTSET    (0) SysTick exception set-pending bit</span></div>
 208 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    <span class="comment">// 0x02000000 [25]    PENDSTCLR    (0) SysTick exception clear-pending bit</span></div>
 209 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    <span class="comment">// 0x00800000 [23]    ISRPREEMPT   (0) The system can only access this bit when the core is halted</span></div>
 210 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    <span class="comment">// 0x00400000 [22]    ISRPENDING   (0) External interrupt pending flag</span></div>
 211 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    <span class="comment">// 0x001ff000 [20:12] VECTPENDING  (0x000) Indicates the exception number for the highest priority...</span></div>
 212 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    <span class="comment">// 0x000001ff [8:0]   VECTACTIVE   (0x000) Active exception number field</span></div>
 213 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    io_rw_32 icsr;</div>
 214 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span> </div>
 215 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    _REG_(M0PLUS_VTOR_OFFSET) <span class="comment">// M0PLUS_VTOR</span></div>
 216 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    <span class="comment">// Vector Table Offset Register</span></div>
 217 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    <span class="comment">// 0xffffff00 [31:8]  TBLOFF       (0x000000) Bits [31:8] of the indicate the vector table offset address</span></div>
 218 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    io_rw_32 vtor;</div>
 219 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span> </div>
 220 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    _REG_(M0PLUS_AIRCR_OFFSET) <span class="comment">// M0PLUS_AIRCR</span></div>
 221 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span>    <span class="comment">// Application Interrupt and Reset Control Register</span></div>
 222 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span>    <span class="comment">// 0xffff0000 [31:16] VECTKEY      (0x0000) Register key: +</span></div>
 223 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    <span class="comment">// 0x00008000 [15]    ENDIANESS    (0) Data endianness implemented: +</span></div>
 224 <div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    <span class="comment">// 0x00000004 [2]     SYSRESETREQ  (0) Writing 1 to this bit causes the SYSRESETREQ signal to...</span></div>
 225 <div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    <span class="comment">// 0x00000002 [1]     VECTCLRACTIVE (0) Clears all active state information for fixed and...</span></div>
 226 <div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    io_rw_32 aircr;</div>
 227 <div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span> </div>
 228 <div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    _REG_(M0PLUS_SCR_OFFSET) <span class="comment">// M0PLUS_SCR</span></div>
 229 <div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    <span class="comment">// System Control Register</span></div>
 230 <div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span>    <span class="comment">// 0x00000010 [4]     SEVONPEND    (0) Send Event on Pending bit: +</span></div>
 231 <div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    <span class="comment">// 0x00000004 [2]     SLEEPDEEP    (0) Controls whether the processor uses sleep or deep sleep...</span></div>
 232 <div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span>    <span class="comment">// 0x00000002 [1]     SLEEPONEXIT  (0) Indicates sleep-on-exit when returning from Handler mode...</span></div>
 233 <div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    io_rw_32 scr;</div>
 234 <div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span> </div>
 235 <div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    _REG_(M0PLUS_CCR_OFFSET) <span class="comment">// M0PLUS_CCR</span></div>
 236 <div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span>    <span class="comment">// Configuration and Control Register</span></div>
 237 <div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    <span class="comment">// 0x00000200 [9]     STKALIGN     (0) Always reads as one, indicates 8-byte stack alignment on...</span></div>
 238 <div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span>    <span class="comment">// 0x00000008 [3]     UNALIGN_TRP  (0) Always reads as one, indicates that all unaligned...</span></div>
 239 <div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    io_ro_32 ccr;</div>
 240 <div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span> </div>
 241 <div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    uint32_t _pad7;</div>
 242 <div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span> </div>
 243 <div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>    <span class="comment">// (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes)</span></div>
 244 <div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span>    _REG_(M0PLUS_SHPR2_OFFSET) <span class="comment">// M0PLUS_SHPR2</span></div>
 245 <div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>    <span class="comment">// System Handler Priority Register 2</span></div>
 246 <div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span>    <span class="comment">// 0xc0000000 [31:30] PRI_11       (0x0) Priority of system handler 11, SVCall</span></div>
 247 <div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    io_rw_32 shpr[2];</div>
 248 <div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span> </div>
 249 <div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    _REG_(M0PLUS_SHCSR_OFFSET) <span class="comment">// M0PLUS_SHCSR</span></div>
 250 <div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>    <span class="comment">// System Handler Control and State Register</span></div>
 251 <div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span>    <span class="comment">// 0x00008000 [15]    SVCALLPENDED (0) Reads as 1 if SVCall is Pending</span></div>
 252 <div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    io_rw_32 shcsr;</div>
 253 <div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span> </div>
 254 <div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span>    uint32_t _pad8[26];</div>
 255 <div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span> </div>
 256 <div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    _REG_(M0PLUS_MPU_TYPE_OFFSET) <span class="comment">// M0PLUS_MPU_TYPE</span></div>
 257 <div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span>    <span class="comment">// MPU Type Register</span></div>
 258 <div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span>    <span class="comment">// 0x00ff0000 [23:16] IREGION      (0x00) Instruction region</span></div>
 259 <div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    <span class="comment">// 0x0000ff00 [15:8]  DREGION      (0x08) Number of regions supported by the MPU</span></div>
 260 <div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// 0x00000001 [0]     SEPARATE     (0) Indicates support for separate instruction and data address maps</span></div>
 261 <div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    io_ro_32 mpu_type;</div>
 262 <div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span> </div>
 263 <div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    _REG_(M0PLUS_MPU_CTRL_OFFSET) <span class="comment">// M0PLUS_MPU_CTRL</span></div>
 264 <div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>    <span class="comment">// MPU Control Register</span></div>
 265 <div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span>    <span class="comment">// 0x00000004 [2]     PRIVDEFENA   (0) Controls whether the default memory map is enabled as a...</span></div>
 266 <div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span>    <span class="comment">// 0x00000002 [1]     HFNMIENA     (0) Controls the use of the MPU for HardFaults and NMIs</span></div>
 267 <div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) Enables the MPU</span></div>
 268 <div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    io_rw_32 mpu_ctrl;</div>
 269 <div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span> </div>
 270 <div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>    _REG_(M0PLUS_MPU_RNR_OFFSET) <span class="comment">// M0PLUS_MPU_RNR</span></div>
 271 <div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>    <span class="comment">// MPU Region Number Register</span></div>
 272 <div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span>    <span class="comment">// 0x0000000f [3:0]   REGION       (0x0) Indicates the MPU region referenced by the MPU_RBAR and...</span></div>
 273 <div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span>    io_rw_32 mpu_rnr;</div>
 274 <div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span> </div>
 275 <div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span>    _REG_(M0PLUS_MPU_RBAR_OFFSET) <span class="comment">// M0PLUS_MPU_RBAR</span></div>
 276 <div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span>    <span class="comment">// MPU Region Base Address Register</span></div>
 277 <div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span>    <span class="comment">// 0xffffff00 [31:8]  ADDR         (0x000000) Base address of the region</span></div>
 278 <div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>    <span class="comment">// 0x00000010 [4]     VALID        (0) On writes, indicates whether the write must update the...</span></div>
 279 <div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span>    <span class="comment">// 0x0000000f [3:0]   REGION       (0x0) On writes, specifies the number of the region whose base...</span></div>
 280 <div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span>    io_rw_32 mpu_rbar;</div>
 281 <div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span> </div>
 282 <div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span>    _REG_(M0PLUS_MPU_RASR_OFFSET) <span class="comment">// M0PLUS_MPU_RASR</span></div>
 283 <div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span>    <span class="comment">// MPU Region Attribute and Size Register</span></div>
 284 <div class="line"><a id="l00186" name="l00186"></a><span class="lineno">  186</span>    <span class="comment">// 0xffff0000 [31:16] ATTRS        (0x0000) The MPU Region Attribute field</span></div>
 285 <div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span>    <span class="comment">// 0x0000ff00 [15:8]  SRD          (0x00) Subregion Disable</span></div>
 286 <div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span>    <span class="comment">// 0x0000003e [5:1]   SIZE         (0x00) Indicates the region size</span></div>
 287 <div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) Enables the region</span></div>
 288 <div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span>    io_rw_32 mpu_rasr;</div>
 289 <div class="line"><a id="l00191" name="l00191"></a><span class="lineno">  191</span>} <a class="code hl_struct" href="structm0plus__hw__t.html">m0plus_hw_t</a>;</div>
 290 <div class="line"><a id="l00192" name="l00192"></a><span class="lineno">  192</span> </div>
 291 <div class="line"><a id="l00193" name="l00193"></a><span class="lineno">  193</span><span class="preprocessor">#define ppb_hw ((m0plus_hw_t *)PPB_BASE)</span></div>
 292 <div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structm0plus__hw__t.html">m0plus_hw_t</a>) == 0xeda4, <span class="stringliteral">&quot;&quot;</span>);</div>
 293 <div class="line"><a id="l00195" name="l00195"></a><span class="lineno">  195</span> </div>
 294 <div class="line"><a id="l00196" name="l00196"></a><span class="lineno">  196</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_M0PLUS_H</span></div>
 295 <div class="line"><a id="l00197" name="l00197"></a><span class="lineno">  197</span> </div>
 296 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 297 <div class="ttc" id="astructm0plus__hw__t_html"><div class="ttname"><a href="structm0plus__hw__t.html">m0plus_hw_t</a></div><div class="ttdef"><b>Definition:</b> m0plus.h:26</div></div>
 298 </div><!-- fragment --></div><!-- contents -->
 299 </div><!-- doc-content -->
 300
 301         <script src="main.js"></script>
 302 </body>
 303 </html>