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 102 </div>
 103
 104 <div class="header">
 105   <div class="summary">
 106 <a href="#groups">Modules</a> &#124;
 107 <a href="#define-members">Macros</a> &#124;
 108 <a href="#typedef-members">Typedefs</a> &#124;
 109 <a href="#enum-members">Enumerations</a> &#124;
 110 <a href="#func-members">Functions</a>  </div>
 111   <div class="headertitle"><div class="title">hardware_dma<div class="ingroups"><a class="el" href="group__hardware.html">Hardware APIs</a></div></div></div>
 112 </div><!--header-->
 113 <div class="contents">
 114
 115 <p>DMA Controller API.
 116 <a href="#details">More...</a></p>
 117 <table class="memberdecls">
 118 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="groups" name="groups"></a>
 119 Modules</h2></td></tr>
 120 <tr class="memitem:group__channel__config"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__channel__config.html">channel_config</a></td></tr>
 121 <tr class="memdesc:group__channel__config"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA channel configuration. <br /></td></tr>
 122 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 123 </table><table class="memberdecls">
 124 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 125 Macros</h2></td></tr>
 126 <tr class="memitem:ga6c72cc3aafb409371f60fefd0463e289"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga6c72cc3aafb409371f60fefd0463e289">DMA_IRQ_NUM</a>(irq_index)</td></tr>
 127 <tr class="memdesc:ga6c72cc3aafb409371f60fefd0463e289"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the <a class="el" href="group__hardware__irq.html#gaf30862f51b5994ffd5863176a185d137">irq_num_t</a> for the nth DMA interrupt.  <a href="group__hardware__dma.html#ga6c72cc3aafb409371f60fefd0463e289">More...</a><br /></td></tr>
 128 <tr class="separator:ga6c72cc3aafb409371f60fefd0463e289"><td class="memSeparator" colspan="2">&#160;</td></tr>
 129 </table><table class="memberdecls">
 130 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="typedef-members" name="typedef-members"></a>
 131 Typedefs</h2></td></tr>
 132 <tr class="memitem:gadedf0e3a016a52299183d4d54d9e71e9"><td class="memItemLeft" align="right" valign="top"><a id="gadedf0e3a016a52299183d4d54d9e71e9" name="gadedf0e3a016a52299183d4d54d9e71e9"></a>
 133 typedef enum <a class="el" href="group__hardware__dma.html#ga6f0a19defc495cfa6078364122266014">dreq_num_rp2350</a>&#160;</td><td class="memItemRight" valign="bottom"><b>dreq_num_t</b></td></tr>
 134 <tr class="memdesc:gadedf0e3a016a52299183d4d54d9e71e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">DREQ numbers for DMA pacing on RP2350 (used as typedef <a class="el" href="group__hardware__dma.html#ga8def0ea481095c94f3a0dd0b4fed999e">dreq_num_t</a>) <br /></td></tr>
 135 <tr class="separator:gadedf0e3a016a52299183d4d54d9e71e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
 136 <tr class="memitem:ga8def0ea481095c94f3a0dd0b4fed999e"><td class="memItemLeft" align="right" valign="top"><a id="ga8def0ea481095c94f3a0dd0b4fed999e" name="ga8def0ea481095c94f3a0dd0b4fed999e"></a>
 137 typedef enum <a class="el" href="group__hardware__dma.html#ga864c3313155ab20116b62a64bf78df6d">dreq_num_rp2040</a>&#160;</td><td class="memItemRight" valign="bottom"><b>dreq_num_t</b></td></tr>
 138 <tr class="memdesc:ga8def0ea481095c94f3a0dd0b4fed999e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DREQ numbers for DMA pacing on RP2040 (used as typedef <a class="el" href="group__hardware__dma.html#ga8def0ea481095c94f3a0dd0b4fed999e">dreq_num_t</a>) <br /></td></tr>
 139 <tr class="separator:ga8def0ea481095c94f3a0dd0b4fed999e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 140 </table><table class="memberdecls">
 141 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a>
 142 Enumerations</h2></td></tr>
 143 <tr class="memitem:ga6f0a19defc495cfa6078364122266014"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga6f0a19defc495cfa6078364122266014">dreq_num_rp2350</a> { <br />
 144 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ad7529b7e45af2d7eab4b740ff15b49d8">DREQ_PIO0_TX0</a> = 0
 145 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ac5fedec084064e1d9ff9c6a382c1ccf8">DREQ_PIO0_TX1</a> = 1
 146 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014aa2e360dbf123d634d08e5fae27aa29e5">DREQ_PIO0_TX2</a> = 2
 147 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a156b1b999c6b2dd877545c8c79060a30">DREQ_PIO0_TX3</a> = 3
 148 , <br />
 149 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ac4bc12d74b758a7b39c1977c401e2fe1">DREQ_PIO0_RX0</a> = 4
 150 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a19b55b49bb618eed839edccba14c0d8f">DREQ_PIO0_RX1</a> = 5
 151 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a967d6b5eb2d3e06113b2b1606ef2af2c">DREQ_PIO0_RX2</a> = 6
 152 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a10f8705467782c859f05f82aa3c3c9f5">DREQ_PIO0_RX3</a> = 7
 153 , <br />
 154 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a3c22f2c9eb4a49654bba70dbc99bc893">DREQ_PIO1_TX0</a> = 8
 155 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a37f1bb39c3aa38a753df88e7e6c57feb">DREQ_PIO1_TX1</a> = 9
 156 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a13d7cb74708595298d788ba0ce25f6a0">DREQ_PIO1_TX2</a> = 10
 157 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014aaa5859ea1daaf5f0760fb4dea23116c3">DREQ_PIO1_TX3</a> = 11
 158 , <br />
 159 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a833bfa99e8b74de9bfc1872958a742e3">DREQ_PIO1_RX0</a> = 12
 160 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a8da9c5655eb51f2fb8a33b16827796a9">DREQ_PIO1_RX1</a> = 13
 161 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a0198dfe2da7237817e780a483144df8f">DREQ_PIO1_RX2</a> = 14
 162 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ab093d84a1df12a37ab6e9d62ee1f6d57">DREQ_PIO1_RX3</a> = 15
 163 , <br />
 164 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a6a3e73df9d0e562b41b571e272100302">DREQ_PIO2_TX0</a> = 16
 165 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a37c21bac317747dda953dca55954db16">DREQ_PIO2_TX1</a> = 17
 166 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014abadc20c78c83d2db4fcf3980f1d5b87f">DREQ_PIO2_TX2</a> = 18
 167 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014aa94c2b7f002c28a6050dda127aeaf3b1">DREQ_PIO2_TX3</a> = 19
 168 , <br />
 169 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a8bb28cdeea9248c04665464cabc6b1e6">DREQ_PIO2_RX0</a> = 20
 170 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a58a5eb511f85599b5e2b93cee7537b18">DREQ_PIO2_RX1</a> = 21
 171 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a9f4f2e7b3cf525ff519db02b0047bf87">DREQ_PIO2_RX2</a> = 22
 172 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ae7c631f739c8fb2e161c88911376ab26">DREQ_PIO2_RX3</a> = 23
 173 , <br />
 174 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a4b8b13f940414660401a7b334d85b64b">DREQ_SPI0_TX</a> = 24
 175 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a46641088908dd355dc82971e7c7fbd35">DREQ_SPI0_RX</a> = 25
 176 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a01d244742e157d2d2fb8e55b5fd6d81b">DREQ_SPI1_TX</a> = 26
 177 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a04665a3e6a5c58a6cbf2d0fe1503cf00">DREQ_SPI1_RX</a> = 27
 178 , <br />
 179 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a80ecb62e37f0c5af2780b93d4995326d">DREQ_UART0_TX</a> = 28
 180 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a4812587fa3aa4cfd7ea0d91e20246b95">DREQ_UART0_RX</a> = 29
 181 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014aa64110e7f89692b9c789275b4d8b04c0">DREQ_UART1_TX</a> = 30
 182 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ae5c7e2a566983a1148113e2987e059d5">DREQ_UART1_RX</a> = 31
 183 , <br />
 184 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a2a861c9dcce9e158ace7bc5d547ebde1">DREQ_PWM_WRAP0</a> = 32
 185 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a1504bdb2bd8aaa535903ea11aa2c2994">DREQ_PWM_WRAP1</a> = 33
 186 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014acb766e3b38daca5c8cd35459d835d7a2">DREQ_PWM_WRAP2</a> = 34
 187 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a017ebaacb45d90c4f20db2d5edded874">DREQ_PWM_WRAP3</a> = 35
 188 , <br />
 189 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a5fdd41bb900549d6ff26772cc9fd507a">DREQ_PWM_WRAP4</a> = 36
 190 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014aced239695d7bf65c41827e1eb6cbc04a">DREQ_PWM_WRAP5</a> = 37
 191 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014add0e022489d6ad4f835a97c6e354c15b">DREQ_PWM_WRAP6</a> = 38
 192 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014adafe5a7f2f401a496e842c7a2c95dac5">DREQ_PWM_WRAP7</a> = 39
 193 , <br />
 194 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a4ab337ff0746f2d9d432020658a478af">DREQ_PWM_WRAP8</a> = 40
 195 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a8d7bd836d3ba015fc800e227b6408f73">DREQ_PWM_WRAP9</a> = 41
 196 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ad17feaa0e6a99ccf14b5d7285ab363d1">DREQ_PWM_WRAP10</a> = 42
 197 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a14ba987e523bd38f813f93322d053a4c">DREQ_PWM_WRAP11</a> = 43
 198 , <br />
 199 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ab51c1095a1fec8ad39050cf49fd01835">DREQ_I2C0_TX</a> = 44
 200 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a675d15a4afa861045235a441d46d0580">DREQ_I2C0_RX</a> = 45
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 202 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a0b5156eb2381872ddc1837d83de16b8b">DREQ_I2C1_RX</a> = 47
 203 , <br />
 204 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a5f3aedb5ef1de25b99afcde8742b4590">DREQ_ADC</a> = 48
 205 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014aedbcc51f819f4c85c3ab8f51b654ebdc">DREQ_XIP_STREAM</a> = 49
 206 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a79533c8a78e8f62f1f564954a755e02a">DREQ_XIP_QMITX</a> = 50
 207 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a35519b1f622ee38560ffd2dfa1571c9b">DREQ_XIP_QMIRX</a> = 51
 208 , <br />
 209 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a71865f5a1fc034131dfb351d2c830c03">DREQ_HSTX</a> = 52
 210 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a1ef0656e59fedc445052acc548cce490">DREQ_CORESIGHT</a> = 53
 211 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a7a5f3a4ca267d2cd53c43779fb5494ba">DREQ_SHA256</a> = 54
 212 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a49bb6d90479edbff257068afd1a5bfe1">DREQ_DMA_TIMER0</a> = 59
 213 , <br />
 214 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a11c9291490c2ddf45df69f45a2f83dcf">DREQ_DMA_TIMER1</a> = 60
 215 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014abb60a9d9038192f9db081b51b9c23f65">DREQ_DMA_TIMER2</a> = 61
 216 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014a86d08425822a129c3eaa1479e920c67c">DREQ_DMA_TIMER3</a> = 62
 217 , <a class="el" href="group__hardware__dma.html#gga6f0a19defc495cfa6078364122266014ae683f0bb3ee8b854fe4cea850cf9d4c8">DREQ_FORCE</a> = 63
 218 , <br />
 219 &#160;&#160;<b>DREQ_COUNT</b>
 220 <br />
 221  }</td></tr>
 222 <tr class="memdesc:ga6f0a19defc495cfa6078364122266014"><td class="mdescLeft">&#160;</td><td class="mdescRight">DREQ numbers for DMA pacing on RP2350 (used as typedef <a class="el" href="group__hardware__dma.html#ga8def0ea481095c94f3a0dd0b4fed999e">dreq_num_t</a>)  <a href="group__hardware__dma.html#ga6f0a19defc495cfa6078364122266014">More...</a><br /></td></tr>
 223 <tr class="separator:ga6f0a19defc495cfa6078364122266014"><td class="memSeparator" colspan="2">&#160;</td></tr>
 224 <tr class="memitem:ga864c3313155ab20116b62a64bf78df6d"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga864c3313155ab20116b62a64bf78df6d">dreq_num_rp2040</a> { <br />
 225 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dad7529b7e45af2d7eab4b740ff15b49d8">DREQ_PIO0_TX0</a> = 0
 226 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dac5fedec084064e1d9ff9c6a382c1ccf8">DREQ_PIO0_TX1</a> = 1
 227 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6daa2e360dbf123d634d08e5fae27aa29e5">DREQ_PIO0_TX2</a> = 2
 228 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da156b1b999c6b2dd877545c8c79060a30">DREQ_PIO0_TX3</a> = 3
 229 , <br />
 230 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dac4bc12d74b758a7b39c1977c401e2fe1">DREQ_PIO0_RX0</a> = 4
 231 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da19b55b49bb618eed839edccba14c0d8f">DREQ_PIO0_RX1</a> = 5
 232 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da967d6b5eb2d3e06113b2b1606ef2af2c">DREQ_PIO0_RX2</a> = 6
 233 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da10f8705467782c859f05f82aa3c3c9f5">DREQ_PIO0_RX3</a> = 7
 234 , <br />
 235 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da3c22f2c9eb4a49654bba70dbc99bc893">DREQ_PIO1_TX0</a> = 8
 236 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da37f1bb39c3aa38a753df88e7e6c57feb">DREQ_PIO1_TX1</a> = 9
 237 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da13d7cb74708595298d788ba0ce25f6a0">DREQ_PIO1_TX2</a> = 10
 238 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6daaa5859ea1daaf5f0760fb4dea23116c3">DREQ_PIO1_TX3</a> = 11
 239 , <br />
 240 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da833bfa99e8b74de9bfc1872958a742e3">DREQ_PIO1_RX0</a> = 12
 241 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da8da9c5655eb51f2fb8a33b16827796a9">DREQ_PIO1_RX1</a> = 13
 242 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da0198dfe2da7237817e780a483144df8f">DREQ_PIO1_RX2</a> = 14
 243 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dab093d84a1df12a37ab6e9d62ee1f6d57">DREQ_PIO1_RX3</a> = 15
 244 , <br />
 245 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da4b8b13f940414660401a7b334d85b64b">DREQ_SPI0_TX</a> = 16
 246 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da46641088908dd355dc82971e7c7fbd35">DREQ_SPI0_RX</a> = 17
 247 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da01d244742e157d2d2fb8e55b5fd6d81b">DREQ_SPI1_TX</a> = 18
 248 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da04665a3e6a5c58a6cbf2d0fe1503cf00">DREQ_SPI1_RX</a> = 19
 249 , <br />
 250 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da80ecb62e37f0c5af2780b93d4995326d">DREQ_UART0_TX</a> = 20
 251 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da4812587fa3aa4cfd7ea0d91e20246b95">DREQ_UART0_RX</a> = 21
 252 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6daa64110e7f89692b9c789275b4d8b04c0">DREQ_UART1_TX</a> = 22
 253 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dae5c7e2a566983a1148113e2987e059d5">DREQ_UART1_RX</a> = 23
 254 , <br />
 255 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da2a861c9dcce9e158ace7bc5d547ebde1">DREQ_PWM_WRAP0</a> = 24
 256 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da1504bdb2bd8aaa535903ea11aa2c2994">DREQ_PWM_WRAP1</a> = 25
 257 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dacb766e3b38daca5c8cd35459d835d7a2">DREQ_PWM_WRAP2</a> = 26
 258 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da017ebaacb45d90c4f20db2d5edded874">DREQ_PWM_WRAP3</a> = 27
 259 , <br />
 260 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da5fdd41bb900549d6ff26772cc9fd507a">DREQ_PWM_WRAP4</a> = 28
 261 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6daced239695d7bf65c41827e1eb6cbc04a">DREQ_PWM_WRAP5</a> = 29
 262 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dadd0e022489d6ad4f835a97c6e354c15b">DREQ_PWM_WRAP6</a> = 30
 263 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dadafe5a7f2f401a496e842c7a2c95dac5">DREQ_PWM_WRAP7</a> = 31
 264 , <br />
 265 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dab51c1095a1fec8ad39050cf49fd01835">DREQ_I2C0_TX</a> = 32
 266 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da675d15a4afa861045235a441d46d0580">DREQ_I2C0_RX</a> = 33
 267 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da74c786868da56dbb18b7da2c7748568f">DREQ_I2C1_TX</a> = 34
 268 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da0b5156eb2381872ddc1837d83de16b8b">DREQ_I2C1_RX</a> = 35
 269 , <br />
 270 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da5f3aedb5ef1de25b99afcde8742b4590">DREQ_ADC</a> = 36
 271 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6daedbcc51f819f4c85c3ab8f51b654ebdc">DREQ_XIP_STREAM</a> = 37
 272 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dabaf536bfba84db157116952ae4a5d466">DREQ_XIP_SSITX</a> = 38
 273 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da74f7500adc3af744bfe564b1c90aba0a">DREQ_XIP_SSIRX</a> = 39
 274 , <br />
 275 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da49bb6d90479edbff257068afd1a5bfe1">DREQ_DMA_TIMER0</a> = 59
 276 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da11c9291490c2ddf45df69f45a2f83dcf">DREQ_DMA_TIMER1</a> = 60
 277 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dabb60a9d9038192f9db081b51b9c23f65">DREQ_DMA_TIMER2</a> = 61
 278 , <a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6da86d08425822a129c3eaa1479e920c67c">DREQ_DMA_TIMER3</a> = 62
 279 , <br />
 280 &#160;&#160;<a class="el" href="group__hardware__dma.html#gga864c3313155ab20116b62a64bf78df6dae683f0bb3ee8b854fe4cea850cf9d4c8">DREQ_FORCE</a> = 63
 281 , <b>DREQ_COUNT</b>
 282 <br />
 283  }</td></tr>
 284 <tr class="memdesc:ga864c3313155ab20116b62a64bf78df6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DREQ numbers for DMA pacing on RP2040 (used as typedef <a class="el" href="group__hardware__dma.html#ga8def0ea481095c94f3a0dd0b4fed999e">dreq_num_t</a>)  <a href="group__hardware__dma.html#ga864c3313155ab20116b62a64bf78df6d">More...</a><br /></td></tr>
 285 <tr class="separator:ga864c3313155ab20116b62a64bf78df6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
 286 <tr class="memitem:gaccecdff367b06a019373e9a55d4f3e01"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaccecdff367b06a019373e9a55d4f3e01">dma_channel_transfer_size</a> { <a class="el" href="group__hardware__dma.html#ggaccecdff367b06a019373e9a55d4f3e01abd7d246406a2ebe4dd49780db176dc3c">DMA_SIZE_8</a> = 0
 287 , <a class="el" href="group__hardware__dma.html#ggaccecdff367b06a019373e9a55d4f3e01a2e343022ac046b6b67bb99eebc833cfc">DMA_SIZE_16</a> = 1
 288 , <a class="el" href="group__hardware__dma.html#ggaccecdff367b06a019373e9a55d4f3e01abf1030013f4ad74b45d25cd9a07b6296">DMA_SIZE_32</a> = 2
 289  }</td></tr>
 290 <tr class="memdesc:gaccecdff367b06a019373e9a55d4f3e01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enumeration of available DMA channel transfer sizes.  <a href="group__hardware__dma.html#gaccecdff367b06a019373e9a55d4f3e01">More...</a><br /></td></tr>
 291 <tr class="separator:gaccecdff367b06a019373e9a55d4f3e01"><td class="memSeparator" colspan="2">&#160;</td></tr>
 292 </table><table class="memberdecls">
 293 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
 294 Functions</h2></td></tr>
 295 <tr class="memitem:gae1b3c916746b3d2052f21b7dda34aab9"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gae1b3c916746b3d2052f21b7dda34aab9">dma_channel_claim</a> (uint channel)</td></tr>
 296 <tr class="memdesc:gae1b3c916746b3d2052f21b7dda34aab9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark a dma channel as used.  <a href="group__hardware__dma.html#gae1b3c916746b3d2052f21b7dda34aab9">More...</a><br /></td></tr>
 297 <tr class="separator:gae1b3c916746b3d2052f21b7dda34aab9"><td class="memSeparator" colspan="2">&#160;</td></tr>
 298 <tr class="memitem:gaa430bc53dc2b36d727ad976f6348c8b3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaa430bc53dc2b36d727ad976f6348c8b3">dma_claim_mask</a> (uint32_t channel_mask)</td></tr>
 299 <tr class="memdesc:gaa430bc53dc2b36d727ad976f6348c8b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark multiple dma channels as used.  <a href="group__hardware__dma.html#gaa430bc53dc2b36d727ad976f6348c8b3">More...</a><br /></td></tr>
 300 <tr class="separator:gaa430bc53dc2b36d727ad976f6348c8b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
 301 <tr class="memitem:gac50200739b88a2fd52316f4150533035"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gac50200739b88a2fd52316f4150533035">dma_channel_unclaim</a> (uint channel)</td></tr>
 302 <tr class="memdesc:gac50200739b88a2fd52316f4150533035"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark a dma channel as no longer used.  <a href="group__hardware__dma.html#gac50200739b88a2fd52316f4150533035">More...</a><br /></td></tr>
 303 <tr class="separator:gac50200739b88a2fd52316f4150533035"><td class="memSeparator" colspan="2">&#160;</td></tr>
 304 <tr class="memitem:ga0211681c906ebe4971d0cded8e98f8b5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga0211681c906ebe4971d0cded8e98f8b5">dma_unclaim_mask</a> (uint32_t channel_mask)</td></tr>
 305 <tr class="memdesc:ga0211681c906ebe4971d0cded8e98f8b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark multiple dma channels as no longer used.  <a href="group__hardware__dma.html#ga0211681c906ebe4971d0cded8e98f8b5">More...</a><br /></td></tr>
 306 <tr class="separator:ga0211681c906ebe4971d0cded8e98f8b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
 307 <tr class="memitem:ga4b0a6680795b9c9ed787362a8a057206"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga4b0a6680795b9c9ed787362a8a057206">dma_claim_unused_channel</a> (bool required)</td></tr>
 308 <tr class="memdesc:ga4b0a6680795b9c9ed787362a8a057206"><td class="mdescLeft">&#160;</td><td class="mdescRight">Claim a free dma channel.  <a href="group__hardware__dma.html#ga4b0a6680795b9c9ed787362a8a057206">More...</a><br /></td></tr>
 309 <tr class="separator:ga4b0a6680795b9c9ed787362a8a057206"><td class="memSeparator" colspan="2">&#160;</td></tr>
 310 <tr class="memitem:ga9aadb81f53b979bde1c1a81164d1eff2"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga9aadb81f53b979bde1c1a81164d1eff2">dma_channel_is_claimed</a> (uint channel)</td></tr>
 311 <tr class="memdesc:ga9aadb81f53b979bde1c1a81164d1eff2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a dma channel is claimed.  <a href="group__hardware__dma.html#ga9aadb81f53b979bde1c1a81164d1eff2">More...</a><br /></td></tr>
 312 <tr class="separator:ga9aadb81f53b979bde1c1a81164d1eff2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 313 <tr class="memitem:ga7449b659efb178a408f42f7f8f7b02f9"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga7449b659efb178a408f42f7f8f7b02f9">dma_channel_set_config</a> (uint channel, const <a class="el" href="structdma__channel__config.html">dma_channel_config</a> *config, bool trigger)</td></tr>
 314 <tr class="memdesc:ga7449b659efb178a408f42f7f8f7b02f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set a channel configuration.  <a href="group__hardware__dma.html#ga7449b659efb178a408f42f7f8f7b02f9">More...</a><br /></td></tr>
 315 <tr class="separator:ga7449b659efb178a408f42f7f8f7b02f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
 316 <tr class="memitem:gabf6f6ffe56fa42dcb105032f110589ae"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gabf6f6ffe56fa42dcb105032f110589ae">dma_channel_set_read_addr</a> (uint channel, const volatile void *read_addr, bool trigger)</td></tr>
 317 <tr class="memdesc:gabf6f6ffe56fa42dcb105032f110589ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the DMA initial read address.  <a href="group__hardware__dma.html#gabf6f6ffe56fa42dcb105032f110589ae">More...</a><br /></td></tr>
 318 <tr class="separator:gabf6f6ffe56fa42dcb105032f110589ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
 319 <tr class="memitem:gaf0156609fe51c07d07118b2aeb4e9ae6"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaf0156609fe51c07d07118b2aeb4e9ae6">dma_channel_set_write_addr</a> (uint channel, volatile void *write_addr, bool trigger)</td></tr>
 320 <tr class="memdesc:gaf0156609fe51c07d07118b2aeb4e9ae6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the DMA initial write address.  <a href="group__hardware__dma.html#gaf0156609fe51c07d07118b2aeb4e9ae6">More...</a><br /></td></tr>
 321 <tr class="separator:gaf0156609fe51c07d07118b2aeb4e9ae6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 322 <tr class="memitem:ga16c0e08eda636f13053d8c8b0f81e821"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga16c0e08eda636f13053d8c8b0f81e821">dma_channel_set_trans_count</a> (uint channel, uint32_t trans_count, bool trigger)</td></tr>
 323 <tr class="memdesc:ga16c0e08eda636f13053d8c8b0f81e821"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the number of bus transfers the channel will do.  <a href="group__hardware__dma.html#ga16c0e08eda636f13053d8c8b0f81e821">More...</a><br /></td></tr>
 324 <tr class="separator:ga16c0e08eda636f13053d8c8b0f81e821"><td class="memSeparator" colspan="2">&#160;</td></tr>
 325 <tr class="memitem:ga971d077ac39b2d7f7c6b45e2ddc5d190"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga971d077ac39b2d7f7c6b45e2ddc5d190">dma_channel_configure</a> (uint channel, const <a class="el" href="structdma__channel__config.html">dma_channel_config</a> *config, volatile void *write_addr, const volatile void *read_addr, uint transfer_count, bool trigger)</td></tr>
 326 <tr class="memdesc:ga971d077ac39b2d7f7c6b45e2ddc5d190"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure all DMA parameters and optionally start transfer.  <a href="group__hardware__dma.html#ga971d077ac39b2d7f7c6b45e2ddc5d190">More...</a><br /></td></tr>
 327 <tr class="separator:ga971d077ac39b2d7f7c6b45e2ddc5d190"><td class="memSeparator" colspan="2">&#160;</td></tr>
 328 <tr class="memitem:gabf64c461a405a8114591105d9dc53575"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gabf64c461a405a8114591105d9dc53575">dma_channel_transfer_from_buffer_now</a> (uint channel, const volatile void *read_addr, uint32_t transfer_count)</td></tr>
 329 <tr class="memdesc:gabf64c461a405a8114591105d9dc53575"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start a DMA transfer from a buffer immediately.  <a href="group__hardware__dma.html#gabf64c461a405a8114591105d9dc53575">More...</a><br /></td></tr>
 330 <tr class="separator:gabf64c461a405a8114591105d9dc53575"><td class="memSeparator" colspan="2">&#160;</td></tr>
 331 <tr class="memitem:ga9110135d8161fc268d87dfb040d0f854"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga9110135d8161fc268d87dfb040d0f854">dma_channel_transfer_to_buffer_now</a> (uint channel, volatile void *write_addr, uint32_t transfer_count)</td></tr>
 332 <tr class="memdesc:ga9110135d8161fc268d87dfb040d0f854"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start a DMA transfer to a buffer immediately.  <a href="group__hardware__dma.html#ga9110135d8161fc268d87dfb040d0f854">More...</a><br /></td></tr>
 333 <tr class="separator:ga9110135d8161fc268d87dfb040d0f854"><td class="memSeparator" colspan="2">&#160;</td></tr>
 334 <tr class="memitem:ga6407f7763b533c98e23f65e35c5e48ee"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga6407f7763b533c98e23f65e35c5e48ee">dma_start_channel_mask</a> (uint32_t chan_mask)</td></tr>
 335 <tr class="memdesc:ga6407f7763b533c98e23f65e35c5e48ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start one or more channels simultaneously.  <a href="group__hardware__dma.html#ga6407f7763b533c98e23f65e35c5e48ee">More...</a><br /></td></tr>
 336 <tr class="separator:ga6407f7763b533c98e23f65e35c5e48ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
 337 <tr class="memitem:ga355720e02713c7324b540efc6f632366"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga355720e02713c7324b540efc6f632366">dma_channel_start</a> (uint channel)</td></tr>
 338 <tr class="memdesc:ga355720e02713c7324b540efc6f632366"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start a single DMA channel.  <a href="group__hardware__dma.html#ga355720e02713c7324b540efc6f632366">More...</a><br /></td></tr>
 339 <tr class="separator:ga355720e02713c7324b540efc6f632366"><td class="memSeparator" colspan="2">&#160;</td></tr>
 340 <tr class="memitem:ga735e7c6c136c078689ead70790f4edb2"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga735e7c6c136c078689ead70790f4edb2">dma_channel_abort</a> (uint channel)</td></tr>
 341 <tr class="memdesc:ga735e7c6c136c078689ead70790f4edb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop a DMA transfer.  <a href="group__hardware__dma.html#ga735e7c6c136c078689ead70790f4edb2">More...</a><br /></td></tr>
 342 <tr class="separator:ga735e7c6c136c078689ead70790f4edb2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 343 <tr class="memitem:gaf60011d46676c87b7139f37188eaa4b9"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaf60011d46676c87b7139f37188eaa4b9">dma_channel_set_irq0_enabled</a> (uint channel, bool enabled)</td></tr>
 344 <tr class="memdesc:gaf60011d46676c87b7139f37188eaa4b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable single DMA channel's interrupt via DMA_IRQ_0.  <a href="group__hardware__dma.html#gaf60011d46676c87b7139f37188eaa4b9">More...</a><br /></td></tr>
 345 <tr class="separator:gaf60011d46676c87b7139f37188eaa4b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
 346 <tr class="memitem:gad5c1ac22e0b4d9b831912fbb95460be4"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gad5c1ac22e0b4d9b831912fbb95460be4">dma_set_irq0_channel_mask_enabled</a> (uint32_t channel_mask, bool enabled)</td></tr>
 347 <tr class="memdesc:gad5c1ac22e0b4d9b831912fbb95460be4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable multiple DMA channels' interrupts via DMA_IRQ_0.  <a href="group__hardware__dma.html#gad5c1ac22e0b4d9b831912fbb95460be4">More...</a><br /></td></tr>
 348 <tr class="separator:gad5c1ac22e0b4d9b831912fbb95460be4"><td class="memSeparator" colspan="2">&#160;</td></tr>
 349 <tr class="memitem:ga4f9415c8f77ff0bacedf5a138a88d76f"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga4f9415c8f77ff0bacedf5a138a88d76f">dma_channel_set_irq1_enabled</a> (uint channel, bool enabled)</td></tr>
 350 <tr class="memdesc:ga4f9415c8f77ff0bacedf5a138a88d76f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable single DMA channel's interrupt via DMA_IRQ_1.  <a href="group__hardware__dma.html#ga4f9415c8f77ff0bacedf5a138a88d76f">More...</a><br /></td></tr>
 351 <tr class="separator:ga4f9415c8f77ff0bacedf5a138a88d76f"><td class="memSeparator" colspan="2">&#160;</td></tr>
 352 <tr class="memitem:gaaa20edc55a2cc4977d24bdb487a22aa5"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaaa20edc55a2cc4977d24bdb487a22aa5">dma_set_irq1_channel_mask_enabled</a> (uint32_t channel_mask, bool enabled)</td></tr>
 353 <tr class="memdesc:gaaa20edc55a2cc4977d24bdb487a22aa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable multiple DMA channels' interrupts via DMA_IRQ_1.  <a href="group__hardware__dma.html#gaaa20edc55a2cc4977d24bdb487a22aa5">More...</a><br /></td></tr>
 354 <tr class="separator:gaaa20edc55a2cc4977d24bdb487a22aa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
 355 <tr class="memitem:ga6fefe19fa5539580315de923e42131d3"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga6fefe19fa5539580315de923e42131d3">dma_irqn_set_channel_enabled</a> (uint irq_index, uint channel, bool enabled)</td></tr>
 356 <tr class="memdesc:ga6fefe19fa5539580315de923e42131d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1.  <a href="group__hardware__dma.html#ga6fefe19fa5539580315de923e42131d3">More...</a><br /></td></tr>
 357 <tr class="separator:ga6fefe19fa5539580315de923e42131d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
 358 <tr class="memitem:ga720f2335e93b0e53e28959566ca18f3e"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga720f2335e93b0e53e28959566ca18f3e">dma_irqn_set_channel_mask_enabled</a> (uint irq_index, uint32_t channel_mask, bool enabled)</td></tr>
 359 <tr class="memdesc:ga720f2335e93b0e53e28959566ca18f3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1.  <a href="group__hardware__dma.html#ga720f2335e93b0e53e28959566ca18f3e">More...</a><br /></td></tr>
 360 <tr class="separator:ga720f2335e93b0e53e28959566ca18f3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 361 <tr class="memitem:gaa86e892c47b054d3c22fa39c001c7c23"><td class="memItemLeft" align="right" valign="top">static bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaa86e892c47b054d3c22fa39c001c7c23">dma_channel_get_irq0_status</a> (uint channel)</td></tr>
 362 <tr class="memdesc:gaa86e892c47b054d3c22fa39c001c7c23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a particular channel is a cause of DMA_IRQ_0.  <a href="group__hardware__dma.html#gaa86e892c47b054d3c22fa39c001c7c23">More...</a><br /></td></tr>
 363 <tr class="separator:gaa86e892c47b054d3c22fa39c001c7c23"><td class="memSeparator" colspan="2">&#160;</td></tr>
 364 <tr class="memitem:gaf61d25264e49058d20fb607dc1c40981"><td class="memItemLeft" align="right" valign="top">static bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaf61d25264e49058d20fb607dc1c40981">dma_channel_get_irq1_status</a> (uint channel)</td></tr>
 365 <tr class="memdesc:gaf61d25264e49058d20fb607dc1c40981"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a particular channel is a cause of DMA_IRQ_1.  <a href="group__hardware__dma.html#gaf61d25264e49058d20fb607dc1c40981">More...</a><br /></td></tr>
 366 <tr class="separator:gaf61d25264e49058d20fb607dc1c40981"><td class="memSeparator" colspan="2">&#160;</td></tr>
 367 <tr class="memitem:ga43f1fe10d5eb241788f72ad11599fc11"><td class="memItemLeft" align="right" valign="top">static bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga43f1fe10d5eb241788f72ad11599fc11">dma_irqn_get_channel_status</a> (uint irq_index, uint channel)</td></tr>
 368 <tr class="memdesc:ga43f1fe10d5eb241788f72ad11599fc11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a particular channel is a cause of DMA_IRQ_N.  <a href="group__hardware__dma.html#ga43f1fe10d5eb241788f72ad11599fc11">More...</a><br /></td></tr>
 369 <tr class="separator:ga43f1fe10d5eb241788f72ad11599fc11"><td class="memSeparator" colspan="2">&#160;</td></tr>
 370 <tr class="memitem:gafefe50f20c44bcfa7f729829a5d494f4"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gafefe50f20c44bcfa7f729829a5d494f4">dma_channel_acknowledge_irq0</a> (uint channel)</td></tr>
 371 <tr class="memdesc:gafefe50f20c44bcfa7f729829a5d494f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0.  <a href="group__hardware__dma.html#gafefe50f20c44bcfa7f729829a5d494f4">More...</a><br /></td></tr>
 372 <tr class="separator:gafefe50f20c44bcfa7f729829a5d494f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
 373 <tr class="memitem:ga4d4b5d461ff09bb6e4e2a05df3b7c75c"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga4d4b5d461ff09bb6e4e2a05df3b7c75c">dma_channel_acknowledge_irq1</a> (uint channel)</td></tr>
 374 <tr class="memdesc:ga4d4b5d461ff09bb6e4e2a05df3b7c75c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1.  <a href="group__hardware__dma.html#ga4d4b5d461ff09bb6e4e2a05df3b7c75c">More...</a><br /></td></tr>
 375 <tr class="separator:ga4d4b5d461ff09bb6e4e2a05df3b7c75c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 376 <tr class="memitem:gad0e8e022fbe67b80c16912254526fada"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gad0e8e022fbe67b80c16912254526fada">dma_irqn_acknowledge_channel</a> (uint irq_index, uint channel)</td></tr>
 377 <tr class="memdesc:gad0e8e022fbe67b80c16912254526fada"><td class="mdescLeft">&#160;</td><td class="mdescRight">Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N.  <a href="group__hardware__dma.html#gad0e8e022fbe67b80c16912254526fada">More...</a><br /></td></tr>
 378 <tr class="separator:gad0e8e022fbe67b80c16912254526fada"><td class="memSeparator" colspan="2">&#160;</td></tr>
 379 <tr class="memitem:gafbb5020a529ed6d39a11da88a6f313f2"><td class="memItemLeft" align="right" valign="top">static bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gafbb5020a529ed6d39a11da88a6f313f2">dma_channel_is_busy</a> (uint channel)</td></tr>
 380 <tr class="memdesc:gafbb5020a529ed6d39a11da88a6f313f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check if DMA channel is busy.  <a href="group__hardware__dma.html#gafbb5020a529ed6d39a11da88a6f313f2">More...</a><br /></td></tr>
 381 <tr class="separator:gafbb5020a529ed6d39a11da88a6f313f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 382 <tr class="memitem:gab57c68850b8e6ed1623de75ad611db62"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gab57c68850b8e6ed1623de75ad611db62">dma_channel_wait_for_finish_blocking</a> (uint channel)</td></tr>
 383 <tr class="memdesc:gab57c68850b8e6ed1623de75ad611db62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait for a DMA channel transfer to complete.  <a href="group__hardware__dma.html#gab57c68850b8e6ed1623de75ad611db62">More...</a><br /></td></tr>
 384 <tr class="separator:gab57c68850b8e6ed1623de75ad611db62"><td class="memSeparator" colspan="2">&#160;</td></tr>
 385 <tr class="memitem:ga078c3c80d5637850ec64e8f5ad5ce0c2"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga078c3c80d5637850ec64e8f5ad5ce0c2">dma_sniffer_enable</a> (uint channel, uint mode, bool force_channel_enable)</td></tr>
 386 <tr class="memdesc:ga078c3c80d5637850ec64e8f5ad5ce0c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the DMA sniffing targeting the specified channel.  <a href="group__hardware__dma.html#ga078c3c80d5637850ec64e8f5ad5ce0c2">More...</a><br /></td></tr>
 387 <tr class="separator:ga078c3c80d5637850ec64e8f5ad5ce0c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 388 <tr class="memitem:gac3b250d97550527a584de9d3f770acea"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gac3b250d97550527a584de9d3f770acea">dma_sniffer_set_byte_swap_enabled</a> (bool swap)</td></tr>
 389 <tr class="memdesc:gac3b250d97550527a584de9d3f770acea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the Sniffer byte swap function.  <a href="group__hardware__dma.html#gac3b250d97550527a584de9d3f770acea">More...</a><br /></td></tr>
 390 <tr class="separator:gac3b250d97550527a584de9d3f770acea"><td class="memSeparator" colspan="2">&#160;</td></tr>
 391 <tr class="memitem:ga1366c938a8322aa1eb8e703b1f22d6af"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga1366c938a8322aa1eb8e703b1f22d6af">dma_sniffer_set_output_invert_enabled</a> (bool invert)</td></tr>
 392 <tr class="memdesc:ga1366c938a8322aa1eb8e703b1f22d6af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the Sniffer output invert function.  <a href="group__hardware__dma.html#ga1366c938a8322aa1eb8e703b1f22d6af">More...</a><br /></td></tr>
 393 <tr class="separator:ga1366c938a8322aa1eb8e703b1f22d6af"><td class="memSeparator" colspan="2">&#160;</td></tr>
 394 <tr class="memitem:gaa2c5775bdb86d63a4866b2f6f5b41143"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gaa2c5775bdb86d63a4866b2f6f5b41143">dma_sniffer_set_output_reverse_enabled</a> (bool reverse)</td></tr>
 395 <tr class="memdesc:gaa2c5775bdb86d63a4866b2f6f5b41143"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the Sniffer output bit reversal function.  <a href="group__hardware__dma.html#gaa2c5775bdb86d63a4866b2f6f5b41143">More...</a><br /></td></tr>
 396 <tr class="separator:gaa2c5775bdb86d63a4866b2f6f5b41143"><td class="memSeparator" colspan="2">&#160;</td></tr>
 397 <tr class="memitem:ga9c9bcbe60b4c6102cae3e616476c4735"><td class="memItemLeft" align="right" valign="top"><a id="ga9c9bcbe60b4c6102cae3e616476c4735" name="ga9c9bcbe60b4c6102cae3e616476c4735"></a>
 398 static void&#160;</td><td class="memItemRight" valign="bottom"><b>dma_sniffer_disable</b> (void)</td></tr>
 399 <tr class="memdesc:ga9c9bcbe60b4c6102cae3e616476c4735"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the DMA sniffer. <br /></td></tr>
 400 <tr class="separator:ga9c9bcbe60b4c6102cae3e616476c4735"><td class="memSeparator" colspan="2">&#160;</td></tr>
 401 <tr class="memitem:gacab1f8010c206dfc77b81cb16902a4e4"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#gacab1f8010c206dfc77b81cb16902a4e4">dma_sniffer_set_data_accumulator</a> (uint32_t seed_value)</td></tr>
 402 <tr class="memdesc:gacab1f8010c206dfc77b81cb16902a4e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the sniffer's data accumulator with initial value.  <a href="group__hardware__dma.html#gacab1f8010c206dfc77b81cb16902a4e4">More...</a><br /></td></tr>
 403 <tr class="separator:gacab1f8010c206dfc77b81cb16902a4e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
 404 <tr class="memitem:ga3527c2567c9253ca602b91d30ae49d1e"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga3527c2567c9253ca602b91d30ae49d1e">dma_sniffer_get_data_accumulator</a> (void)</td></tr>
 405 <tr class="memdesc:ga3527c2567c9253ca602b91d30ae49d1e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the sniffer's data accumulator value.  <a href="group__hardware__dma.html#ga3527c2567c9253ca602b91d30ae49d1e">More...</a><br /></td></tr>
 406 <tr class="separator:ga3527c2567c9253ca602b91d30ae49d1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 407 <tr class="memitem:ga08fc90c0064510e7a0a2cf8d1cd187bc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga08fc90c0064510e7a0a2cf8d1cd187bc">dma_timer_claim</a> (uint timer)</td></tr>
 408 <tr class="memdesc:ga08fc90c0064510e7a0a2cf8d1cd187bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark a dma timer as used.  <a href="group__hardware__dma.html#ga08fc90c0064510e7a0a2cf8d1cd187bc">More...</a><br /></td></tr>
 409 <tr class="separator:ga08fc90c0064510e7a0a2cf8d1cd187bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
 410 <tr class="memitem:ga890490576d8806b8933aad0e34d09c5e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga890490576d8806b8933aad0e34d09c5e">dma_timer_unclaim</a> (uint timer)</td></tr>
 411 <tr class="memdesc:ga890490576d8806b8933aad0e34d09c5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark a dma timer as no longer used.  <a href="group__hardware__dma.html#ga890490576d8806b8933aad0e34d09c5e">More...</a><br /></td></tr>
 412 <tr class="separator:ga890490576d8806b8933aad0e34d09c5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 413 <tr class="memitem:ga2f218b6acd97e09430afbb74172bd570"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga2f218b6acd97e09430afbb74172bd570">dma_claim_unused_timer</a> (bool required)</td></tr>
 414 <tr class="memdesc:ga2f218b6acd97e09430afbb74172bd570"><td class="mdescLeft">&#160;</td><td class="mdescRight">Claim a free dma timer.  <a href="group__hardware__dma.html#ga2f218b6acd97e09430afbb74172bd570">More...</a><br /></td></tr>
 415 <tr class="separator:ga2f218b6acd97e09430afbb74172bd570"><td class="memSeparator" colspan="2">&#160;</td></tr>
 416 <tr class="memitem:ga9b45bfe6985f8c0894d34876eedc3090"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga9b45bfe6985f8c0894d34876eedc3090">dma_timer_is_claimed</a> (uint timer)</td></tr>
 417 <tr class="memdesc:ga9b45bfe6985f8c0894d34876eedc3090"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a dma timer is claimed.  <a href="group__hardware__dma.html#ga9b45bfe6985f8c0894d34876eedc3090">More...</a><br /></td></tr>
 418 <tr class="separator:ga9b45bfe6985f8c0894d34876eedc3090"><td class="memSeparator" colspan="2">&#160;</td></tr>
 419 <tr class="memitem:ga58f9c3cb606759e4620c82583f833dc8"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga58f9c3cb606759e4620c82583f833dc8">dma_timer_set_fraction</a> (uint timer, uint16_t numerator, uint16_t denominator)</td></tr>
 420 <tr class="memdesc:ga58f9c3cb606759e4620c82583f833dc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the multiplier for the given DMA timer.  <a href="group__hardware__dma.html#ga58f9c3cb606759e4620c82583f833dc8">More...</a><br /></td></tr>
 421 <tr class="separator:ga58f9c3cb606759e4620c82583f833dc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
 422 <tr class="memitem:ga75ef6881795fd1760fe813f9e0a79223"><td class="memItemLeft" align="right" valign="top">static uint&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga75ef6881795fd1760fe813f9e0a79223">dma_get_timer_dreq</a> (uint timer_num)</td></tr>
 423 <tr class="memdesc:ga75ef6881795fd1760fe813f9e0a79223"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the DREQ number for a given DMA timer.  <a href="group__hardware__dma.html#ga75ef6881795fd1760fe813f9e0a79223">More...</a><br /></td></tr>
 424 <tr class="separator:ga75ef6881795fd1760fe813f9e0a79223"><td class="memSeparator" colspan="2">&#160;</td></tr>
 425 <tr class="memitem:ga5da1507764272564a75939e2cf38fa9a"><td class="memItemLeft" align="right" valign="top">static int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga5da1507764272564a75939e2cf38fa9a">dma_get_irq_num</a> (uint irq_index)</td></tr>
 426 <tr class="memdesc:ga5da1507764272564a75939e2cf38fa9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return DMA_IRQ_&lt;irqn&gt;  <a href="group__hardware__dma.html#ga5da1507764272564a75939e2cf38fa9a">More...</a><br /></td></tr>
 427 <tr class="separator:ga5da1507764272564a75939e2cf38fa9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
 428 <tr class="memitem:ga655130988c1045bdf711135698adf321"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__dma.html#ga655130988c1045bdf711135698adf321">dma_channel_cleanup</a> (uint channel)</td></tr>
 429 <tr class="memdesc:ga655130988c1045bdf711135698adf321"><td class="mdescLeft">&#160;</td><td class="mdescRight">Performs DMA channel cleanup after use.  <a href="group__hardware__dma.html#ga655130988c1045bdf711135698adf321">More...</a><br /></td></tr>
 430 <tr class="separator:ga655130988c1045bdf711135698adf321"><td class="memSeparator" colspan="2">&#160;</td></tr>
 431 </table>
 432 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
 433 <p >DMA Controller API. </p>
 434 <p >The RP-series microcontroller Direct Memory Access (DMA) master performs bulk data transfers on a processor’s behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states. The data throughput of the DMA is also significantly higher than one of RP-series microcontroller’s processors.</p>
 435 <p >The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle. There are 12 independent channels, which each supervise a sequence of bus transfers, usually in one of the following scenarios:</p>
 436 <ul>
 437 <li>Memory to peripheral</li>
 438 <li>Peripheral to memory</li>
 439 <li>Memory to memory </li>
 440 </ul>
 441 <h2 class="groupheader">Macro Definition Documentation</h2>
 442 <a id="ga6c72cc3aafb409371f60fefd0463e289" name="ga6c72cc3aafb409371f60fefd0463e289"></a>
 443 <h2 class="memtitle"><span class="permalink"><a href="#ga6c72cc3aafb409371f60fefd0463e289">&#9670;&nbsp;</a></span>DMA_IRQ_NUM</h2>
 444
 445 <div class="memitem">
 446 <div class="memproto">
 447       <table class="memname">
 448         <tr>
 449           <td class="memname">#define DMA_IRQ_NUM</td>
 450           <td>(</td>
 451           <td class="paramtype">&#160;</td>
 452           <td class="paramname">irq_index</td><td>)</td>
 453           <td></td>
 454         </tr>
 455       </table>
 456 </div><div class="memdoc">
 457
 458 <p>Returns the <a class="el" href="group__hardware__irq.html#gaf30862f51b5994ffd5863176a185d137">irq_num_t</a> for the nth DMA interrupt. </p>
 459 <p >Note this macro is intended to resolve at compile time, and does no parameter checking </p>
 460
 461 </div>
 462 </div>
 463 <h2 class="groupheader">Enumeration Type Documentation</h2>
 464 <a id="gaccecdff367b06a019373e9a55d4f3e01" name="gaccecdff367b06a019373e9a55d4f3e01"></a>
 465 <h2 class="memtitle"><span class="permalink"><a href="#gaccecdff367b06a019373e9a55d4f3e01">&#9670;&nbsp;</a></span>dma_channel_transfer_size</h2>
 466
 467 <div class="memitem">
 468 <div class="memproto">
 469       <table class="memname">
 470         <tr>
 471           <td class="memname">enum <a class="el" href="group__hardware__dma.html#gaccecdff367b06a019373e9a55d4f3e01">dma_channel_transfer_size</a></td>
 472         </tr>
 473       </table>
 474 </div><div class="memdoc">
 475
 476 <p>Enumeration of available DMA channel transfer sizes. </p>
 477 <p >Names indicate the number of bits. </p>
 478 <table class="fieldtable">
 479 <tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaccecdff367b06a019373e9a55d4f3e01abd7d246406a2ebe4dd49780db176dc3c" name="ggaccecdff367b06a019373e9a55d4f3e01abd7d246406a2ebe4dd49780db176dc3c"></a>DMA_SIZE_8&#160;</td><td class="fielddoc"><p >Byte transfer (8 bits) </p>
 480 </td></tr>
 481 <tr><td class="fieldname"><a id="ggaccecdff367b06a019373e9a55d4f3e01a2e343022ac046b6b67bb99eebc833cfc" name="ggaccecdff367b06a019373e9a55d4f3e01a2e343022ac046b6b67bb99eebc833cfc"></a>DMA_SIZE_16&#160;</td><td class="fielddoc"><p >Half word transfer (16 bits) </p>
 482 </td></tr>
 483 <tr><td class="fieldname"><a id="ggaccecdff367b06a019373e9a55d4f3e01abf1030013f4ad74b45d25cd9a07b6296" name="ggaccecdff367b06a019373e9a55d4f3e01abf1030013f4ad74b45d25cd9a07b6296"></a>DMA_SIZE_32&#160;</td><td class="fielddoc"><p >Word transfer (32 bits) </p>
 484 </td></tr>
 485 </table>
 486
 487 </div>
 488 </div>
 489 <a id="ga864c3313155ab20116b62a64bf78df6d" name="ga864c3313155ab20116b62a64bf78df6d"></a>
 490 <h2 class="memtitle"><span class="permalink"><a href="#ga864c3313155ab20116b62a64bf78df6d">&#9670;&nbsp;</a></span>dreq_num_rp2040</h2>
 491
 492 <div class="memitem">
 493 <div class="memproto">
 494       <table class="memname">
 495         <tr>
 496           <td class="memname">enum <a class="el" href="group__hardware__dma.html#ga864c3313155ab20116b62a64bf78df6d">dreq_num_rp2040</a></td>
 497         </tr>
 498       </table>
 499 </div><div class="memdoc">
 500
 501 <p>DREQ numbers for DMA pacing on RP2040 (used as typedef <a class="el" href="group__hardware__dma.html#ga8def0ea481095c94f3a0dd0b4fed999e">dreq_num_t</a>) </p>
 502 <table class="fieldtable">
 503 <tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dad7529b7e45af2d7eab4b740ff15b49d8" name="gga864c3313155ab20116b62a64bf78df6dad7529b7e45af2d7eab4b740ff15b49d8"></a>DREQ_PIO0_TX0&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 0 as DREQ. </p>
 504 </td></tr>
 505 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dac5fedec084064e1d9ff9c6a382c1ccf8" name="gga864c3313155ab20116b62a64bf78df6dac5fedec084064e1d9ff9c6a382c1ccf8"></a>DREQ_PIO0_TX1&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 1 as DREQ. </p>
 506 </td></tr>
 507 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6daa2e360dbf123d634d08e5fae27aa29e5" name="gga864c3313155ab20116b62a64bf78df6daa2e360dbf123d634d08e5fae27aa29e5"></a>DREQ_PIO0_TX2&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 2 as DREQ. </p>
 508 </td></tr>
 509 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da156b1b999c6b2dd877545c8c79060a30" name="gga864c3313155ab20116b62a64bf78df6da156b1b999c6b2dd877545c8c79060a30"></a>DREQ_PIO0_TX3&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 3 as DREQ. </p>
 510 </td></tr>
 511 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dac4bc12d74b758a7b39c1977c401e2fe1" name="gga864c3313155ab20116b62a64bf78df6dac4bc12d74b758a7b39c1977c401e2fe1"></a>DREQ_PIO0_RX0&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 0 as DREQ. </p>
 512 </td></tr>
 513 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da19b55b49bb618eed839edccba14c0d8f" name="gga864c3313155ab20116b62a64bf78df6da19b55b49bb618eed839edccba14c0d8f"></a>DREQ_PIO0_RX1&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 1 as DREQ. </p>
 514 </td></tr>
 515 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da967d6b5eb2d3e06113b2b1606ef2af2c" name="gga864c3313155ab20116b62a64bf78df6da967d6b5eb2d3e06113b2b1606ef2af2c"></a>DREQ_PIO0_RX2&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 2 as DREQ. </p>
 516 </td></tr>
 517 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da10f8705467782c859f05f82aa3c3c9f5" name="gga864c3313155ab20116b62a64bf78df6da10f8705467782c859f05f82aa3c3c9f5"></a>DREQ_PIO0_RX3&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 3 as DREQ. </p>
 518 </td></tr>
 519 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da3c22f2c9eb4a49654bba70dbc99bc893" name="gga864c3313155ab20116b62a64bf78df6da3c22f2c9eb4a49654bba70dbc99bc893"></a>DREQ_PIO1_TX0&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 0 as DREQ. </p>
 520 </td></tr>
 521 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da37f1bb39c3aa38a753df88e7e6c57feb" name="gga864c3313155ab20116b62a64bf78df6da37f1bb39c3aa38a753df88e7e6c57feb"></a>DREQ_PIO1_TX1&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 1 as DREQ. </p>
 522 </td></tr>
 523 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da13d7cb74708595298d788ba0ce25f6a0" name="gga864c3313155ab20116b62a64bf78df6da13d7cb74708595298d788ba0ce25f6a0"></a>DREQ_PIO1_TX2&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 2 as DREQ. </p>
 524 </td></tr>
 525 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6daaa5859ea1daaf5f0760fb4dea23116c3" name="gga864c3313155ab20116b62a64bf78df6daaa5859ea1daaf5f0760fb4dea23116c3"></a>DREQ_PIO1_TX3&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 3 as DREQ. </p>
 526 </td></tr>
 527 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da833bfa99e8b74de9bfc1872958a742e3" name="gga864c3313155ab20116b62a64bf78df6da833bfa99e8b74de9bfc1872958a742e3"></a>DREQ_PIO1_RX0&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 0 as DREQ. </p>
 528 </td></tr>
 529 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da8da9c5655eb51f2fb8a33b16827796a9" name="gga864c3313155ab20116b62a64bf78df6da8da9c5655eb51f2fb8a33b16827796a9"></a>DREQ_PIO1_RX1&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 1 as DREQ. </p>
 530 </td></tr>
 531 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da0198dfe2da7237817e780a483144df8f" name="gga864c3313155ab20116b62a64bf78df6da0198dfe2da7237817e780a483144df8f"></a>DREQ_PIO1_RX2&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 2 as DREQ. </p>
 532 </td></tr>
 533 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dab093d84a1df12a37ab6e9d62ee1f6d57" name="gga864c3313155ab20116b62a64bf78df6dab093d84a1df12a37ab6e9d62ee1f6d57"></a>DREQ_PIO1_RX3&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 3 as DREQ. </p>
 534 </td></tr>
 535 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da4b8b13f940414660401a7b334d85b64b" name="gga864c3313155ab20116b62a64bf78df6da4b8b13f940414660401a7b334d85b64b"></a>DREQ_SPI0_TX&#160;</td><td class="fielddoc"><p >Select SPI0's TX FIFO as DREQ. </p>
 536 </td></tr>
 537 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da46641088908dd355dc82971e7c7fbd35" name="gga864c3313155ab20116b62a64bf78df6da46641088908dd355dc82971e7c7fbd35"></a>DREQ_SPI0_RX&#160;</td><td class="fielddoc"><p >Select SPI0's RX FIFO as DREQ. </p>
 538 </td></tr>
 539 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da01d244742e157d2d2fb8e55b5fd6d81b" name="gga864c3313155ab20116b62a64bf78df6da01d244742e157d2d2fb8e55b5fd6d81b"></a>DREQ_SPI1_TX&#160;</td><td class="fielddoc"><p >Select SPI1's TX FIFO as DREQ. </p>
 540 </td></tr>
 541 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da04665a3e6a5c58a6cbf2d0fe1503cf00" name="gga864c3313155ab20116b62a64bf78df6da04665a3e6a5c58a6cbf2d0fe1503cf00"></a>DREQ_SPI1_RX&#160;</td><td class="fielddoc"><p >Select SPI1's RX FIFO as DREQ. </p>
 542 </td></tr>
 543 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da80ecb62e37f0c5af2780b93d4995326d" name="gga864c3313155ab20116b62a64bf78df6da80ecb62e37f0c5af2780b93d4995326d"></a>DREQ_UART0_TX&#160;</td><td class="fielddoc"><p >Select UART0's TX FIFO as DREQ. </p>
 544 </td></tr>
 545 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da4812587fa3aa4cfd7ea0d91e20246b95" name="gga864c3313155ab20116b62a64bf78df6da4812587fa3aa4cfd7ea0d91e20246b95"></a>DREQ_UART0_RX&#160;</td><td class="fielddoc"><p >Select UART0's RX FIFO as DREQ. </p>
 546 </td></tr>
 547 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6daa64110e7f89692b9c789275b4d8b04c0" name="gga864c3313155ab20116b62a64bf78df6daa64110e7f89692b9c789275b4d8b04c0"></a>DREQ_UART1_TX&#160;</td><td class="fielddoc"><p >Select UART1's TX FIFO as DREQ. </p>
 548 </td></tr>
 549 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dae5c7e2a566983a1148113e2987e059d5" name="gga864c3313155ab20116b62a64bf78df6dae5c7e2a566983a1148113e2987e059d5"></a>DREQ_UART1_RX&#160;</td><td class="fielddoc"><p >Select UART1's RX FIFO as DREQ. </p>
 550 </td></tr>
 551 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da2a861c9dcce9e158ace7bc5d547ebde1" name="gga864c3313155ab20116b62a64bf78df6da2a861c9dcce9e158ace7bc5d547ebde1"></a>DREQ_PWM_WRAP0&#160;</td><td class="fielddoc"><p >Select PWM Counter 0's Wrap Value as DREQ. </p>
 552 </td></tr>
 553 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da1504bdb2bd8aaa535903ea11aa2c2994" name="gga864c3313155ab20116b62a64bf78df6da1504bdb2bd8aaa535903ea11aa2c2994"></a>DREQ_PWM_WRAP1&#160;</td><td class="fielddoc"><p >Select PWM Counter 1's Wrap Value as DREQ. </p>
 554 </td></tr>
 555 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dacb766e3b38daca5c8cd35459d835d7a2" name="gga864c3313155ab20116b62a64bf78df6dacb766e3b38daca5c8cd35459d835d7a2"></a>DREQ_PWM_WRAP2&#160;</td><td class="fielddoc"><p >Select PWM Counter 2's Wrap Value as DREQ. </p>
 556 </td></tr>
 557 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da017ebaacb45d90c4f20db2d5edded874" name="gga864c3313155ab20116b62a64bf78df6da017ebaacb45d90c4f20db2d5edded874"></a>DREQ_PWM_WRAP3&#160;</td><td class="fielddoc"><p >Select PWM Counter 3's Wrap Value as DREQ. </p>
 558 </td></tr>
 559 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da5fdd41bb900549d6ff26772cc9fd507a" name="gga864c3313155ab20116b62a64bf78df6da5fdd41bb900549d6ff26772cc9fd507a"></a>DREQ_PWM_WRAP4&#160;</td><td class="fielddoc"><p >Select PWM Counter 4's Wrap Value as DREQ. </p>
 560 </td></tr>
 561 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6daced239695d7bf65c41827e1eb6cbc04a" name="gga864c3313155ab20116b62a64bf78df6daced239695d7bf65c41827e1eb6cbc04a"></a>DREQ_PWM_WRAP5&#160;</td><td class="fielddoc"><p >Select PWM Counter 5's Wrap Value as DREQ. </p>
 562 </td></tr>
 563 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dadd0e022489d6ad4f835a97c6e354c15b" name="gga864c3313155ab20116b62a64bf78df6dadd0e022489d6ad4f835a97c6e354c15b"></a>DREQ_PWM_WRAP6&#160;</td><td class="fielddoc"><p >Select PWM Counter 6's Wrap Value as DREQ. </p>
 564 </td></tr>
 565 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dadafe5a7f2f401a496e842c7a2c95dac5" name="gga864c3313155ab20116b62a64bf78df6dadafe5a7f2f401a496e842c7a2c95dac5"></a>DREQ_PWM_WRAP7&#160;</td><td class="fielddoc"><p >Select PWM Counter 7's Wrap Value as DREQ. </p>
 566 </td></tr>
 567 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dab51c1095a1fec8ad39050cf49fd01835" name="gga864c3313155ab20116b62a64bf78df6dab51c1095a1fec8ad39050cf49fd01835"></a>DREQ_I2C0_TX&#160;</td><td class="fielddoc"><p >Select I2C0's TX FIFO as DREQ. </p>
 568 </td></tr>
 569 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da675d15a4afa861045235a441d46d0580" name="gga864c3313155ab20116b62a64bf78df6da675d15a4afa861045235a441d46d0580"></a>DREQ_I2C0_RX&#160;</td><td class="fielddoc"><p >Select I2C0's RX FIFO as DREQ. </p>
 570 </td></tr>
 571 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da74c786868da56dbb18b7da2c7748568f" name="gga864c3313155ab20116b62a64bf78df6da74c786868da56dbb18b7da2c7748568f"></a>DREQ_I2C1_TX&#160;</td><td class="fielddoc"><p >Select I2C1's TX FIFO as DREQ. </p>
 572 </td></tr>
 573 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da0b5156eb2381872ddc1837d83de16b8b" name="gga864c3313155ab20116b62a64bf78df6da0b5156eb2381872ddc1837d83de16b8b"></a>DREQ_I2C1_RX&#160;</td><td class="fielddoc"><p >Select I2C1's RX FIFO as DREQ. </p>
 574 </td></tr>
 575 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da5f3aedb5ef1de25b99afcde8742b4590" name="gga864c3313155ab20116b62a64bf78df6da5f3aedb5ef1de25b99afcde8742b4590"></a>DREQ_ADC&#160;</td><td class="fielddoc"><p >Select the ADC as DREQ. </p>
 576 </td></tr>
 577 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6daedbcc51f819f4c85c3ab8f51b654ebdc" name="gga864c3313155ab20116b62a64bf78df6daedbcc51f819f4c85c3ab8f51b654ebdc"></a>DREQ_XIP_STREAM&#160;</td><td class="fielddoc"><p >Select the XIP Streaming FIFO as DREQ. </p>
 578 </td></tr>
 579 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dabaf536bfba84db157116952ae4a5d466" name="gga864c3313155ab20116b62a64bf78df6dabaf536bfba84db157116952ae4a5d466"></a>DREQ_XIP_SSITX&#160;</td><td class="fielddoc"><p >Select the XIP SSI TX FIFO as DREQ. </p>
 580 </td></tr>
 581 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da74f7500adc3af744bfe564b1c90aba0a" name="gga864c3313155ab20116b62a64bf78df6da74f7500adc3af744bfe564b1c90aba0a"></a>DREQ_XIP_SSIRX&#160;</td><td class="fielddoc"><p >Select the XIP SSI RX FIFO as DREQ. </p>
 582 </td></tr>
 583 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da49bb6d90479edbff257068afd1a5bfe1" name="gga864c3313155ab20116b62a64bf78df6da49bb6d90479edbff257068afd1a5bfe1"></a>DREQ_DMA_TIMER0&#160;</td><td class="fielddoc"><p >Select DMA_TIMER0 as DREQ. </p>
 584 </td></tr>
 585 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da11c9291490c2ddf45df69f45a2f83dcf" name="gga864c3313155ab20116b62a64bf78df6da11c9291490c2ddf45df69f45a2f83dcf"></a>DREQ_DMA_TIMER1&#160;</td><td class="fielddoc"><p >Select DMA_TIMER0 as DREQ. </p>
 586 </td></tr>
 587 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dabb60a9d9038192f9db081b51b9c23f65" name="gga864c3313155ab20116b62a64bf78df6dabb60a9d9038192f9db081b51b9c23f65"></a>DREQ_DMA_TIMER2&#160;</td><td class="fielddoc"><p >Select DMA_TIMER1 as DREQ. </p>
 588 </td></tr>
 589 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6da86d08425822a129c3eaa1479e920c67c" name="gga864c3313155ab20116b62a64bf78df6da86d08425822a129c3eaa1479e920c67c"></a>DREQ_DMA_TIMER3&#160;</td><td class="fielddoc"><p >Select DMA_TIMER3 as DREQ. </p>
 590 </td></tr>
 591 <tr><td class="fieldname"><a id="gga864c3313155ab20116b62a64bf78df6dae683f0bb3ee8b854fe4cea850cf9d4c8" name="gga864c3313155ab20116b62a64bf78df6dae683f0bb3ee8b854fe4cea850cf9d4c8"></a>DREQ_FORCE&#160;</td><td class="fielddoc"><p >Select FORCE as DREQ. </p>
 592 </td></tr>
 593 </table>
 594
 595 </div>
 596 </div>
 597 <a id="ga6f0a19defc495cfa6078364122266014" name="ga6f0a19defc495cfa6078364122266014"></a>
 598 <h2 class="memtitle"><span class="permalink"><a href="#ga6f0a19defc495cfa6078364122266014">&#9670;&nbsp;</a></span>dreq_num_rp2350</h2>
 599
 600 <div class="memitem">
 601 <div class="memproto">
 602       <table class="memname">
 603         <tr>
 604           <td class="memname">enum <a class="el" href="group__hardware__dma.html#ga6f0a19defc495cfa6078364122266014">dreq_num_rp2350</a></td>
 605         </tr>
 606       </table>
 607 </div><div class="memdoc">
 608
 609 <p>DREQ numbers for DMA pacing on RP2350 (used as typedef <a class="el" href="group__hardware__dma.html#ga8def0ea481095c94f3a0dd0b4fed999e">dreq_num_t</a>) </p>
 610 <table class="fieldtable">
 611 <tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ad7529b7e45af2d7eab4b740ff15b49d8" name="gga6f0a19defc495cfa6078364122266014ad7529b7e45af2d7eab4b740ff15b49d8"></a>DREQ_PIO0_TX0&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 0 as DREQ. </p>
 612 </td></tr>
 613 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ac5fedec084064e1d9ff9c6a382c1ccf8" name="gga6f0a19defc495cfa6078364122266014ac5fedec084064e1d9ff9c6a382c1ccf8"></a>DREQ_PIO0_TX1&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 1 as DREQ. </p>
 614 </td></tr>
 615 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014aa2e360dbf123d634d08e5fae27aa29e5" name="gga6f0a19defc495cfa6078364122266014aa2e360dbf123d634d08e5fae27aa29e5"></a>DREQ_PIO0_TX2&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 2 as DREQ. </p>
 616 </td></tr>
 617 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a156b1b999c6b2dd877545c8c79060a30" name="gga6f0a19defc495cfa6078364122266014a156b1b999c6b2dd877545c8c79060a30"></a>DREQ_PIO0_TX3&#160;</td><td class="fielddoc"><p >Select PIO0's TX FIFO 3 as DREQ. </p>
 618 </td></tr>
 619 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ac4bc12d74b758a7b39c1977c401e2fe1" name="gga6f0a19defc495cfa6078364122266014ac4bc12d74b758a7b39c1977c401e2fe1"></a>DREQ_PIO0_RX0&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 0 as DREQ. </p>
 620 </td></tr>
 621 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a19b55b49bb618eed839edccba14c0d8f" name="gga6f0a19defc495cfa6078364122266014a19b55b49bb618eed839edccba14c0d8f"></a>DREQ_PIO0_RX1&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 1 as DREQ. </p>
 622 </td></tr>
 623 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a967d6b5eb2d3e06113b2b1606ef2af2c" name="gga6f0a19defc495cfa6078364122266014a967d6b5eb2d3e06113b2b1606ef2af2c"></a>DREQ_PIO0_RX2&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 2 as DREQ. </p>
 624 </td></tr>
 625 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a10f8705467782c859f05f82aa3c3c9f5" name="gga6f0a19defc495cfa6078364122266014a10f8705467782c859f05f82aa3c3c9f5"></a>DREQ_PIO0_RX3&#160;</td><td class="fielddoc"><p >Select PIO0's RX FIFO 3 as DREQ. </p>
 626 </td></tr>
 627 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a3c22f2c9eb4a49654bba70dbc99bc893" name="gga6f0a19defc495cfa6078364122266014a3c22f2c9eb4a49654bba70dbc99bc893"></a>DREQ_PIO1_TX0&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 0 as DREQ. </p>
 628 </td></tr>
 629 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a37f1bb39c3aa38a753df88e7e6c57feb" name="gga6f0a19defc495cfa6078364122266014a37f1bb39c3aa38a753df88e7e6c57feb"></a>DREQ_PIO1_TX1&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 1 as DREQ. </p>
 630 </td></tr>
 631 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a13d7cb74708595298d788ba0ce25f6a0" name="gga6f0a19defc495cfa6078364122266014a13d7cb74708595298d788ba0ce25f6a0"></a>DREQ_PIO1_TX2&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 2 as DREQ. </p>
 632 </td></tr>
 633 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014aaa5859ea1daaf5f0760fb4dea23116c3" name="gga6f0a19defc495cfa6078364122266014aaa5859ea1daaf5f0760fb4dea23116c3"></a>DREQ_PIO1_TX3&#160;</td><td class="fielddoc"><p >Select PIO1's TX FIFO 3 as DREQ. </p>
 634 </td></tr>
 635 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a833bfa99e8b74de9bfc1872958a742e3" name="gga6f0a19defc495cfa6078364122266014a833bfa99e8b74de9bfc1872958a742e3"></a>DREQ_PIO1_RX0&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 0 as DREQ. </p>
 636 </td></tr>
 637 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a8da9c5655eb51f2fb8a33b16827796a9" name="gga6f0a19defc495cfa6078364122266014a8da9c5655eb51f2fb8a33b16827796a9"></a>DREQ_PIO1_RX1&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 1 as DREQ. </p>
 638 </td></tr>
 639 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a0198dfe2da7237817e780a483144df8f" name="gga6f0a19defc495cfa6078364122266014a0198dfe2da7237817e780a483144df8f"></a>DREQ_PIO1_RX2&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 2 as DREQ. </p>
 640 </td></tr>
 641 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ab093d84a1df12a37ab6e9d62ee1f6d57" name="gga6f0a19defc495cfa6078364122266014ab093d84a1df12a37ab6e9d62ee1f6d57"></a>DREQ_PIO1_RX3&#160;</td><td class="fielddoc"><p >Select PIO1's RX FIFO 3 as DREQ. </p>
 642 </td></tr>
 643 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a6a3e73df9d0e562b41b571e272100302" name="gga6f0a19defc495cfa6078364122266014a6a3e73df9d0e562b41b571e272100302"></a>DREQ_PIO2_TX0&#160;</td><td class="fielddoc"><p >Select PIO2's TX FIFO 0 as DREQ. </p>
 644 </td></tr>
 645 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a37c21bac317747dda953dca55954db16" name="gga6f0a19defc495cfa6078364122266014a37c21bac317747dda953dca55954db16"></a>DREQ_PIO2_TX1&#160;</td><td class="fielddoc"><p >Select PIO2's TX FIFO 1 as DREQ. </p>
 646 </td></tr>
 647 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014abadc20c78c83d2db4fcf3980f1d5b87f" name="gga6f0a19defc495cfa6078364122266014abadc20c78c83d2db4fcf3980f1d5b87f"></a>DREQ_PIO2_TX2&#160;</td><td class="fielddoc"><p >Select PIO2's TX FIFO 2 as DREQ. </p>
 648 </td></tr>
 649 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014aa94c2b7f002c28a6050dda127aeaf3b1" name="gga6f0a19defc495cfa6078364122266014aa94c2b7f002c28a6050dda127aeaf3b1"></a>DREQ_PIO2_TX3&#160;</td><td class="fielddoc"><p >Select PIO2's TX FIFO 3 as DREQ. </p>
 650 </td></tr>
 651 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a8bb28cdeea9248c04665464cabc6b1e6" name="gga6f0a19defc495cfa6078364122266014a8bb28cdeea9248c04665464cabc6b1e6"></a>DREQ_PIO2_RX0&#160;</td><td class="fielddoc"><p >Select PIO2's RX FIFO 0 as DREQ. </p>
 652 </td></tr>
 653 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a58a5eb511f85599b5e2b93cee7537b18" name="gga6f0a19defc495cfa6078364122266014a58a5eb511f85599b5e2b93cee7537b18"></a>DREQ_PIO2_RX1&#160;</td><td class="fielddoc"><p >Select PIO2's RX FIFO 1 as DREQ. </p>
 654 </td></tr>
 655 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a9f4f2e7b3cf525ff519db02b0047bf87" name="gga6f0a19defc495cfa6078364122266014a9f4f2e7b3cf525ff519db02b0047bf87"></a>DREQ_PIO2_RX2&#160;</td><td class="fielddoc"><p >Select PIO2's RX FIFO 2 as DREQ. </p>
 656 </td></tr>
 657 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ae7c631f739c8fb2e161c88911376ab26" name="gga6f0a19defc495cfa6078364122266014ae7c631f739c8fb2e161c88911376ab26"></a>DREQ_PIO2_RX3&#160;</td><td class="fielddoc"><p >Select PIO2's RX FIFO 3 as DREQ. </p>
 658 </td></tr>
 659 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a4b8b13f940414660401a7b334d85b64b" name="gga6f0a19defc495cfa6078364122266014a4b8b13f940414660401a7b334d85b64b"></a>DREQ_SPI0_TX&#160;</td><td class="fielddoc"><p >Select SPI0's TX FIFO as DREQ. </p>
 660 </td></tr>
 661 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a46641088908dd355dc82971e7c7fbd35" name="gga6f0a19defc495cfa6078364122266014a46641088908dd355dc82971e7c7fbd35"></a>DREQ_SPI0_RX&#160;</td><td class="fielddoc"><p >Select SPI0's RX FIFO as DREQ. </p>
 662 </td></tr>
 663 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a01d244742e157d2d2fb8e55b5fd6d81b" name="gga6f0a19defc495cfa6078364122266014a01d244742e157d2d2fb8e55b5fd6d81b"></a>DREQ_SPI1_TX&#160;</td><td class="fielddoc"><p >Select SPI1's TX FIFO as DREQ. </p>
 664 </td></tr>
 665 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a04665a3e6a5c58a6cbf2d0fe1503cf00" name="gga6f0a19defc495cfa6078364122266014a04665a3e6a5c58a6cbf2d0fe1503cf00"></a>DREQ_SPI1_RX&#160;</td><td class="fielddoc"><p >Select SPI1's RX FIFO as DREQ. </p>
 666 </td></tr>
 667 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a80ecb62e37f0c5af2780b93d4995326d" name="gga6f0a19defc495cfa6078364122266014a80ecb62e37f0c5af2780b93d4995326d"></a>DREQ_UART0_TX&#160;</td><td class="fielddoc"><p >Select UART0's TX FIFO as DREQ. </p>
 668 </td></tr>
 669 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a4812587fa3aa4cfd7ea0d91e20246b95" name="gga6f0a19defc495cfa6078364122266014a4812587fa3aa4cfd7ea0d91e20246b95"></a>DREQ_UART0_RX&#160;</td><td class="fielddoc"><p >Select UART0's RX FIFO as DREQ. </p>
 670 </td></tr>
 671 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014aa64110e7f89692b9c789275b4d8b04c0" name="gga6f0a19defc495cfa6078364122266014aa64110e7f89692b9c789275b4d8b04c0"></a>DREQ_UART1_TX&#160;</td><td class="fielddoc"><p >Select UART1's TX FIFO as DREQ. </p>
 672 </td></tr>
 673 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ae5c7e2a566983a1148113e2987e059d5" name="gga6f0a19defc495cfa6078364122266014ae5c7e2a566983a1148113e2987e059d5"></a>DREQ_UART1_RX&#160;</td><td class="fielddoc"><p >Select UART1's RX FIFO as DREQ. </p>
 674 </td></tr>
 675 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a2a861c9dcce9e158ace7bc5d547ebde1" name="gga6f0a19defc495cfa6078364122266014a2a861c9dcce9e158ace7bc5d547ebde1"></a>DREQ_PWM_WRAP0&#160;</td><td class="fielddoc"><p >Select PWM Counter 0's Wrap Value as DREQ. </p>
 676 </td></tr>
 677 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a1504bdb2bd8aaa535903ea11aa2c2994" name="gga6f0a19defc495cfa6078364122266014a1504bdb2bd8aaa535903ea11aa2c2994"></a>DREQ_PWM_WRAP1&#160;</td><td class="fielddoc"><p >Select PWM Counter 1's Wrap Value as DREQ. </p>
 678 </td></tr>
 679 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014acb766e3b38daca5c8cd35459d835d7a2" name="gga6f0a19defc495cfa6078364122266014acb766e3b38daca5c8cd35459d835d7a2"></a>DREQ_PWM_WRAP2&#160;</td><td class="fielddoc"><p >Select PWM Counter 2's Wrap Value as DREQ. </p>
 680 </td></tr>
 681 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a017ebaacb45d90c4f20db2d5edded874" name="gga6f0a19defc495cfa6078364122266014a017ebaacb45d90c4f20db2d5edded874"></a>DREQ_PWM_WRAP3&#160;</td><td class="fielddoc"><p >Select PWM Counter 3's Wrap Value as DREQ. </p>
 682 </td></tr>
 683 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a5fdd41bb900549d6ff26772cc9fd507a" name="gga6f0a19defc495cfa6078364122266014a5fdd41bb900549d6ff26772cc9fd507a"></a>DREQ_PWM_WRAP4&#160;</td><td class="fielddoc"><p >Select PWM Counter 4's Wrap Value as DREQ. </p>
 684 </td></tr>
 685 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014aced239695d7bf65c41827e1eb6cbc04a" name="gga6f0a19defc495cfa6078364122266014aced239695d7bf65c41827e1eb6cbc04a"></a>DREQ_PWM_WRAP5&#160;</td><td class="fielddoc"><p >Select PWM Counter 5's Wrap Value as DREQ. </p>
 686 </td></tr>
 687 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014add0e022489d6ad4f835a97c6e354c15b" name="gga6f0a19defc495cfa6078364122266014add0e022489d6ad4f835a97c6e354c15b"></a>DREQ_PWM_WRAP6&#160;</td><td class="fielddoc"><p >Select PWM Counter 6's Wrap Value as DREQ. </p>
 688 </td></tr>
 689 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014adafe5a7f2f401a496e842c7a2c95dac5" name="gga6f0a19defc495cfa6078364122266014adafe5a7f2f401a496e842c7a2c95dac5"></a>DREQ_PWM_WRAP7&#160;</td><td class="fielddoc"><p >Select PWM Counter 7's Wrap Value as DREQ. </p>
 690 </td></tr>
 691 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a4ab337ff0746f2d9d432020658a478af" name="gga6f0a19defc495cfa6078364122266014a4ab337ff0746f2d9d432020658a478af"></a>DREQ_PWM_WRAP8&#160;</td><td class="fielddoc"><p >Select PWM Counter 8's Wrap Value as DREQ. </p>
 692 </td></tr>
 693 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a8d7bd836d3ba015fc800e227b6408f73" name="gga6f0a19defc495cfa6078364122266014a8d7bd836d3ba015fc800e227b6408f73"></a>DREQ_PWM_WRAP9&#160;</td><td class="fielddoc"><p >Select PWM Counter 9's Wrap Value as DREQ. </p>
 694 </td></tr>
 695 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ad17feaa0e6a99ccf14b5d7285ab363d1" name="gga6f0a19defc495cfa6078364122266014ad17feaa0e6a99ccf14b5d7285ab363d1"></a>DREQ_PWM_WRAP10&#160;</td><td class="fielddoc"><p >Select PWM Counter 0's Wrap Value as DREQ. </p>
 696 </td></tr>
 697 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a14ba987e523bd38f813f93322d053a4c" name="gga6f0a19defc495cfa6078364122266014a14ba987e523bd38f813f93322d053a4c"></a>DREQ_PWM_WRAP11&#160;</td><td class="fielddoc"><p >Select PWM Counter 1's Wrap Value as DREQ. </p>
 698 </td></tr>
 699 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ab51c1095a1fec8ad39050cf49fd01835" name="gga6f0a19defc495cfa6078364122266014ab51c1095a1fec8ad39050cf49fd01835"></a>DREQ_I2C0_TX&#160;</td><td class="fielddoc"><p >Select I2C0's TX FIFO as DREQ. </p>
 700 </td></tr>
 701 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a675d15a4afa861045235a441d46d0580" name="gga6f0a19defc495cfa6078364122266014a675d15a4afa861045235a441d46d0580"></a>DREQ_I2C0_RX&#160;</td><td class="fielddoc"><p >Select I2C0's RX FIFO as DREQ. </p>
 702 </td></tr>
 703 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a74c786868da56dbb18b7da2c7748568f" name="gga6f0a19defc495cfa6078364122266014a74c786868da56dbb18b7da2c7748568f"></a>DREQ_I2C1_TX&#160;</td><td class="fielddoc"><p >Select I2C1's TX FIFO as DREQ. </p>
 704 </td></tr>
 705 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a0b5156eb2381872ddc1837d83de16b8b" name="gga6f0a19defc495cfa6078364122266014a0b5156eb2381872ddc1837d83de16b8b"></a>DREQ_I2C1_RX&#160;</td><td class="fielddoc"><p >Select I2C1's RX FIFO as DREQ. </p>
 706 </td></tr>
 707 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a5f3aedb5ef1de25b99afcde8742b4590" name="gga6f0a19defc495cfa6078364122266014a5f3aedb5ef1de25b99afcde8742b4590"></a>DREQ_ADC&#160;</td><td class="fielddoc"><p >Select the ADC as DREQ. </p>
 708 </td></tr>
 709 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014aedbcc51f819f4c85c3ab8f51b654ebdc" name="gga6f0a19defc495cfa6078364122266014aedbcc51f819f4c85c3ab8f51b654ebdc"></a>DREQ_XIP_STREAM&#160;</td><td class="fielddoc"><p >Select the XIP Streaming FIFO as DREQ. </p>
 710 </td></tr>
 711 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a79533c8a78e8f62f1f564954a755e02a" name="gga6f0a19defc495cfa6078364122266014a79533c8a78e8f62f1f564954a755e02a"></a>DREQ_XIP_QMITX&#160;</td><td class="fielddoc"><p >Select XIP_QMITX as DREQ. </p>
 712 </td></tr>
 713 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a35519b1f622ee38560ffd2dfa1571c9b" name="gga6f0a19defc495cfa6078364122266014a35519b1f622ee38560ffd2dfa1571c9b"></a>DREQ_XIP_QMIRX&#160;</td><td class="fielddoc"><p >Select XIP_QMIRX as DREQ. </p>
 714 </td></tr>
 715 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a71865f5a1fc034131dfb351d2c830c03" name="gga6f0a19defc495cfa6078364122266014a71865f5a1fc034131dfb351d2c830c03"></a>DREQ_HSTX&#160;</td><td class="fielddoc"><p >Select HSTX as DREQ. </p>
 716 </td></tr>
 717 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a1ef0656e59fedc445052acc548cce490" name="gga6f0a19defc495cfa6078364122266014a1ef0656e59fedc445052acc548cce490"></a>DREQ_CORESIGHT&#160;</td><td class="fielddoc"><p >Select CORESIGHT as DREQ. </p>
 718 </td></tr>
 719 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a7a5f3a4ca267d2cd53c43779fb5494ba" name="gga6f0a19defc495cfa6078364122266014a7a5f3a4ca267d2cd53c43779fb5494ba"></a>DREQ_SHA256&#160;</td><td class="fielddoc"><p >Select SHA256 as DREQ. </p>
 720 </td></tr>
 721 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a49bb6d90479edbff257068afd1a5bfe1" name="gga6f0a19defc495cfa6078364122266014a49bb6d90479edbff257068afd1a5bfe1"></a>DREQ_DMA_TIMER0&#160;</td><td class="fielddoc"><p >Select DMA_TIMER0 as DREQ. </p>
 722 </td></tr>
 723 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a11c9291490c2ddf45df69f45a2f83dcf" name="gga6f0a19defc495cfa6078364122266014a11c9291490c2ddf45df69f45a2f83dcf"></a>DREQ_DMA_TIMER1&#160;</td><td class="fielddoc"><p >Select DMA_TIMER0 as DREQ. </p>
 724 </td></tr>
 725 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014abb60a9d9038192f9db081b51b9c23f65" name="gga6f0a19defc495cfa6078364122266014abb60a9d9038192f9db081b51b9c23f65"></a>DREQ_DMA_TIMER2&#160;</td><td class="fielddoc"><p >Select DMA_TIMER1 as DREQ. </p>
 726 </td></tr>
 727 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014a86d08425822a129c3eaa1479e920c67c" name="gga6f0a19defc495cfa6078364122266014a86d08425822a129c3eaa1479e920c67c"></a>DREQ_DMA_TIMER3&#160;</td><td class="fielddoc"><p >Select DMA_TIMER3 as DREQ. </p>
 728 </td></tr>
 729 <tr><td class="fieldname"><a id="gga6f0a19defc495cfa6078364122266014ae683f0bb3ee8b854fe4cea850cf9d4c8" name="gga6f0a19defc495cfa6078364122266014ae683f0bb3ee8b854fe4cea850cf9d4c8"></a>DREQ_FORCE&#160;</td><td class="fielddoc"><p >Select FORCE as DREQ. </p>
 730 </td></tr>
 731 </table>
 732
 733 </div>
 734 </div>
 735 <h2 class="groupheader">Function Documentation</h2>
 736 <a id="ga735e7c6c136c078689ead70790f4edb2" name="ga735e7c6c136c078689ead70790f4edb2"></a>
 737 <h2 class="memtitle"><span class="permalink"><a href="#ga735e7c6c136c078689ead70790f4edb2">&#9670;&nbsp;</a></span>dma_channel_abort()</h2>
 738
 739 <div class="memitem">
 740 <div class="memproto">
 741 <table class="mlabels">
 742   <tr>
 743   <td class="mlabels-left">
 744       <table class="memname">
 745         <tr>
 746           <td class="memname">static void dma_channel_abort </td>
 747           <td>(</td>
 748           <td class="paramtype">uint&#160;</td>
 749           <td class="paramname"><em>channel</em></td><td>)</td>
 750           <td></td>
 751         </tr>
 752       </table>
 753   </td>
 754   <td class="mlabels-right">
 755 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
 756   </tr>
 757 </table>
 758 </div><div class="memdoc">
 759
 760 <p>Stop a DMA transfer. </p>
 761 <p >Function will only return once the DMA has stopped.</p>
 762 <p >RP2040 only: Note that due to errata RP2040-E13, aborting a channel which has transfers in-flight (i.e. an individual read has taken place but the corresponding write has not), the ABORT status bit will clear prematurely, and subsequently the in-flight transfers will trigger a completion interrupt once they complete. </p>
 763 <p >The effect of this is that you <em>may</em> see a spurious completion interrupt on the channel as a result of calling this method.</p>
 764 <p >The calling code should be sure to ignore a completion IRQ as a result of this method. This may not require any additional work, as aborting a channel which may be about to complete, when you have a completion IRQ handler registered, is inherently race-prone, and so code is likely needed to disambiguate the two occurrences.</p>
 765 <p >If that is not the case, but you do have a channel completion IRQ handler registered, you can simply disable/re-enable the IRQ around the call to this method as shown by this code fragment (using DMA IRQ0).</p>
 766 <div class="fragment"><div class="line"><span class="comment">// disable the channel on IRQ0</span></div>
 767 <div class="line"><a class="code hl_function" href="group__hardware__dma.html#gaf60011d46676c87b7139f37188eaa4b9">dma_channel_set_irq0_enabled</a>(channel, <span class="keyword">false</span>);</div>
 768 <div class="line"><span class="comment">// abort the channel</span></div>
 769 <div class="line"><a class="code hl_function" href="group__hardware__dma.html#ga735e7c6c136c078689ead70790f4edb2">dma_channel_abort</a>(channel);</div>
 770 <div class="line"><span class="comment">// clear the spurious IRQ (if there was one)</span></div>
 771 <div class="line"><a class="code hl_function" href="group__hardware__dma.html#gafefe50f20c44bcfa7f729829a5d494f4">dma_channel_acknowledge_irq0</a>(channel);</div>
 772 <div class="line"><span class="comment">// re-enable the channel on IRQ0</span></div>
 773 <div class="line"><a class="code hl_function" href="group__hardware__dma.html#gaf60011d46676c87b7139f37188eaa4b9">dma_channel_set_irq0_enabled</a>(channel, <span class="keyword">true</span>);</div>
 774 <div class="ttc" id="agroup__hardware__dma_html_ga735e7c6c136c078689ead70790f4edb2"><div class="ttname"><a href="group__hardware__dma.html#ga735e7c6c136c078689ead70790f4edb2">dma_channel_abort</a></div><div class="ttdeci">static void dma_channel_abort(uint channel)</div><div class="ttdoc">Stop a DMA transfer.</div><div class="ttdef"><b>Definition:</b> dma.h:544</div></div>
 775 <div class="ttc" id="agroup__hardware__dma_html_gaf60011d46676c87b7139f37188eaa4b9"><div class="ttname"><a href="group__hardware__dma.html#gaf60011d46676c87b7139f37188eaa4b9">dma_channel_set_irq0_enabled</a></div><div class="ttdeci">static void dma_channel_set_irq0_enabled(uint channel, bool enabled)</div><div class="ttdoc">Enable single DMA channel's interrupt via DMA_IRQ_0.</div><div class="ttdef"><b>Definition:</b> dma.h:558</div></div>
 776 <div class="ttc" id="agroup__hardware__dma_html_gafefe50f20c44bcfa7f729829a5d494f4"><div class="ttname"><a href="group__hardware__dma.html#gafefe50f20c44bcfa7f729829a5d494f4">dma_channel_acknowledge_irq0</a></div><div class="ttdeci">static void dma_channel_acknowledge_irq0(uint channel)</div><div class="ttdoc">Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0.</div><div class="ttdef"><b>Definition:</b> dma.h:682</div></div>
 777 </div><!-- fragment --><p >RP2350 only: Due to errata RP12350-E5 (see the RP2350 datasheet for further detail), it is necessary to clear the enable bit of the aborted channel and any chained channels prior to the abort to prevent re-triggering. </p>
 778 <dl class="params"><dt>Parameters</dt><dd>
 779   <table class="params">
 780     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
 781   </table>
 782   </dd>
 783 </dl>
 784
 785 </div>
 786 </div>
 787 <a id="gafefe50f20c44bcfa7f729829a5d494f4" name="gafefe50f20c44bcfa7f729829a5d494f4"></a>
 788 <h2 class="memtitle"><span class="permalink"><a href="#gafefe50f20c44bcfa7f729829a5d494f4">&#9670;&nbsp;</a></span>dma_channel_acknowledge_irq0()</h2>
 789
 790 <div class="memitem">
 791 <div class="memproto">
 792 <table class="mlabels">
 793   <tr>
 794   <td class="mlabels-left">
 795       <table class="memname">
 796         <tr>
 797           <td class="memname">static void dma_channel_acknowledge_irq0 </td>
 798           <td>(</td>
 799           <td class="paramtype">uint&#160;</td>
 800           <td class="paramname"><em>channel</em></td><td>)</td>
 801           <td></td>
 802         </tr>
 803       </table>
 804   </td>
 805   <td class="mlabels-right">
 806 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
 807   </tr>
 808 </table>
 809 </div><div class="memdoc">
 810
 811 <p>Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0. </p>
 812 <dl class="params"><dt>Parameters</dt><dd>
 813   <table class="params">
 814     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
 815   </table>
 816   </dd>
 817 </dl>
 818
 819 </div>
 820 </div>
 821 <a id="ga4d4b5d461ff09bb6e4e2a05df3b7c75c" name="ga4d4b5d461ff09bb6e4e2a05df3b7c75c"></a>
 822 <h2 class="memtitle"><span class="permalink"><a href="#ga4d4b5d461ff09bb6e4e2a05df3b7c75c">&#9670;&nbsp;</a></span>dma_channel_acknowledge_irq1()</h2>
 823
 824 <div class="memitem">
 825 <div class="memproto">
 826 <table class="mlabels">
 827   <tr>
 828   <td class="mlabels-left">
 829       <table class="memname">
 830         <tr>
 831           <td class="memname">static void dma_channel_acknowledge_irq1 </td>
 832           <td>(</td>
 833           <td class="paramtype">uint&#160;</td>
 834           <td class="paramname"><em>channel</em></td><td>)</td>
 835           <td></td>
 836         </tr>
 837       </table>
 838   </td>
 839   <td class="mlabels-right">
 840 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
 841   </tr>
 842 </table>
 843 </div><div class="memdoc">
 844
 845 <p>Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1. </p>
 846 <dl class="params"><dt>Parameters</dt><dd>
 847   <table class="params">
 848     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
 849   </table>
 850   </dd>
 851 </dl>
 852
 853 </div>
 854 </div>
 855 <a id="gae1b3c916746b3d2052f21b7dda34aab9" name="gae1b3c916746b3d2052f21b7dda34aab9"></a>
 856 <h2 class="memtitle"><span class="permalink"><a href="#gae1b3c916746b3d2052f21b7dda34aab9">&#9670;&nbsp;</a></span>dma_channel_claim()</h2>
 857
 858 <div class="memitem">
 859 <div class="memproto">
 860       <table class="memname">
 861         <tr>
 862           <td class="memname">void dma_channel_claim </td>
 863           <td>(</td>
 864           <td class="paramtype">uint&#160;</td>
 865           <td class="paramname"><em>channel</em></td><td>)</td>
 866           <td></td>
 867         </tr>
 868       </table>
 869 </div><div class="memdoc">
 870
 871 <p>Mark a dma channel as used. </p>
 872 <p >Method for cooperative claiming of hardware. Will cause a panic if the channel is already claimed. Use of this method by libraries detects accidental configurations that would fail in unpredictable ways.</p>
 873 <dl class="params"><dt>Parameters</dt><dd>
 874   <table class="params">
 875     <tr><td class="paramname">channel</td><td>the dma channel </td></tr>
 876   </table>
 877   </dd>
 878 </dl>
 879
 880 </div>
 881 </div>
 882 <a id="ga655130988c1045bdf711135698adf321" name="ga655130988c1045bdf711135698adf321"></a>
 883 <h2 class="memtitle"><span class="permalink"><a href="#ga655130988c1045bdf711135698adf321">&#9670;&nbsp;</a></span>dma_channel_cleanup()</h2>
 884
 885 <div class="memitem">
 886 <div class="memproto">
 887       <table class="memname">
 888         <tr>
 889           <td class="memname">void dma_channel_cleanup </td>
 890           <td>(</td>
 891           <td class="paramtype">uint&#160;</td>
 892           <td class="paramname"><em>channel</em></td><td>)</td>
 893           <td></td>
 894         </tr>
 895       </table>
 896 </div><div class="memdoc">
 897
 898 <p>Performs DMA channel cleanup after use. </p>
 899 <p >This can be used to cleanup dma channels when they're no longer needed, such that they are in a clean state for reuse. IRQ's for the channel are disabled, any in flight-transfer is aborted and any outstanding interrupts are cleared. The channel is then clear to be reused for other purposes.</p>
 900 <div class="fragment"><div class="line"><span class="keywordflow">if</span> (dma_channel &gt;= 0) {</div>
 901 <div class="line">    <a class="code hl_function" href="group__hardware__dma.html#ga655130988c1045bdf711135698adf321">dma_channel_cleanup</a>(dma_channel);</div>
 902 <div class="line">    <a class="code hl_function" href="group__hardware__dma.html#gac50200739b88a2fd52316f4150533035">dma_channel_unclaim</a>(dma_channel);</div>
 903 <div class="line">    dma_channel = -1;</div>
 904 <div class="line">}</div>
 905 <div class="ttc" id="agroup__hardware__dma_html_ga655130988c1045bdf711135698adf321"><div class="ttname"><a href="group__hardware__dma.html#ga655130988c1045bdf711135698adf321">dma_channel_cleanup</a></div><div class="ttdeci">void dma_channel_cleanup(uint channel)</div><div class="ttdoc">Performs DMA channel cleanup after use.</div><div class="ttdef"><b>Definition:</b> dma.c:73</div></div>
 906 <div class="ttc" id="agroup__hardware__dma_html_gac50200739b88a2fd52316f4150533035"><div class="ttname"><a href="group__hardware__dma.html#gac50200739b88a2fd52316f4150533035">dma_channel_unclaim</a></div><div class="ttdeci">void dma_channel_unclaim(uint channel)</div><div class="ttdoc">Mark a dma channel as no longer used.</div><div class="ttdef"><b>Definition:</b> dma.c:34</div></div>
 907 </div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
 908   <table class="params">
 909     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
 910   </table>
 911   </dd>
 912 </dl>
 913
 914 </div>
 915 </div>
 916 <a id="ga971d077ac39b2d7f7c6b45e2ddc5d190" name="ga971d077ac39b2d7f7c6b45e2ddc5d190"></a>
 917 <h2 class="memtitle"><span class="permalink"><a href="#ga971d077ac39b2d7f7c6b45e2ddc5d190">&#9670;&nbsp;</a></span>dma_channel_configure()</h2>
 918
 919 <div class="memitem">
 920 <div class="memproto">
 921 <table class="mlabels">
 922   <tr>
 923   <td class="mlabels-left">
 924       <table class="memname">
 925         <tr>
 926           <td class="memname">static void dma_channel_configure </td>
 927           <td>(</td>
 928           <td class="paramtype">uint&#160;</td>
 929           <td class="paramname"><em>channel</em>, </td>
 930         </tr>
 931         <tr>
 932           <td class="paramkey"></td>
 933           <td></td>
 934           <td class="paramtype">const <a class="el" href="structdma__channel__config.html">dma_channel_config</a> *&#160;</td>
 935           <td class="paramname"><em>config</em>, </td>
 936         </tr>
 937         <tr>
 938           <td class="paramkey"></td>
 939           <td></td>
 940           <td class="paramtype">volatile void *&#160;</td>
 941           <td class="paramname"><em>write_addr</em>, </td>
 942         </tr>
 943         <tr>
 944           <td class="paramkey"></td>
 945           <td></td>
 946           <td class="paramtype">const volatile void *&#160;</td>
 947           <td class="paramname"><em>read_addr</em>, </td>
 948         </tr>
 949         <tr>
 950           <td class="paramkey"></td>
 951           <td></td>
 952           <td class="paramtype">uint&#160;</td>
 953           <td class="paramname"><em>transfer_count</em>, </td>
 954         </tr>
 955         <tr>
 956           <td class="paramkey"></td>
 957           <td></td>
 958           <td class="paramtype">bool&#160;</td>
 959           <td class="paramname"><em>trigger</em>&#160;</td>
 960         </tr>
 961         <tr>
 962           <td></td>
 963           <td>)</td>
 964           <td></td><td></td>
 965         </tr>
 966       </table>
 967   </td>
 968   <td class="mlabels-right">
 969 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
 970   </tr>
 971 </table>
 972 </div><div class="memdoc">
 973
 974 <p>Configure all DMA parameters and optionally start transfer. </p>
 975 <dl class="params"><dt>Parameters</dt><dd>
 976   <table class="params">
 977     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
 978     <tr><td class="paramname">config</td><td>Pointer to DMA config structure </td></tr>
 979     <tr><td class="paramname">write_addr</td><td>Initial write address </td></tr>
 980     <tr><td class="paramname">read_addr</td><td>Initial read address </td></tr>
 981     <tr><td class="paramname">transfer_count</td><td>Number of transfers to perform </td></tr>
 982     <tr><td class="paramname">trigger</td><td>True to start the transfer immediately </td></tr>
 983   </table>
 984   </dd>
 985 </dl>
 986
 987 </div>
 988 </div>
 989 <a id="gaa86e892c47b054d3c22fa39c001c7c23" name="gaa86e892c47b054d3c22fa39c001c7c23"></a>
 990 <h2 class="memtitle"><span class="permalink"><a href="#gaa86e892c47b054d3c22fa39c001c7c23">&#9670;&nbsp;</a></span>dma_channel_get_irq0_status()</h2>
 991
 992 <div class="memitem">
 993 <div class="memproto">
 994 <table class="mlabels">
 995   <tr>
 996   <td class="mlabels-left">
 997       <table class="memname">
 998         <tr>
 999           <td class="memname">static bool dma_channel_get_irq0_status </td>
1000           <td>(</td>
1001           <td class="paramtype">uint&#160;</td>
1002           <td class="paramname"><em>channel</em></td><td>)</td>
1003           <td></td>
1004         </tr>
1005       </table>
1006   </td>
1007   <td class="mlabels-right">
1008 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1009   </tr>
1010 </table>
1011 </div><div class="memdoc">
1012
1013 <p>Determine if a particular channel is a cause of DMA_IRQ_0. </p>
1014 <dl class="params"><dt>Parameters</dt><dd>
1015   <table class="params">
1016     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1017   </table>
1018   </dd>
1019 </dl>
1020 <dl class="section return"><dt>Returns</dt><dd>true if the channel is a cause of DMA_IRQ_0, false otherwise </dd></dl>
1021
1022 </div>
1023 </div>
1024 <a id="gaf61d25264e49058d20fb607dc1c40981" name="gaf61d25264e49058d20fb607dc1c40981"></a>
1025 <h2 class="memtitle"><span class="permalink"><a href="#gaf61d25264e49058d20fb607dc1c40981">&#9670;&nbsp;</a></span>dma_channel_get_irq1_status()</h2>
1026
1027 <div class="memitem">
1028 <div class="memproto">
1029 <table class="mlabels">
1030   <tr>
1031   <td class="mlabels-left">
1032       <table class="memname">
1033         <tr>
1034           <td class="memname">static bool dma_channel_get_irq1_status </td>
1035           <td>(</td>
1036           <td class="paramtype">uint&#160;</td>
1037           <td class="paramname"><em>channel</em></td><td>)</td>
1038           <td></td>
1039         </tr>
1040       </table>
1041   </td>
1042   <td class="mlabels-right">
1043 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1044   </tr>
1045 </table>
1046 </div><div class="memdoc">
1047
1048 <p>Determine if a particular channel is a cause of DMA_IRQ_1. </p>
1049 <dl class="params"><dt>Parameters</dt><dd>
1050   <table class="params">
1051     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1052   </table>
1053   </dd>
1054 </dl>
1055 <dl class="section return"><dt>Returns</dt><dd>true if the channel is a cause of DMA_IRQ_1, false otherwise </dd></dl>
1056
1057 </div>
1058 </div>
1059 <a id="gafbb5020a529ed6d39a11da88a6f313f2" name="gafbb5020a529ed6d39a11da88a6f313f2"></a>
1060 <h2 class="memtitle"><span class="permalink"><a href="#gafbb5020a529ed6d39a11da88a6f313f2">&#9670;&nbsp;</a></span>dma_channel_is_busy()</h2>
1061
1062 <div class="memitem">
1063 <div class="memproto">
1064 <table class="mlabels">
1065   <tr>
1066   <td class="mlabels-left">
1067       <table class="memname">
1068         <tr>
1069           <td class="memname">static bool dma_channel_is_busy </td>
1070           <td>(</td>
1071           <td class="paramtype">uint&#160;</td>
1072           <td class="paramname"><em>channel</em></td><td>)</td>
1073           <td></td>
1074         </tr>
1075       </table>
1076   </td>
1077   <td class="mlabels-right">
1078 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1079   </tr>
1080 </table>
1081 </div><div class="memdoc">
1082
1083 <p>Check if DMA channel is busy. </p>
1084 <dl class="params"><dt>Parameters</dt><dd>
1085   <table class="params">
1086     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1087   </table>
1088   </dd>
1089 </dl>
1090 <dl class="section return"><dt>Returns</dt><dd>true if the channel is currently busy </dd></dl>
1091
1092 </div>
1093 </div>
1094 <a id="ga9aadb81f53b979bde1c1a81164d1eff2" name="ga9aadb81f53b979bde1c1a81164d1eff2"></a>
1095 <h2 class="memtitle"><span class="permalink"><a href="#ga9aadb81f53b979bde1c1a81164d1eff2">&#9670;&nbsp;</a></span>dma_channel_is_claimed()</h2>
1096
1097 <div class="memitem">
1098 <div class="memproto">
1099       <table class="memname">
1100         <tr>
1101           <td class="memname">bool dma_channel_is_claimed </td>
1102           <td>(</td>
1103           <td class="paramtype">uint&#160;</td>
1104           <td class="paramname"><em>channel</em></td><td>)</td>
1105           <td></td>
1106         </tr>
1107       </table>
1108 </div><div class="memdoc">
1109
1110 <p>Determine if a dma channel is claimed. </p>
1111 <dl class="params"><dt>Parameters</dt><dd>
1112   <table class="params">
1113     <tr><td class="paramname">channel</td><td>the dma channel </td></tr>
1114   </table>
1115   </dd>
1116 </dl>
1117 <dl class="section return"><dt>Returns</dt><dd>true if the channel is claimed, false otherwise </dd></dl>
1118 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__hardware__dma.html#gae1b3c916746b3d2052f21b7dda34aab9" title="Mark a dma channel as used.">dma_channel_claim</a> </dd>
1119 <dd>
1120 dma_channel_claim_mask </dd></dl>
1121
1122 </div>
1123 </div>
1124 <a id="ga7449b659efb178a408f42f7f8f7b02f9" name="ga7449b659efb178a408f42f7f8f7b02f9"></a>
1125 <h2 class="memtitle"><span class="permalink"><a href="#ga7449b659efb178a408f42f7f8f7b02f9">&#9670;&nbsp;</a></span>dma_channel_set_config()</h2>
1126
1127 <div class="memitem">
1128 <div class="memproto">
1129 <table class="mlabels">
1130   <tr>
1131   <td class="mlabels-left">
1132       <table class="memname">
1133         <tr>
1134           <td class="memname">static void dma_channel_set_config </td>
1135           <td>(</td>
1136           <td class="paramtype">uint&#160;</td>
1137           <td class="paramname"><em>channel</em>, </td>
1138         </tr>
1139         <tr>
1140           <td class="paramkey"></td>
1141           <td></td>
1142           <td class="paramtype">const <a class="el" href="structdma__channel__config.html">dma_channel_config</a> *&#160;</td>
1143           <td class="paramname"><em>config</em>, </td>
1144         </tr>
1145         <tr>
1146           <td class="paramkey"></td>
1147           <td></td>
1148           <td class="paramtype">bool&#160;</td>
1149           <td class="paramname"><em>trigger</em>&#160;</td>
1150         </tr>
1151         <tr>
1152           <td></td>
1153           <td>)</td>
1154           <td></td><td></td>
1155         </tr>
1156       </table>
1157   </td>
1158   <td class="mlabels-right">
1159 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1160   </tr>
1161 </table>
1162 </div><div class="memdoc">
1163
1164 <p>Set a channel configuration. </p>
1165 <dl class="params"><dt>Parameters</dt><dd>
1166   <table class="params">
1167     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1168     <tr><td class="paramname">config</td><td>Pointer to a config structure with required configuration </td></tr>
1169     <tr><td class="paramname">trigger</td><td>True to trigger the transfer immediately </td></tr>
1170   </table>
1171   </dd>
1172 </dl>
1173
1174 </div>
1175 </div>
1176 <a id="gaf60011d46676c87b7139f37188eaa4b9" name="gaf60011d46676c87b7139f37188eaa4b9"></a>
1177 <h2 class="memtitle"><span class="permalink"><a href="#gaf60011d46676c87b7139f37188eaa4b9">&#9670;&nbsp;</a></span>dma_channel_set_irq0_enabled()</h2>
1178
1179 <div class="memitem">
1180 <div class="memproto">
1181 <table class="mlabels">
1182   <tr>
1183   <td class="mlabels-left">
1184       <table class="memname">
1185         <tr>
1186           <td class="memname">static void dma_channel_set_irq0_enabled </td>
1187           <td>(</td>
1188           <td class="paramtype">uint&#160;</td>
1189           <td class="paramname"><em>channel</em>, </td>
1190         </tr>
1191         <tr>
1192           <td class="paramkey"></td>
1193           <td></td>
1194           <td class="paramtype">bool&#160;</td>
1195           <td class="paramname"><em>enabled</em>&#160;</td>
1196         </tr>
1197         <tr>
1198           <td></td>
1199           <td>)</td>
1200           <td></td><td></td>
1201         </tr>
1202       </table>
1203   </td>
1204   <td class="mlabels-right">
1205 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1206   </tr>
1207 </table>
1208 </div><div class="memdoc">
1209
1210 <p>Enable single DMA channel's interrupt via DMA_IRQ_0. </p>
1211 <dl class="params"><dt>Parameters</dt><dd>
1212   <table class="params">
1213     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1214     <tr><td class="paramname">enabled</td><td>true to enable interrupt 0 on specified channel, false to disable. </td></tr>
1215   </table>
1216   </dd>
1217 </dl>
1218
1219 </div>
1220 </div>
1221 <a id="ga4f9415c8f77ff0bacedf5a138a88d76f" name="ga4f9415c8f77ff0bacedf5a138a88d76f"></a>
1222 <h2 class="memtitle"><span class="permalink"><a href="#ga4f9415c8f77ff0bacedf5a138a88d76f">&#9670;&nbsp;</a></span>dma_channel_set_irq1_enabled()</h2>
1223
1224 <div class="memitem">
1225 <div class="memproto">
1226 <table class="mlabels">
1227   <tr>
1228   <td class="mlabels-left">
1229       <table class="memname">
1230         <tr>
1231           <td class="memname">static void dma_channel_set_irq1_enabled </td>
1232           <td>(</td>
1233           <td class="paramtype">uint&#160;</td>
1234           <td class="paramname"><em>channel</em>, </td>
1235         </tr>
1236         <tr>
1237           <td class="paramkey"></td>
1238           <td></td>
1239           <td class="paramtype">bool&#160;</td>
1240           <td class="paramname"><em>enabled</em>&#160;</td>
1241         </tr>
1242         <tr>
1243           <td></td>
1244           <td>)</td>
1245           <td></td><td></td>
1246         </tr>
1247       </table>
1248   </td>
1249   <td class="mlabels-right">
1250 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1251   </tr>
1252 </table>
1253 </div><div class="memdoc">
1254
1255 <p>Enable single DMA channel's interrupt via DMA_IRQ_1. </p>
1256 <dl class="params"><dt>Parameters</dt><dd>
1257   <table class="params">
1258     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1259     <tr><td class="paramname">enabled</td><td>true to enable interrupt 1 on specified channel, false to disable. </td></tr>
1260   </table>
1261   </dd>
1262 </dl>
1263
1264 </div>
1265 </div>
1266 <a id="gabf6f6ffe56fa42dcb105032f110589ae" name="gabf6f6ffe56fa42dcb105032f110589ae"></a>
1267 <h2 class="memtitle"><span class="permalink"><a href="#gabf6f6ffe56fa42dcb105032f110589ae">&#9670;&nbsp;</a></span>dma_channel_set_read_addr()</h2>
1268
1269 <div class="memitem">
1270 <div class="memproto">
1271 <table class="mlabels">
1272   <tr>
1273   <td class="mlabels-left">
1274       <table class="memname">
1275         <tr>
1276           <td class="memname">static void dma_channel_set_read_addr </td>
1277           <td>(</td>
1278           <td class="paramtype">uint&#160;</td>
1279           <td class="paramname"><em>channel</em>, </td>
1280         </tr>
1281         <tr>
1282           <td class="paramkey"></td>
1283           <td></td>
1284           <td class="paramtype">const volatile void *&#160;</td>
1285           <td class="paramname"><em>read_addr</em>, </td>
1286         </tr>
1287         <tr>
1288           <td class="paramkey"></td>
1289           <td></td>
1290           <td class="paramtype">bool&#160;</td>
1291           <td class="paramname"><em>trigger</em>&#160;</td>
1292         </tr>
1293         <tr>
1294           <td></td>
1295           <td>)</td>
1296           <td></td><td></td>
1297         </tr>
1298       </table>
1299   </td>
1300   <td class="mlabels-right">
1301 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1302   </tr>
1303 </table>
1304 </div><div class="memdoc">
1305
1306 <p>Set the DMA initial read address. </p>
1307 <dl class="params"><dt>Parameters</dt><dd>
1308   <table class="params">
1309     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1310     <tr><td class="paramname">read_addr</td><td>Initial read address of transfer. </td></tr>
1311     <tr><td class="paramname">trigger</td><td>True to start the transfer immediately </td></tr>
1312   </table>
1313   </dd>
1314 </dl>
1315
1316 </div>
1317 </div>
1318 <a id="ga16c0e08eda636f13053d8c8b0f81e821" name="ga16c0e08eda636f13053d8c8b0f81e821"></a>
1319 <h2 class="memtitle"><span class="permalink"><a href="#ga16c0e08eda636f13053d8c8b0f81e821">&#9670;&nbsp;</a></span>dma_channel_set_trans_count()</h2>
1320
1321 <div class="memitem">
1322 <div class="memproto">
1323 <table class="mlabels">
1324   <tr>
1325   <td class="mlabels-left">
1326       <table class="memname">
1327         <tr>
1328           <td class="memname">static void dma_channel_set_trans_count </td>
1329           <td>(</td>
1330           <td class="paramtype">uint&#160;</td>
1331           <td class="paramname"><em>channel</em>, </td>
1332         </tr>
1333         <tr>
1334           <td class="paramkey"></td>
1335           <td></td>
1336           <td class="paramtype">uint32_t&#160;</td>
1337           <td class="paramname"><em>trans_count</em>, </td>
1338         </tr>
1339         <tr>
1340           <td class="paramkey"></td>
1341           <td></td>
1342           <td class="paramtype">bool&#160;</td>
1343           <td class="paramname"><em>trigger</em>&#160;</td>
1344         </tr>
1345         <tr>
1346           <td></td>
1347           <td>)</td>
1348           <td></td><td></td>
1349         </tr>
1350       </table>
1351   </td>
1352   <td class="mlabels-right">
1353 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1354   </tr>
1355 </table>
1356 </div><div class="memdoc">
1357
1358 <p>Set the number of bus transfers the channel will do. </p>
1359 <dl class="params"><dt>Parameters</dt><dd>
1360   <table class="params">
1361     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1362     <tr><td class="paramname">trans_count</td><td>The number of transfers (not NOT bytes, see channel_config_set_transfer_data_size) </td></tr>
1363     <tr><td class="paramname">trigger</td><td>True to start the transfer immediately </td></tr>
1364   </table>
1365   </dd>
1366 </dl>
1367
1368 </div>
1369 </div>
1370 <a id="gaf0156609fe51c07d07118b2aeb4e9ae6" name="gaf0156609fe51c07d07118b2aeb4e9ae6"></a>
1371 <h2 class="memtitle"><span class="permalink"><a href="#gaf0156609fe51c07d07118b2aeb4e9ae6">&#9670;&nbsp;</a></span>dma_channel_set_write_addr()</h2>
1372
1373 <div class="memitem">
1374 <div class="memproto">
1375 <table class="mlabels">
1376   <tr>
1377   <td class="mlabels-left">
1378       <table class="memname">
1379         <tr>
1380           <td class="memname">static void dma_channel_set_write_addr </td>
1381           <td>(</td>
1382           <td class="paramtype">uint&#160;</td>
1383           <td class="paramname"><em>channel</em>, </td>
1384         </tr>
1385         <tr>
1386           <td class="paramkey"></td>
1387           <td></td>
1388           <td class="paramtype">volatile void *&#160;</td>
1389           <td class="paramname"><em>write_addr</em>, </td>
1390         </tr>
1391         <tr>
1392           <td class="paramkey"></td>
1393           <td></td>
1394           <td class="paramtype">bool&#160;</td>
1395           <td class="paramname"><em>trigger</em>&#160;</td>
1396         </tr>
1397         <tr>
1398           <td></td>
1399           <td>)</td>
1400           <td></td><td></td>
1401         </tr>
1402       </table>
1403   </td>
1404   <td class="mlabels-right">
1405 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1406   </tr>
1407 </table>
1408 </div><div class="memdoc">
1409
1410 <p>Set the DMA initial write address. </p>
1411 <dl class="params"><dt>Parameters</dt><dd>
1412   <table class="params">
1413     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1414     <tr><td class="paramname">write_addr</td><td>Initial write address of transfer. </td></tr>
1415     <tr><td class="paramname">trigger</td><td>True to start the transfer immediately </td></tr>
1416   </table>
1417   </dd>
1418 </dl>
1419
1420 </div>
1421 </div>
1422 <a id="ga355720e02713c7324b540efc6f632366" name="ga355720e02713c7324b540efc6f632366"></a>
1423 <h2 class="memtitle"><span class="permalink"><a href="#ga355720e02713c7324b540efc6f632366">&#9670;&nbsp;</a></span>dma_channel_start()</h2>
1424
1425 <div class="memitem">
1426 <div class="memproto">
1427 <table class="mlabels">
1428   <tr>
1429   <td class="mlabels-left">
1430       <table class="memname">
1431         <tr>
1432           <td class="memname">static void dma_channel_start </td>
1433           <td>(</td>
1434           <td class="paramtype">uint&#160;</td>
1435           <td class="paramname"><em>channel</em></td><td>)</td>
1436           <td></td>
1437         </tr>
1438       </table>
1439   </td>
1440   <td class="mlabels-right">
1441 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1442   </tr>
1443 </table>
1444 </div><div class="memdoc">
1445
1446 <p>Start a single DMA channel. </p>
1447 <dl class="params"><dt>Parameters</dt><dd>
1448   <table class="params">
1449     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1450   </table>
1451   </dd>
1452 </dl>
1453
1454 </div>
1455 </div>
1456 <a id="gabf64c461a405a8114591105d9dc53575" name="gabf64c461a405a8114591105d9dc53575"></a>
1457 <h2 class="memtitle"><span class="permalink"><a href="#gabf64c461a405a8114591105d9dc53575">&#9670;&nbsp;</a></span>dma_channel_transfer_from_buffer_now()</h2>
1458
1459 <div class="memitem">
1460 <div class="memproto">
1461 <table class="mlabels">
1462   <tr>
1463   <td class="mlabels-left">
1464       <table class="memname">
1465         <tr>
1466           <td class="memname">static void dma_channel_transfer_from_buffer_now </td>
1467           <td>(</td>
1468           <td class="paramtype">uint&#160;</td>
1469           <td class="paramname"><em>channel</em>, </td>
1470         </tr>
1471         <tr>
1472           <td class="paramkey"></td>
1473           <td></td>
1474           <td class="paramtype">const volatile void *&#160;</td>
1475           <td class="paramname"><em>read_addr</em>, </td>
1476         </tr>
1477         <tr>
1478           <td class="paramkey"></td>
1479           <td></td>
1480           <td class="paramtype">uint32_t&#160;</td>
1481           <td class="paramname"><em>transfer_count</em>&#160;</td>
1482         </tr>
1483         <tr>
1484           <td></td>
1485           <td>)</td>
1486           <td></td><td></td>
1487         </tr>
1488       </table>
1489   </td>
1490   <td class="mlabels-right">
1491 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1492   </tr>
1493 </table>
1494 </div><div class="memdoc">
1495
1496 <p>Start a DMA transfer from a buffer immediately. </p>
1497 <dl class="params"><dt>Parameters</dt><dd>
1498   <table class="params">
1499     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1500     <tr><td class="paramname">read_addr</td><td>Sets the initial read address </td></tr>
1501     <tr><td class="paramname">transfer_count</td><td>Number of transfers to make. Not bytes, but the number of transfers of <a class="el" href="group__channel__config.html#gad1a02fcee90d21f133460006b025bac0" title="Set the size of each DMA bus transfer in a channel configuration object.">channel_config_set_transfer_data_size()</a> to be sent. </td></tr>
1502   </table>
1503   </dd>
1504 </dl>
1505
1506 </div>
1507 </div>
1508 <a id="ga9110135d8161fc268d87dfb040d0f854" name="ga9110135d8161fc268d87dfb040d0f854"></a>
1509 <h2 class="memtitle"><span class="permalink"><a href="#ga9110135d8161fc268d87dfb040d0f854">&#9670;&nbsp;</a></span>dma_channel_transfer_to_buffer_now()</h2>
1510
1511 <div class="memitem">
1512 <div class="memproto">
1513 <table class="mlabels">
1514   <tr>
1515   <td class="mlabels-left">
1516       <table class="memname">
1517         <tr>
1518           <td class="memname">static void dma_channel_transfer_to_buffer_now </td>
1519           <td>(</td>
1520           <td class="paramtype">uint&#160;</td>
1521           <td class="paramname"><em>channel</em>, </td>
1522         </tr>
1523         <tr>
1524           <td class="paramkey"></td>
1525           <td></td>
1526           <td class="paramtype">volatile void *&#160;</td>
1527           <td class="paramname"><em>write_addr</em>, </td>
1528         </tr>
1529         <tr>
1530           <td class="paramkey"></td>
1531           <td></td>
1532           <td class="paramtype">uint32_t&#160;</td>
1533           <td class="paramname"><em>transfer_count</em>&#160;</td>
1534         </tr>
1535         <tr>
1536           <td></td>
1537           <td>)</td>
1538           <td></td><td></td>
1539         </tr>
1540       </table>
1541   </td>
1542   <td class="mlabels-right">
1543 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1544   </tr>
1545 </table>
1546 </div><div class="memdoc">
1547
1548 <p>Start a DMA transfer to a buffer immediately. </p>
1549 <dl class="params"><dt>Parameters</dt><dd>
1550   <table class="params">
1551     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1552     <tr><td class="paramname">write_addr</td><td>Sets the initial write address </td></tr>
1553     <tr><td class="paramname">transfer_count</td><td>Number of transfers to make. Not bytes, but the number of transfers of <a class="el" href="group__channel__config.html#gad1a02fcee90d21f133460006b025bac0" title="Set the size of each DMA bus transfer in a channel configuration object.">channel_config_set_transfer_data_size()</a> to be sent. </td></tr>
1554   </table>
1555   </dd>
1556 </dl>
1557
1558 </div>
1559 </div>
1560 <a id="gac50200739b88a2fd52316f4150533035" name="gac50200739b88a2fd52316f4150533035"></a>
1561 <h2 class="memtitle"><span class="permalink"><a href="#gac50200739b88a2fd52316f4150533035">&#9670;&nbsp;</a></span>dma_channel_unclaim()</h2>
1562
1563 <div class="memitem">
1564 <div class="memproto">
1565       <table class="memname">
1566         <tr>
1567           <td class="memname">void dma_channel_unclaim </td>
1568           <td>(</td>
1569           <td class="paramtype">uint&#160;</td>
1570           <td class="paramname"><em>channel</em></td><td>)</td>
1571           <td></td>
1572         </tr>
1573       </table>
1574 </div><div class="memdoc">
1575
1576 <p>Mark a dma channel as no longer used. </p>
1577 <dl class="params"><dt>Parameters</dt><dd>
1578   <table class="params">
1579     <tr><td class="paramname">channel</td><td>the dma channel to release </td></tr>
1580   </table>
1581   </dd>
1582 </dl>
1583
1584 </div>
1585 </div>
1586 <a id="gab57c68850b8e6ed1623de75ad611db62" name="gab57c68850b8e6ed1623de75ad611db62"></a>
1587 <h2 class="memtitle"><span class="permalink"><a href="#gab57c68850b8e6ed1623de75ad611db62">&#9670;&nbsp;</a></span>dma_channel_wait_for_finish_blocking()</h2>
1588
1589 <div class="memitem">
1590 <div class="memproto">
1591 <table class="mlabels">
1592   <tr>
1593   <td class="mlabels-left">
1594       <table class="memname">
1595         <tr>
1596           <td class="memname">static void dma_channel_wait_for_finish_blocking </td>
1597           <td>(</td>
1598           <td class="paramtype">uint&#160;</td>
1599           <td class="paramname"><em>channel</em></td><td>)</td>
1600           <td></td>
1601         </tr>
1602       </table>
1603   </td>
1604   <td class="mlabels-right">
1605 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1606   </tr>
1607 </table>
1608 </div><div class="memdoc">
1609
1610 <p>Wait for a DMA channel transfer to complete. </p>
1611 <dl class="params"><dt>Parameters</dt><dd>
1612   <table class="params">
1613     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1614   </table>
1615   </dd>
1616 </dl>
1617
1618 </div>
1619 </div>
1620 <a id="gaa430bc53dc2b36d727ad976f6348c8b3" name="gaa430bc53dc2b36d727ad976f6348c8b3"></a>
1621 <h2 class="memtitle"><span class="permalink"><a href="#gaa430bc53dc2b36d727ad976f6348c8b3">&#9670;&nbsp;</a></span>dma_claim_mask()</h2>
1622
1623 <div class="memitem">
1624 <div class="memproto">
1625       <table class="memname">
1626         <tr>
1627           <td class="memname">void dma_claim_mask </td>
1628           <td>(</td>
1629           <td class="paramtype">uint32_t&#160;</td>
1630           <td class="paramname"><em>channel_mask</em></td><td>)</td>
1631           <td></td>
1632         </tr>
1633       </table>
1634 </div><div class="memdoc">
1635
1636 <p>Mark multiple dma channels as used. </p>
1637 <p >Method for cooperative claiming of hardware. Will cause a panic if any of the channels are already claimed. Use of this method by libraries detects accidental configurations that would fail in unpredictable ways.</p>
1638 <dl class="params"><dt>Parameters</dt><dd>
1639   <table class="params">
1640     <tr><td class="paramname">channel_mask</td><td>Bitfield of all required channels to claim (bit 0 == channel 0, bit 1 == channel 1 etc) </td></tr>
1641   </table>
1642   </dd>
1643 </dl>
1644
1645 </div>
1646 </div>
1647 <a id="ga4b0a6680795b9c9ed787362a8a057206" name="ga4b0a6680795b9c9ed787362a8a057206"></a>
1648 <h2 class="memtitle"><span class="permalink"><a href="#ga4b0a6680795b9c9ed787362a8a057206">&#9670;&nbsp;</a></span>dma_claim_unused_channel()</h2>
1649
1650 <div class="memitem">
1651 <div class="memproto">
1652       <table class="memname">
1653         <tr>
1654           <td class="memname">int dma_claim_unused_channel </td>
1655           <td>(</td>
1656           <td class="paramtype">bool&#160;</td>
1657           <td class="paramname"><em>required</em></td><td>)</td>
1658           <td></td>
1659         </tr>
1660       </table>
1661 </div><div class="memdoc">
1662
1663 <p>Claim a free dma channel. </p>
1664 <dl class="params"><dt>Parameters</dt><dd>
1665   <table class="params">
1666     <tr><td class="paramname">required</td><td>if true the function will panic if none are available </td></tr>
1667   </table>
1668   </dd>
1669 </dl>
1670 <dl class="section return"><dt>Returns</dt><dd>the dma channel number or -1 if required was false, and none were free </dd></dl>
1671
1672 </div>
1673 </div>
1674 <a id="ga2f218b6acd97e09430afbb74172bd570" name="ga2f218b6acd97e09430afbb74172bd570"></a>
1675 <h2 class="memtitle"><span class="permalink"><a href="#ga2f218b6acd97e09430afbb74172bd570">&#9670;&nbsp;</a></span>dma_claim_unused_timer()</h2>
1676
1677 <div class="memitem">
1678 <div class="memproto">
1679       <table class="memname">
1680         <tr>
1681           <td class="memname">int dma_claim_unused_timer </td>
1682           <td>(</td>
1683           <td class="paramtype">bool&#160;</td>
1684           <td class="paramname"><em>required</em></td><td>)</td>
1685           <td></td>
1686         </tr>
1687       </table>
1688 </div><div class="memdoc">
1689
1690 <p>Claim a free dma timer. </p>
1691 <dl class="params"><dt>Parameters</dt><dd>
1692   <table class="params">
1693     <tr><td class="paramname">required</td><td>if true the function will panic if none are available </td></tr>
1694   </table>
1695   </dd>
1696 </dl>
1697 <dl class="section return"><dt>Returns</dt><dd>the dma timer number or -1 if required was false, and none were free </dd></dl>
1698
1699 </div>
1700 </div>
1701 <a id="ga5da1507764272564a75939e2cf38fa9a" name="ga5da1507764272564a75939e2cf38fa9a"></a>
1702 <h2 class="memtitle"><span class="permalink"><a href="#ga5da1507764272564a75939e2cf38fa9a">&#9670;&nbsp;</a></span>dma_get_irq_num()</h2>
1703
1704 <div class="memitem">
1705 <div class="memproto">
1706 <table class="mlabels">
1707   <tr>
1708   <td class="mlabels-left">
1709       <table class="memname">
1710         <tr>
1711           <td class="memname">static int dma_get_irq_num </td>
1712           <td>(</td>
1713           <td class="paramtype">uint&#160;</td>
1714           <td class="paramname"><em>irq_index</em></td><td>)</td>
1715           <td></td>
1716         </tr>
1717       </table>
1718   </td>
1719   <td class="mlabels-right">
1720 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1721   </tr>
1722 </table>
1723 </div><div class="memdoc">
1724
1725 <p>Return DMA_IRQ_&lt;irqn&gt; </p>
1726 <dl class="params"><dt>Parameters</dt><dd>
1727   <table class="params">
1728     <tr><td class="paramname">irq_index</td><td>0 the DMA irq index </td></tr>
1729   </table>
1730   </dd>
1731 </dl>
1732 <dl class="section return"><dt>Returns</dt><dd>The irq_num_to use for DMA </dd></dl>
1733
1734 </div>
1735 </div>
1736 <a id="ga75ef6881795fd1760fe813f9e0a79223" name="ga75ef6881795fd1760fe813f9e0a79223"></a>
1737 <h2 class="memtitle"><span class="permalink"><a href="#ga75ef6881795fd1760fe813f9e0a79223">&#9670;&nbsp;</a></span>dma_get_timer_dreq()</h2>
1738
1739 <div class="memitem">
1740 <div class="memproto">
1741 <table class="mlabels">
1742   <tr>
1743   <td class="mlabels-left">
1744       <table class="memname">
1745         <tr>
1746           <td class="memname">static uint dma_get_timer_dreq </td>
1747           <td>(</td>
1748           <td class="paramtype">uint&#160;</td>
1749           <td class="paramname"><em>timer_num</em></td><td>)</td>
1750           <td></td>
1751         </tr>
1752       </table>
1753   </td>
1754   <td class="mlabels-right">
1755 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1756   </tr>
1757 </table>
1758 </div><div class="memdoc">
1759
1760 <p>Return the DREQ number for a given DMA timer. </p>
1761 <dl class="params"><dt>Parameters</dt><dd>
1762   <table class="params">
1763     <tr><td class="paramname">timer_num</td><td>DMA timer number 0-3 </td></tr>
1764   </table>
1765   </dd>
1766 </dl>
1767
1768 </div>
1769 </div>
1770 <a id="gad0e8e022fbe67b80c16912254526fada" name="gad0e8e022fbe67b80c16912254526fada"></a>
1771 <h2 class="memtitle"><span class="permalink"><a href="#gad0e8e022fbe67b80c16912254526fada">&#9670;&nbsp;</a></span>dma_irqn_acknowledge_channel()</h2>
1772
1773 <div class="memitem">
1774 <div class="memproto">
1775 <table class="mlabels">
1776   <tr>
1777   <td class="mlabels-left">
1778       <table class="memname">
1779         <tr>
1780           <td class="memname">static void dma_irqn_acknowledge_channel </td>
1781           <td>(</td>
1782           <td class="paramtype">uint&#160;</td>
1783           <td class="paramname"><em>irq_index</em>, </td>
1784         </tr>
1785         <tr>
1786           <td class="paramkey"></td>
1787           <td></td>
1788           <td class="paramtype">uint&#160;</td>
1789           <td class="paramname"><em>channel</em>&#160;</td>
1790         </tr>
1791         <tr>
1792           <td></td>
1793           <td>)</td>
1794           <td></td><td></td>
1795         </tr>
1796       </table>
1797   </td>
1798   <td class="mlabels-right">
1799 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1800   </tr>
1801 </table>
1802 </div><div class="memdoc">
1803
1804 <p>Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N. </p>
1805 <dl class="params"><dt>Parameters</dt><dd>
1806   <table class="params">
1807     <tr><td class="paramname">irq_index</td><td>the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 </td></tr>
1808     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1809   </table>
1810   </dd>
1811 </dl>
1812
1813 </div>
1814 </div>
1815 <a id="ga43f1fe10d5eb241788f72ad11599fc11" name="ga43f1fe10d5eb241788f72ad11599fc11"></a>
1816 <h2 class="memtitle"><span class="permalink"><a href="#ga43f1fe10d5eb241788f72ad11599fc11">&#9670;&nbsp;</a></span>dma_irqn_get_channel_status()</h2>
1817
1818 <div class="memitem">
1819 <div class="memproto">
1820 <table class="mlabels">
1821   <tr>
1822   <td class="mlabels-left">
1823       <table class="memname">
1824         <tr>
1825           <td class="memname">static bool dma_irqn_get_channel_status </td>
1826           <td>(</td>
1827           <td class="paramtype">uint&#160;</td>
1828           <td class="paramname"><em>irq_index</em>, </td>
1829         </tr>
1830         <tr>
1831           <td class="paramkey"></td>
1832           <td></td>
1833           <td class="paramtype">uint&#160;</td>
1834           <td class="paramname"><em>channel</em>&#160;</td>
1835         </tr>
1836         <tr>
1837           <td></td>
1838           <td>)</td>
1839           <td></td><td></td>
1840         </tr>
1841       </table>
1842   </td>
1843   <td class="mlabels-right">
1844 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1845   </tr>
1846 </table>
1847 </div><div class="memdoc">
1848
1849 <p>Determine if a particular channel is a cause of DMA_IRQ_N. </p>
1850 <dl class="params"><dt>Parameters</dt><dd>
1851   <table class="params">
1852     <tr><td class="paramname">irq_index</td><td>the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 </td></tr>
1853     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1854   </table>
1855   </dd>
1856 </dl>
1857 <dl class="section return"><dt>Returns</dt><dd>true if the channel is a cause of the DMA_IRQ_N, false otherwise </dd></dl>
1858
1859 </div>
1860 </div>
1861 <a id="ga6fefe19fa5539580315de923e42131d3" name="ga6fefe19fa5539580315de923e42131d3"></a>
1862 <h2 class="memtitle"><span class="permalink"><a href="#ga6fefe19fa5539580315de923e42131d3">&#9670;&nbsp;</a></span>dma_irqn_set_channel_enabled()</h2>
1863
1864 <div class="memitem">
1865 <div class="memproto">
1866 <table class="mlabels">
1867   <tr>
1868   <td class="mlabels-left">
1869       <table class="memname">
1870         <tr>
1871           <td class="memname">static void dma_irqn_set_channel_enabled </td>
1872           <td>(</td>
1873           <td class="paramtype">uint&#160;</td>
1874           <td class="paramname"><em>irq_index</em>, </td>
1875         </tr>
1876         <tr>
1877           <td class="paramkey"></td>
1878           <td></td>
1879           <td class="paramtype">uint&#160;</td>
1880           <td class="paramname"><em>channel</em>, </td>
1881         </tr>
1882         <tr>
1883           <td class="paramkey"></td>
1884           <td></td>
1885           <td class="paramtype">bool&#160;</td>
1886           <td class="paramname"><em>enabled</em>&#160;</td>
1887         </tr>
1888         <tr>
1889           <td></td>
1890           <td>)</td>
1891           <td></td><td></td>
1892         </tr>
1893       </table>
1894   </td>
1895   <td class="mlabels-right">
1896 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1897   </tr>
1898 </table>
1899 </div><div class="memdoc">
1900
1901 <p>Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1. </p>
1902 <dl class="params"><dt>Parameters</dt><dd>
1903   <table class="params">
1904     <tr><td class="paramname">irq_index</td><td>the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 </td></tr>
1905     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
1906     <tr><td class="paramname">enabled</td><td>true to enable interrupt via irq_index for specified channel, false to disable. </td></tr>
1907   </table>
1908   </dd>
1909 </dl>
1910
1911 </div>
1912 </div>
1913 <a id="ga720f2335e93b0e53e28959566ca18f3e" name="ga720f2335e93b0e53e28959566ca18f3e"></a>
1914 <h2 class="memtitle"><span class="permalink"><a href="#ga720f2335e93b0e53e28959566ca18f3e">&#9670;&nbsp;</a></span>dma_irqn_set_channel_mask_enabled()</h2>
1915
1916 <div class="memitem">
1917 <div class="memproto">
1918 <table class="mlabels">
1919   <tr>
1920   <td class="mlabels-left">
1921       <table class="memname">
1922         <tr>
1923           <td class="memname">static void dma_irqn_set_channel_mask_enabled </td>
1924           <td>(</td>
1925           <td class="paramtype">uint&#160;</td>
1926           <td class="paramname"><em>irq_index</em>, </td>
1927         </tr>
1928         <tr>
1929           <td class="paramkey"></td>
1930           <td></td>
1931           <td class="paramtype">uint32_t&#160;</td>
1932           <td class="paramname"><em>channel_mask</em>, </td>
1933         </tr>
1934         <tr>
1935           <td class="paramkey"></td>
1936           <td></td>
1937           <td class="paramtype">bool&#160;</td>
1938           <td class="paramname"><em>enabled</em>&#160;</td>
1939         </tr>
1940         <tr>
1941           <td></td>
1942           <td>)</td>
1943           <td></td><td></td>
1944         </tr>
1945       </table>
1946   </td>
1947   <td class="mlabels-right">
1948 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1949   </tr>
1950 </table>
1951 </div><div class="memdoc">
1952
1953 <p>Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1. </p>
1954 <dl class="params"><dt>Parameters</dt><dd>
1955   <table class="params">
1956     <tr><td class="paramname">irq_index</td><td>the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 </td></tr>
1957     <tr><td class="paramname">channel_mask</td><td>Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. </td></tr>
1958     <tr><td class="paramname">enabled</td><td>true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. </td></tr>
1959   </table>
1960   </dd>
1961 </dl>
1962
1963 </div>
1964 </div>
1965 <a id="gad5c1ac22e0b4d9b831912fbb95460be4" name="gad5c1ac22e0b4d9b831912fbb95460be4"></a>
1966 <h2 class="memtitle"><span class="permalink"><a href="#gad5c1ac22e0b4d9b831912fbb95460be4">&#9670;&nbsp;</a></span>dma_set_irq0_channel_mask_enabled()</h2>
1967
1968 <div class="memitem">
1969 <div class="memproto">
1970 <table class="mlabels">
1971   <tr>
1972   <td class="mlabels-left">
1973       <table class="memname">
1974         <tr>
1975           <td class="memname">static void dma_set_irq0_channel_mask_enabled </td>
1976           <td>(</td>
1977           <td class="paramtype">uint32_t&#160;</td>
1978           <td class="paramname"><em>channel_mask</em>, </td>
1979         </tr>
1980         <tr>
1981           <td class="paramkey"></td>
1982           <td></td>
1983           <td class="paramtype">bool&#160;</td>
1984           <td class="paramname"><em>enabled</em>&#160;</td>
1985         </tr>
1986         <tr>
1987           <td></td>
1988           <td>)</td>
1989           <td></td><td></td>
1990         </tr>
1991       </table>
1992   </td>
1993   <td class="mlabels-right">
1994 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
1995   </tr>
1996 </table>
1997 </div><div class="memdoc">
1998
1999 <p>Enable multiple DMA channels' interrupts via DMA_IRQ_0. </p>
2000 <dl class="params"><dt>Parameters</dt><dd>
2001   <table class="params">
2002     <tr><td class="paramname">channel_mask</td><td>Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. </td></tr>
2003     <tr><td class="paramname">enabled</td><td>true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. </td></tr>
2004   </table>
2005   </dd>
2006 </dl>
2007
2008 </div>
2009 </div>
2010 <a id="gaaa20edc55a2cc4977d24bdb487a22aa5" name="gaaa20edc55a2cc4977d24bdb487a22aa5"></a>
2011 <h2 class="memtitle"><span class="permalink"><a href="#gaaa20edc55a2cc4977d24bdb487a22aa5">&#9670;&nbsp;</a></span>dma_set_irq1_channel_mask_enabled()</h2>
2012
2013 <div class="memitem">
2014 <div class="memproto">
2015 <table class="mlabels">
2016   <tr>
2017   <td class="mlabels-left">
2018       <table class="memname">
2019         <tr>
2020           <td class="memname">static void dma_set_irq1_channel_mask_enabled </td>
2021           <td>(</td>
2022           <td class="paramtype">uint32_t&#160;</td>
2023           <td class="paramname"><em>channel_mask</em>, </td>
2024         </tr>
2025         <tr>
2026           <td class="paramkey"></td>
2027           <td></td>
2028           <td class="paramtype">bool&#160;</td>
2029           <td class="paramname"><em>enabled</em>&#160;</td>
2030         </tr>
2031         <tr>
2032           <td></td>
2033           <td>)</td>
2034           <td></td><td></td>
2035         </tr>
2036       </table>
2037   </td>
2038   <td class="mlabels-right">
2039 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2040   </tr>
2041 </table>
2042 </div><div class="memdoc">
2043
2044 <p>Enable multiple DMA channels' interrupts via DMA_IRQ_1. </p>
2045 <dl class="params"><dt>Parameters</dt><dd>
2046   <table class="params">
2047     <tr><td class="paramname">channel_mask</td><td>Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. </td></tr>
2048     <tr><td class="paramname">enabled</td><td>true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. </td></tr>
2049   </table>
2050   </dd>
2051 </dl>
2052
2053 </div>
2054 </div>
2055 <a id="ga078c3c80d5637850ec64e8f5ad5ce0c2" name="ga078c3c80d5637850ec64e8f5ad5ce0c2"></a>
2056 <h2 class="memtitle"><span class="permalink"><a href="#ga078c3c80d5637850ec64e8f5ad5ce0c2">&#9670;&nbsp;</a></span>dma_sniffer_enable()</h2>
2057
2058 <div class="memitem">
2059 <div class="memproto">
2060 <table class="mlabels">
2061   <tr>
2062   <td class="mlabels-left">
2063       <table class="memname">
2064         <tr>
2065           <td class="memname">static void dma_sniffer_enable </td>
2066           <td>(</td>
2067           <td class="paramtype">uint&#160;</td>
2068           <td class="paramname"><em>channel</em>, </td>
2069         </tr>
2070         <tr>
2071           <td class="paramkey"></td>
2072           <td></td>
2073           <td class="paramtype">uint&#160;</td>
2074           <td class="paramname"><em>mode</em>, </td>
2075         </tr>
2076         <tr>
2077           <td class="paramkey"></td>
2078           <td></td>
2079           <td class="paramtype">bool&#160;</td>
2080           <td class="paramname"><em>force_channel_enable</em>&#160;</td>
2081         </tr>
2082         <tr>
2083           <td></td>
2084           <td>)</td>
2085           <td></td><td></td>
2086         </tr>
2087       </table>
2088   </td>
2089   <td class="mlabels-right">
2090 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2091   </tr>
2092 </table>
2093 </div><div class="memdoc">
2094
2095 <p>Enable the DMA sniffing targeting the specified channel. </p>
2096 <p >The mode can be one of the following:</p>
2097 <table class="markdownTable">
2098 <tr class="markdownTableHead">
2099 <th class="markdownTableHeadNone">Mode   </th><th class="markdownTableHeadNone">Function    </th></tr>
2100 <tr class="markdownTableRowOdd">
2101 <td class="markdownTableBodyNone">0x0   </td><td class="markdownTableBodyNone">Calculate a CRC-32 (IEEE802.3 polynomial)    </td></tr>
2102 <tr class="markdownTableRowEven">
2103 <td class="markdownTableBodyNone">0x1   </td><td class="markdownTableBodyNone">Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data    </td></tr>
2104 <tr class="markdownTableRowOdd">
2105 <td class="markdownTableBodyNone">0x2   </td><td class="markdownTableBodyNone">Calculate a CRC-16-CCITT    </td></tr>
2106 <tr class="markdownTableRowEven">
2107 <td class="markdownTableBodyNone">0x3   </td><td class="markdownTableBodyNone">Calculate a CRC-16-CCITT with bit reversed data    </td></tr>
2108 <tr class="markdownTableRowOdd">
2109 <td class="markdownTableBodyNone">0xe   </td><td class="markdownTableBodyNone">XOR reduction over all data. == 1 if the total 1 population count is odd.    </td></tr>
2110 <tr class="markdownTableRowEven">
2111 <td class="markdownTableBodyNone">0xf   </td><td class="markdownTableBodyNone">Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)   </td></tr>
2112 </table>
2113 <dl class="params"><dt>Parameters</dt><dd>
2114   <table class="params">
2115     <tr><td class="paramname">channel</td><td>DMA channel </td></tr>
2116     <tr><td class="paramname">mode</td><td>See description </td></tr>
2117     <tr><td class="paramname">force_channel_enable</td><td>Set true to also turn on sniffing in the channel configuration (this is usually what you want, but sometimes you might have a chain DMA with only certain segments of the chain sniffed, in which case you might pass false). </td></tr>
2118   </table>
2119   </dd>
2120 </dl>
2121
2122 </div>
2123 </div>
2124 <a id="ga3527c2567c9253ca602b91d30ae49d1e" name="ga3527c2567c9253ca602b91d30ae49d1e"></a>
2125 <h2 class="memtitle"><span class="permalink"><a href="#ga3527c2567c9253ca602b91d30ae49d1e">&#9670;&nbsp;</a></span>dma_sniffer_get_data_accumulator()</h2>
2126
2127 <div class="memitem">
2128 <div class="memproto">
2129 <table class="mlabels">
2130   <tr>
2131   <td class="mlabels-left">
2132       <table class="memname">
2133         <tr>
2134           <td class="memname">static uint32_t dma_sniffer_get_data_accumulator </td>
2135           <td>(</td>
2136           <td class="paramtype">void&#160;</td>
2137           <td class="paramname"></td><td>)</td>
2138           <td></td>
2139         </tr>
2140       </table>
2141   </td>
2142   <td class="mlabels-right">
2143 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2144   </tr>
2145 </table>
2146 </div><div class="memdoc">
2147
2148 <p>Get the sniffer's data accumulator value. </p>
2149 <p >Read value calculated by the hardware from sniffing the DMA stream </p>
2150
2151 </div>
2152 </div>
2153 <a id="gac3b250d97550527a584de9d3f770acea" name="gac3b250d97550527a584de9d3f770acea"></a>
2154 <h2 class="memtitle"><span class="permalink"><a href="#gac3b250d97550527a584de9d3f770acea">&#9670;&nbsp;</a></span>dma_sniffer_set_byte_swap_enabled()</h2>
2155
2156 <div class="memitem">
2157 <div class="memproto">
2158 <table class="mlabels">
2159   <tr>
2160   <td class="mlabels-left">
2161       <table class="memname">
2162         <tr>
2163           <td class="memname">static void dma_sniffer_set_byte_swap_enabled </td>
2164           <td>(</td>
2165           <td class="paramtype">bool&#160;</td>
2166           <td class="paramname"><em>swap</em></td><td>)</td>
2167           <td></td>
2168         </tr>
2169       </table>
2170   </td>
2171   <td class="mlabels-right">
2172 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2173   </tr>
2174 </table>
2175 </div><div class="memdoc">
2176
2177 <p>Enable the Sniffer byte swap function. </p>
2178 <p >Locally perform a byte reverse on the sniffed data, before feeding into checksum.</p>
2179 <p >Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if <a class="el" href="group__channel__config.html#ga43c3a2dd43fe7e962b1de0e90a46bb9e" title="Set DMA byte swapping config in a channel configuration object.">channel_config_set_bswap()</a> and <a class="el" href="group__hardware__dma.html#gac3b250d97550527a584de9d3f770acea" title="Enable the Sniffer byte swap function.">dma_sniffer_set_byte_swap_enabled()</a> are both enabled, their effects cancel from the sniffer’s point of view.</p>
2180 <dl class="params"><dt>Parameters</dt><dd>
2181   <table class="params">
2182     <tr><td class="paramname">swap</td><td>Set true to enable byte swapping </td></tr>
2183   </table>
2184   </dd>
2185 </dl>
2186
2187 </div>
2188 </div>
2189 <a id="gacab1f8010c206dfc77b81cb16902a4e4" name="gacab1f8010c206dfc77b81cb16902a4e4"></a>
2190 <h2 class="memtitle"><span class="permalink"><a href="#gacab1f8010c206dfc77b81cb16902a4e4">&#9670;&nbsp;</a></span>dma_sniffer_set_data_accumulator()</h2>
2191
2192 <div class="memitem">
2193 <div class="memproto">
2194 <table class="mlabels">
2195   <tr>
2196   <td class="mlabels-left">
2197       <table class="memname">
2198         <tr>
2199           <td class="memname">static void dma_sniffer_set_data_accumulator </td>
2200           <td>(</td>
2201           <td class="paramtype">uint32_t&#160;</td>
2202           <td class="paramname"><em>seed_value</em></td><td>)</td>
2203           <td></td>
2204         </tr>
2205       </table>
2206   </td>
2207   <td class="mlabels-right">
2208 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2209   </tr>
2210 </table>
2211 </div><div class="memdoc">
2212
2213 <p>Set the sniffer's data accumulator with initial value. </p>
2214 <p >Generally, CRC algorithms are used with the data accumulator initially seeded with 0xFFFF or 0xFFFFFFFF (for crc16 and crc32 algorithms)</p>
2215 <dl class="params"><dt>Parameters</dt><dd>
2216   <table class="params">
2217     <tr><td class="paramname">seed_value</td><td>value to set data accumulator </td></tr>
2218   </table>
2219   </dd>
2220 </dl>
2221
2222 </div>
2223 </div>
2224 <a id="ga1366c938a8322aa1eb8e703b1f22d6af" name="ga1366c938a8322aa1eb8e703b1f22d6af"></a>
2225 <h2 class="memtitle"><span class="permalink"><a href="#ga1366c938a8322aa1eb8e703b1f22d6af">&#9670;&nbsp;</a></span>dma_sniffer_set_output_invert_enabled()</h2>
2226
2227 <div class="memitem">
2228 <div class="memproto">
2229 <table class="mlabels">
2230   <tr>
2231   <td class="mlabels-left">
2232       <table class="memname">
2233         <tr>
2234           <td class="memname">static void dma_sniffer_set_output_invert_enabled </td>
2235           <td>(</td>
2236           <td class="paramtype">bool&#160;</td>
2237           <td class="paramname"><em>invert</em></td><td>)</td>
2238           <td></td>
2239         </tr>
2240       </table>
2241   </td>
2242   <td class="mlabels-right">
2243 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2244   </tr>
2245 </table>
2246 </div><div class="memdoc">
2247
2248 <p>Enable the Sniffer output invert function. </p>
2249 <p >If enabled, the sniff data result appears bit-inverted when read. This does not affect the way the checksum is calculated.</p>
2250 <dl class="params"><dt>Parameters</dt><dd>
2251   <table class="params">
2252     <tr><td class="paramname">invert</td><td>Set true to enable output bit inversion </td></tr>
2253   </table>
2254   </dd>
2255 </dl>
2256
2257 </div>
2258 </div>
2259 <a id="gaa2c5775bdb86d63a4866b2f6f5b41143" name="gaa2c5775bdb86d63a4866b2f6f5b41143"></a>
2260 <h2 class="memtitle"><span class="permalink"><a href="#gaa2c5775bdb86d63a4866b2f6f5b41143">&#9670;&nbsp;</a></span>dma_sniffer_set_output_reverse_enabled()</h2>
2261
2262 <div class="memitem">
2263 <div class="memproto">
2264 <table class="mlabels">
2265   <tr>
2266   <td class="mlabels-left">
2267       <table class="memname">
2268         <tr>
2269           <td class="memname">static void dma_sniffer_set_output_reverse_enabled </td>
2270           <td>(</td>
2271           <td class="paramtype">bool&#160;</td>
2272           <td class="paramname"><em>reverse</em></td><td>)</td>
2273           <td></td>
2274         </tr>
2275       </table>
2276   </td>
2277   <td class="mlabels-right">
2278 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2279   </tr>
2280 </table>
2281 </div><div class="memdoc">
2282
2283 <p>Enable the Sniffer output bit reversal function. </p>
2284 <p >If enabled, the sniff data result appears bit-reversed when read. This does not affect the way the checksum is calculated.</p>
2285 <dl class="params"><dt>Parameters</dt><dd>
2286   <table class="params">
2287     <tr><td class="paramname">reverse</td><td>Set true to enable output bit reversal </td></tr>
2288   </table>
2289   </dd>
2290 </dl>
2291
2292 </div>
2293 </div>
2294 <a id="ga6407f7763b533c98e23f65e35c5e48ee" name="ga6407f7763b533c98e23f65e35c5e48ee"></a>
2295 <h2 class="memtitle"><span class="permalink"><a href="#ga6407f7763b533c98e23f65e35c5e48ee">&#9670;&nbsp;</a></span>dma_start_channel_mask()</h2>
2296
2297 <div class="memitem">
2298 <div class="memproto">
2299 <table class="mlabels">
2300   <tr>
2301   <td class="mlabels-left">
2302       <table class="memname">
2303         <tr>
2304           <td class="memname">static void dma_start_channel_mask </td>
2305           <td>(</td>
2306           <td class="paramtype">uint32_t&#160;</td>
2307           <td class="paramname"><em>chan_mask</em></td><td>)</td>
2308           <td></td>
2309         </tr>
2310       </table>
2311   </td>
2312   <td class="mlabels-right">
2313 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2314   </tr>
2315 </table>
2316 </div><div class="memdoc">
2317
2318 <p>Start one or more channels simultaneously. </p>
2319 <dl class="params"><dt>Parameters</dt><dd>
2320   <table class="params">
2321     <tr><td class="paramname">chan_mask</td><td>Bitmask of all the channels requiring starting. Channel 0 = bit 0, channel 1 = bit 1 etc. </td></tr>
2322   </table>
2323   </dd>
2324 </dl>
2325
2326 </div>
2327 </div>
2328 <a id="ga08fc90c0064510e7a0a2cf8d1cd187bc" name="ga08fc90c0064510e7a0a2cf8d1cd187bc"></a>
2329 <h2 class="memtitle"><span class="permalink"><a href="#ga08fc90c0064510e7a0a2cf8d1cd187bc">&#9670;&nbsp;</a></span>dma_timer_claim()</h2>
2330
2331 <div class="memitem">
2332 <div class="memproto">
2333       <table class="memname">
2334         <tr>
2335           <td class="memname">void dma_timer_claim </td>
2336           <td>(</td>
2337           <td class="paramtype">uint&#160;</td>
2338           <td class="paramname"><em>timer</em></td><td>)</td>
2339           <td></td>
2340         </tr>
2341       </table>
2342 </div><div class="memdoc">
2343
2344 <p>Mark a dma timer as used. </p>
2345 <p >Method for cooperative claiming of hardware. Will cause a panic if the timer is already claimed. Use of this method by libraries detects accidental configurations that would fail in unpredictable ways.</p>
2346 <dl class="params"><dt>Parameters</dt><dd>
2347   <table class="params">
2348     <tr><td class="paramname">timer</td><td>the dma timer </td></tr>
2349   </table>
2350   </dd>
2351 </dl>
2352
2353 </div>
2354 </div>
2355 <a id="ga9b45bfe6985f8c0894d34876eedc3090" name="ga9b45bfe6985f8c0894d34876eedc3090"></a>
2356 <h2 class="memtitle"><span class="permalink"><a href="#ga9b45bfe6985f8c0894d34876eedc3090">&#9670;&nbsp;</a></span>dma_timer_is_claimed()</h2>
2357
2358 <div class="memitem">
2359 <div class="memproto">
2360       <table class="memname">
2361         <tr>
2362           <td class="memname">bool dma_timer_is_claimed </td>
2363           <td>(</td>
2364           <td class="paramtype">uint&#160;</td>
2365           <td class="paramname"><em>timer</em></td><td>)</td>
2366           <td></td>
2367         </tr>
2368       </table>
2369 </div><div class="memdoc">
2370
2371 <p>Determine if a dma timer is claimed. </p>
2372 <dl class="params"><dt>Parameters</dt><dd>
2373   <table class="params">
2374     <tr><td class="paramname">timer</td><td>the dma timer </td></tr>
2375   </table>
2376   </dd>
2377 </dl>
2378 <dl class="section return"><dt>Returns</dt><dd>true if the timer is claimed, false otherwise </dd></dl>
2379 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__hardware__dma.html#ga08fc90c0064510e7a0a2cf8d1cd187bc" title="Mark a dma timer as used.">dma_timer_claim</a> </dd></dl>
2380
2381 </div>
2382 </div>
2383 <a id="ga58f9c3cb606759e4620c82583f833dc8" name="ga58f9c3cb606759e4620c82583f833dc8"></a>
2384 <h2 class="memtitle"><span class="permalink"><a href="#ga58f9c3cb606759e4620c82583f833dc8">&#9670;&nbsp;</a></span>dma_timer_set_fraction()</h2>
2385
2386 <div class="memitem">
2387 <div class="memproto">
2388 <table class="mlabels">
2389   <tr>
2390   <td class="mlabels-left">
2391       <table class="memname">
2392         <tr>
2393           <td class="memname">static void dma_timer_set_fraction </td>
2394           <td>(</td>
2395           <td class="paramtype">uint&#160;</td>
2396           <td class="paramname"><em>timer</em>, </td>
2397         </tr>
2398         <tr>
2399           <td class="paramkey"></td>
2400           <td></td>
2401           <td class="paramtype">uint16_t&#160;</td>
2402           <td class="paramname"><em>numerator</em>, </td>
2403         </tr>
2404         <tr>
2405           <td class="paramkey"></td>
2406           <td></td>
2407           <td class="paramtype">uint16_t&#160;</td>
2408           <td class="paramname"><em>denominator</em>&#160;</td>
2409         </tr>
2410         <tr>
2411           <td></td>
2412           <td>)</td>
2413           <td></td><td></td>
2414         </tr>
2415       </table>
2416   </td>
2417   <td class="mlabels-right">
2418 <span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span>  </td>
2419   </tr>
2420 </table>
2421 </div><div class="memdoc">
2422
2423 <p>Set the multiplier for the given DMA timer. </p>
2424 <p >The timer will run at the system_clock_freq * numerator / denominator, so this is the speed that data elements will be transferred at via a DMA channel using this timer as a DREQ. The multiplier must be less than or equal to one.</p>
2425 <dl class="params"><dt>Parameters</dt><dd>
2426   <table class="params">
2427     <tr><td class="paramname">timer</td><td>the dma timer </td></tr>
2428     <tr><td class="paramname">numerator</td><td>the fraction's numerator </td></tr>
2429     <tr><td class="paramname">denominator</td><td>the fraction's denominator </td></tr>
2430   </table>
2431   </dd>
2432 </dl>
2433
2434 </div>
2435 </div>
2436 <a id="ga890490576d8806b8933aad0e34d09c5e" name="ga890490576d8806b8933aad0e34d09c5e"></a>
2437 <h2 class="memtitle"><span class="permalink"><a href="#ga890490576d8806b8933aad0e34d09c5e">&#9670;&nbsp;</a></span>dma_timer_unclaim()</h2>
2438
2439 <div class="memitem">
2440 <div class="memproto">
2441       <table class="memname">
2442         <tr>
2443           <td class="memname">void dma_timer_unclaim </td>
2444           <td>(</td>
2445           <td class="paramtype">uint&#160;</td>
2446           <td class="paramname"><em>timer</em></td><td>)</td>
2447           <td></td>
2448         </tr>
2449       </table>
2450 </div><div class="memdoc">
2451
2452 <p>Mark a dma timer as no longer used. </p>
2453 <p >Method for cooperative claiming of hardware.</p>
2454 <dl class="params"><dt>Parameters</dt><dd>
2455   <table class="params">
2456     <tr><td class="paramname">timer</td><td>the dma timer to release </td></tr>
2457   </table>
2458   </dd>
2459 </dl>
2460
2461 </div>
2462 </div>
2463 <a id="ga0211681c906ebe4971d0cded8e98f8b5" name="ga0211681c906ebe4971d0cded8e98f8b5"></a>
2464 <h2 class="memtitle"><span class="permalink"><a href="#ga0211681c906ebe4971d0cded8e98f8b5">&#9670;&nbsp;</a></span>dma_unclaim_mask()</h2>
2465
2466 <div class="memitem">
2467 <div class="memproto">
2468       <table class="memname">
2469         <tr>
2470           <td class="memname">void dma_unclaim_mask </td>
2471           <td>(</td>
2472           <td class="paramtype">uint32_t&#160;</td>
2473           <td class="paramname"><em>channel_mask</em></td><td>)</td>
2474           <td></td>
2475         </tr>
2476       </table>
2477 </div><div class="memdoc">
2478
2479 <p>Mark multiple dma channels as no longer used. </p>
2480 <dl class="params"><dt>Parameters</dt><dd>
2481   <table class="params">
2482     <tr><td class="paramname">channel_mask</td><td>Bitfield of all channels to unclaim (bit 0 == channel 0, bit 1 == channel 1 etc) </td></tr>
2483   </table>
2484   </dd>
2485 </dl>
2486
2487 </div>
2488 </div>
2489 </div><!-- contents -->
2490 </div><!-- doc-content -->
2491
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