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 103
 104 <div class="header">
 105   <div class="summary">
 106 <a href="#func-members">Functions</a>  </div>
 107   <div class="headertitle"><div class="title">hardware_base<div class="ingroups"><a class="el" href="group__hardware.html">Hardware APIs</a></div></div></div>
 108 </div><!--header-->
 109 <div class="contents">
 110
 111 <p>Low-level types and (atomic) accessors for memory-mapped hardware registers.
 112 <a href="#details">More...</a></p>
 113 <table class="memberdecls">
 114 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
 115 Functions</h2></td></tr>
 116 <tr class="memitem:ga625e737a57f12211cf1f634ca5095ae4"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__base.html#ga625e737a57f12211cf1f634ca5095ae4">hw_set_bits</a> (io_rw_32 *addr, uint32_t mask)</td></tr>
 117 <tr class="memdesc:ga625e737a57f12211cf1f634ca5095ae4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomically set the specified bits to 1 in a HW register.  <a href="group__hardware__base.html#ga625e737a57f12211cf1f634ca5095ae4">More...</a><br /></td></tr>
 118 <tr class="separator:ga625e737a57f12211cf1f634ca5095ae4"><td class="memSeparator" colspan="2">&#160;</td></tr>
 119 <tr class="memitem:gafd1c089df868d987daf95870b501c2ed"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__base.html#gafd1c089df868d987daf95870b501c2ed">hw_clear_bits</a> (io_rw_32 *addr, uint32_t mask)</td></tr>
 120 <tr class="memdesc:gafd1c089df868d987daf95870b501c2ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomically clear the specified bits to 0 in a HW register.  <a href="group__hardware__base.html#gafd1c089df868d987daf95870b501c2ed">More...</a><br /></td></tr>
 121 <tr class="separator:gafd1c089df868d987daf95870b501c2ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
 122 <tr class="memitem:ga643ecd2ac7ab82d2e1f04dba42135f2b"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__base.html#ga643ecd2ac7ab82d2e1f04dba42135f2b">hw_xor_bits</a> (io_rw_32 *addr, uint32_t mask)</td></tr>
 123 <tr class="memdesc:ga643ecd2ac7ab82d2e1f04dba42135f2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Atomically flip the specified bits in a HW register.  <a href="group__hardware__base.html#ga643ecd2ac7ab82d2e1f04dba42135f2b">More...</a><br /></td></tr>
 124 <tr class="separator:ga643ecd2ac7ab82d2e1f04dba42135f2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
 125 <tr class="memitem:ga81b27e30abef56fe090d22fd8dfdbcc1"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hardware__base.html#ga81b27e30abef56fe090d22fd8dfdbcc1">hw_write_masked</a> (io_rw_32 *addr, uint32_t values, uint32_t write_mask)</td></tr>
 126 <tr class="memdesc:ga81b27e30abef56fe090d22fd8dfdbcc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set new values for a sub-set of the bits in a HW register.  <a href="group__hardware__base.html#ga81b27e30abef56fe090d22fd8dfdbcc1">More...</a><br /></td></tr>
 127 <tr class="separator:ga81b27e30abef56fe090d22fd8dfdbcc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
 128 </table>
 129 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
 130 <p >Low-level types and (atomic) accessors for memory-mapped hardware registers. </p>
 131 <p ><code>hardware_base</code> defines the low level types and access functions for memory mapped hardware registers. It is included by default by all other hardware libraries.</p>
 132 <p >The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register. The register type names are formed by concatenating one from each of the 3 parts A, B, C</p>
 133 <table class="markdownTable">
 134 <tr class="markdownTableHead">
 135 <th class="markdownTableHeadNone">A   </th><th class="markdownTableHeadNone">B   </th><th class="markdownTableHeadNone">C   </th><th class="markdownTableHeadNone">Meaning    </th></tr>
 136 <tr class="markdownTableRowOdd">
 137 <td class="markdownTableBodyNone">io_   </td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone">A Memory mapped IO register    </td></tr>
 138 <tr class="markdownTableRowEven">
 139 <td class="markdownTableBodyNone">&#160;   </td><td class="markdownTableBodyNone">ro_   </td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone">read-only access    </td></tr>
 140 <tr class="markdownTableRowOdd">
 141 <td class="markdownTableBodyNone">&#160;   </td><td class="markdownTableBodyNone">rw_   </td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone">read-write access    </td></tr>
 142 <tr class="markdownTableRowEven">
 143 <td class="markdownTableBodyNone">&#160;   </td><td class="markdownTableBodyNone">wo_   </td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone">write-only access (can't actually be enforced via C API)    </td></tr>
 144 <tr class="markdownTableRowOdd">
 145 <td class="markdownTableBodyNone">&#160;   </td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone">8   </td><td class="markdownTableBodyNone">8-bit wide access    </td></tr>
 146 <tr class="markdownTableRowEven">
 147 <td class="markdownTableBodyNone">&#160;   </td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone">16   </td><td class="markdownTableBodyNone">16-bit wide access    </td></tr>
 148 <tr class="markdownTableRowOdd">
 149 <td class="markdownTableBodyNone">&#160;   </td><td class="markdownTableBodyNone"></td><td class="markdownTableBodyNone">32   </td><td class="markdownTableBodyNone">32-bit wide access   </td></tr>
 150 </table>
 151 <p >When dealing with these types, you will always use a pointer, i.e. <code>io_rw_32 *some_reg</code> is a pointer to a read/write 32 bit register that you can write with <code>*some_reg = value</code>, or read with <code>value = *some_reg</code>.</p>
 152 <p >RP-series hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within a hardware register so that concurrent access by two cores is always consistent with one atomic operation being performed first, followed by the second.</p>
 153 <p >See <a class="el" href="group__hardware__base.html#ga625e737a57f12211cf1f634ca5095ae4" title="Atomically set the specified bits to 1 in a HW register.">hw_set_bits()</a>, <a class="el" href="group__hardware__base.html#gafd1c089df868d987daf95870b501c2ed" title="Atomically clear the specified bits to 0 in a HW register.">hw_clear_bits()</a> and <a class="el" href="group__hardware__base.html#ga643ecd2ac7ab82d2e1f04dba42135f2b" title="Atomically flip the specified bits in a HW register.">hw_xor_bits()</a> provide for atomic access via a pointer to a 32 bit register</p>
 154 <p >Additionally given a pointer to a structure representing a piece of hardware (e.g. <code><a class="el" href="structdma__hw__t.html">dma_hw_t</a> *dma_hw</code> for the DMA controller), you can get an alias to the entire structure such that writing any member (register) within the structure is equivalent to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()...</p>
 155 <p >For example <code>hw_set_alias(dma_hw)-&gt;inte1 = 0x80;</code> will set bit 7 of the INTE1 register of the DMA controller, leaving the other bits unchanged. </p>
 156 <h2 class="groupheader">Function Documentation</h2>
 157 <a id="gafd1c089df868d987daf95870b501c2ed" name="gafd1c089df868d987daf95870b501c2ed"></a>
 158 <h2 class="memtitle"><span class="permalink"><a href="#gafd1c089df868d987daf95870b501c2ed">&#9670;&nbsp;</a></span>hw_clear_bits()</h2>
 159
 160 <div class="memitem">
 161 <div class="memproto">
 162 <table class="mlabels">
 163   <tr>
 164   <td class="mlabels-left">
 165       <table class="memname">
 166         <tr>
 167           <td class="memname">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void hw_clear_bits </td>
 168           <td>(</td>
 169           <td class="paramtype">io_rw_32 *&#160;</td>
 170           <td class="paramname"><em>addr</em>, </td>
 171         </tr>
 172         <tr>
 173           <td class="paramkey"></td>
 174           <td></td>
 175           <td class="paramtype">uint32_t&#160;</td>
 176           <td class="paramname"><em>mask</em>&#160;</td>
 177         </tr>
 178         <tr>
 179           <td></td>
 180           <td>)</td>
 181           <td></td><td></td>
 182         </tr>
 183       </table>
 184   </td>
 185   <td class="mlabels-right">
 186 <span class="mlabels"><span class="mlabel">static</span></span>  </td>
 187   </tr>
 188 </table>
 189 </div><div class="memdoc">
 190
 191 <p>Atomically clear the specified bits to 0 in a HW register. </p>
 192 <dl class="params"><dt>Parameters</dt><dd>
 193   <table class="params">
 194     <tr><td class="paramname">addr</td><td>Address of writable register </td></tr>
 195     <tr><td class="paramname">mask</td><td>Bit-mask specifying bits to clear </td></tr>
 196   </table>
 197   </dd>
 198 </dl>
 199
 200 </div>
 201 </div>
 202 <a id="ga625e737a57f12211cf1f634ca5095ae4" name="ga625e737a57f12211cf1f634ca5095ae4"></a>
 203 <h2 class="memtitle"><span class="permalink"><a href="#ga625e737a57f12211cf1f634ca5095ae4">&#9670;&nbsp;</a></span>hw_set_bits()</h2>
 204
 205 <div class="memitem">
 206 <div class="memproto">
 207 <table class="mlabels">
 208   <tr>
 209   <td class="mlabels-left">
 210       <table class="memname">
 211         <tr>
 212           <td class="memname">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void hw_set_bits </td>
 213           <td>(</td>
 214           <td class="paramtype">io_rw_32 *&#160;</td>
 215           <td class="paramname"><em>addr</em>, </td>
 216         </tr>
 217         <tr>
 218           <td class="paramkey"></td>
 219           <td></td>
 220           <td class="paramtype">uint32_t&#160;</td>
 221           <td class="paramname"><em>mask</em>&#160;</td>
 222         </tr>
 223         <tr>
 224           <td></td>
 225           <td>)</td>
 226           <td></td><td></td>
 227         </tr>
 228       </table>
 229   </td>
 230   <td class="mlabels-right">
 231 <span class="mlabels"><span class="mlabel">static</span></span>  </td>
 232   </tr>
 233 </table>
 234 </div><div class="memdoc">
 235
 236 <p>Atomically set the specified bits to 1 in a HW register. </p>
 237 <dl class="params"><dt>Parameters</dt><dd>
 238   <table class="params">
 239     <tr><td class="paramname">addr</td><td>Address of writable register </td></tr>
 240     <tr><td class="paramname">mask</td><td>Bit-mask specifying bits to set </td></tr>
 241   </table>
 242   </dd>
 243 </dl>
 244
 245 </div>
 246 </div>
 247 <a id="ga81b27e30abef56fe090d22fd8dfdbcc1" name="ga81b27e30abef56fe090d22fd8dfdbcc1"></a>
 248 <h2 class="memtitle"><span class="permalink"><a href="#ga81b27e30abef56fe090d22fd8dfdbcc1">&#9670;&nbsp;</a></span>hw_write_masked()</h2>
 249
 250 <div class="memitem">
 251 <div class="memproto">
 252 <table class="mlabels">
 253   <tr>
 254   <td class="mlabels-left">
 255       <table class="memname">
 256         <tr>
 257           <td class="memname">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void hw_write_masked </td>
 258           <td>(</td>
 259           <td class="paramtype">io_rw_32 *&#160;</td>
 260           <td class="paramname"><em>addr</em>, </td>
 261         </tr>
 262         <tr>
 263           <td class="paramkey"></td>
 264           <td></td>
 265           <td class="paramtype">uint32_t&#160;</td>
 266           <td class="paramname"><em>values</em>, </td>
 267         </tr>
 268         <tr>
 269           <td class="paramkey"></td>
 270           <td></td>
 271           <td class="paramtype">uint32_t&#160;</td>
 272           <td class="paramname"><em>write_mask</em>&#160;</td>
 273         </tr>
 274         <tr>
 275           <td></td>
 276           <td>)</td>
 277           <td></td><td></td>
 278         </tr>
 279       </table>
 280   </td>
 281   <td class="mlabels-right">
 282 <span class="mlabels"><span class="mlabel">static</span></span>  </td>
 283   </tr>
 284 </table>
 285 </div><div class="memdoc">
 286
 287 <p>Set new values for a sub-set of the bits in a HW register. </p>
 288 <p >Sets destination bits to values specified in <code>values</code>, if and only if corresponding bit in <code>write_mask</code> is set</p>
 289 <p >Note: this method allows safe concurrent modification of <em>different</em> bits of a register, but multiple concurrent access to the same bits is still unsafe.</p>
 290 <dl class="params"><dt>Parameters</dt><dd>
 291   <table class="params">
 292     <tr><td class="paramname">addr</td><td>Address of writable register </td></tr>
 293     <tr><td class="paramname">values</td><td>Bits values </td></tr>
 294     <tr><td class="paramname">write_mask</td><td>Mask of bits to change </td></tr>
 295   </table>
 296   </dd>
 297 </dl>
 298
 299 </div>
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 301 <a id="ga643ecd2ac7ab82d2e1f04dba42135f2b" name="ga643ecd2ac7ab82d2e1f04dba42135f2b"></a>
 302 <h2 class="memtitle"><span class="permalink"><a href="#ga643ecd2ac7ab82d2e1f04dba42135f2b">&#9670;&nbsp;</a></span>hw_xor_bits()</h2>
 303
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 306 <table class="mlabels">
 307   <tr>
 308   <td class="mlabels-left">
 309       <table class="memname">
 310         <tr>
 311           <td class="memname">static <a class="el" href="group__pico__platform.html#ga23eadd8d1642fb8fe4600708c36e116a">__force_inline</a> void hw_xor_bits </td>
 312           <td>(</td>
 313           <td class="paramtype">io_rw_32 *&#160;</td>
 314           <td class="paramname"><em>addr</em>, </td>
 315         </tr>
 316         <tr>
 317           <td class="paramkey"></td>
 318           <td></td>
 319           <td class="paramtype">uint32_t&#160;</td>
 320           <td class="paramname"><em>mask</em>&#160;</td>
 321         </tr>
 322         <tr>
 323           <td></td>
 324           <td>)</td>
 325           <td></td><td></td>
 326         </tr>
 327       </table>
 328   </td>
 329   <td class="mlabels-right">
 330 <span class="mlabels"><span class="mlabel">static</span></span>  </td>
 331   </tr>
 332 </table>
 333 </div><div class="memdoc">
 334
 335 <p>Atomically flip the specified bits in a HW register. </p>
 336 <dl class="params"><dt>Parameters</dt><dd>
 337   <table class="params">
 338     <tr><td class="paramname">addr</td><td>Address of writable register </td></tr>
 339     <tr><td class="paramname">mask</td><td>Bit-mask specifying bits to invert </td></tr>
 340   </table>
 341   </dd>
 342 </dl>
 343
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 345 </div>
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