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 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">accessctrl.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_ACCESSCTRL_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_ACCESSCTRL_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/accessctrl.h&quot;</span></div>
 115 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
 116 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_accessctrl</span></div>
 117 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
 118 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 119 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/accessctrl.h.</span></div>
 120 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
 121 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 122 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 123 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
 124 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structaccessctrl__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 125 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    _REG_(ACCESSCTRL_LOCK_OFFSET) <span class="comment">// ACCESSCTRL_LOCK</span></div>
 126 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    <span class="comment">// Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master</span></div>
 127 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// 0x00000008 [3]     DEBUG        (0) </span></div>
 128 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0x00000004 [2]     DMA          (1) </span></div>
 129 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// 0x00000002 [1]     CORE1        (0) </span></div>
 130 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    <span class="comment">// 0x00000001 [0]     CORE0        (0) </span></div>
 131 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    io_rw_32 lock;</div>
 132 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span> </div>
 133 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    _REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) <span class="comment">// ACCESSCTRL_FORCE_CORE_NS</span></div>
 134 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    <span class="comment">// Force core 1&#39;s bus accesses to always be Non-secure, no matter the core&#39;s internal state</span></div>
 135 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    <span class="comment">// 0x00000002 [1]     CORE1        (0) </span></div>
 136 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    io_rw_32 force_core_ns;</div>
 137 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span> </div>
 138 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    _REG_(ACCESSCTRL_CFGRESET_OFFSET) <span class="comment">// ACCESSCTRL_CFGRESET</span></div>
 139 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers</span></div>
 140 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// 0x00000001 [0]     CFGRESET     (0) </span></div>
 141 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    io_wo_32 cfgreset;</div>
 142 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span> </div>
 143 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_GPIO_NSMASK0 applies similarly to other array indexes)</span></div>
 144 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    _REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) <span class="comment">// ACCESSCTRL_GPIO_NSMASK0</span></div>
 145 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// Control whether GPIO0</span></div>
 146 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_NSMASK0 (0x00000000) </span></div>
 147 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    io_rw_32 gpio_nsmask[2];</div>
 148 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span> </div>
 149 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    _REG_(ACCESSCTRL_ROM_OFFSET) <span class="comment">// ACCESSCTRL_ROM</span></div>
 150 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    <span class="comment">// Control access to ROM. Defaults to fully open access.</span></div>
 151 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, ROM can be accessed by the debugger, at...</span></div>
 152 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, ROM can be accessed by the DMA, at...</span></div>
 153 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, ROM can be accessed by core 1, at...</span></div>
 154 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, ROM can be accessed by core 0, at...</span></div>
 155 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, ROM can be accessed from a Secure, Privileged context</span></div>
 156 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, ROM can be accessed from a...</span></div>
 157 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x00000002 [1]     NSP          (1) If 1, ROM can be accessed from a Non-secure, Privileged context</span></div>
 158 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    <span class="comment">// 0x00000001 [0]     NSU          (1) If 1, and NSP is also set, ROM can be accessed from a...</span></div>
 159 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    io_rw_32 rom;</div>
 160 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span> </div>
 161 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    _REG_(ACCESSCTRL_XIP_MAIN_OFFSET) <span class="comment">// ACCESSCTRL_XIP_MAIN</span></div>
 162 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// Control access to XIP_MAIN. Defaults to fully open access.</span></div>
 163 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, XIP_MAIN can be accessed by the debugger, at...</span></div>
 164 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, XIP_MAIN can be accessed by the DMA, at...</span></div>
 165 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, XIP_MAIN can be accessed by core 1, at...</span></div>
 166 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, XIP_MAIN can be accessed by core 0, at...</span></div>
 167 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, XIP_MAIN can be accessed from a Secure, Privileged context</span></div>
 168 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, XIP_MAIN can be accessed from...</span></div>
 169 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    <span class="comment">// 0x00000002 [1]     NSP          (1) If 1, XIP_MAIN can be accessed from a Non-secure,...</span></div>
 170 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// 0x00000001 [0]     NSU          (1) If 1, and NSP is also set, XIP_MAIN can be accessed from...</span></div>
 171 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    io_rw_32 xip_main;</div>
 172 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span> </div>
 173 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_SRAM0 applies similarly to other array indexes)</span></div>
 174 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    _REG_(ACCESSCTRL_SRAM0_OFFSET) <span class="comment">// ACCESSCTRL_SRAM0</span></div>
 175 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    <span class="comment">// Control access to SRAM0. Defaults to fully open access.</span></div>
 176 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, SRAM0 can be accessed by the debugger, at...</span></div>
 177 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, SRAM0 can be accessed by the DMA, at...</span></div>
 178 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, SRAM0 can be accessed by core 1, at...</span></div>
 179 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, SRAM0 can be accessed by core 0, at...</span></div>
 180 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, SRAM0 can be accessed from a Secure, Privileged context</span></div>
 181 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, SRAM0 can be accessed from a...</span></div>
 182 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    <span class="comment">// 0x00000002 [1]     NSP          (1) If 1, SRAM0 can be accessed from a Non-secure, Privileged context</span></div>
 183 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    <span class="comment">// 0x00000001 [0]     NSU          (1) If 1, and NSP is also set, SRAM0 can be accessed from a...</span></div>
 184 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    io_rw_32 sram[10];</div>
 185 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span> </div>
 186 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    _REG_(ACCESSCTRL_DMA_OFFSET) <span class="comment">// ACCESSCTRL_DMA</span></div>
 187 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// Control access to DMA. Defaults to Secure access from any master.</span></div>
 188 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, DMA can be accessed by the debugger, at...</span></div>
 189 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, DMA can be accessed by the DMA, at...</span></div>
 190 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, DMA can be accessed by core 1, at...</span></div>
 191 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, DMA can be accessed by core 0, at...</span></div>
 192 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, DMA can be accessed from a Secure, Privileged context</span></div>
 193 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, DMA can be accessed from a...</span></div>
 194 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, DMA can be accessed from a Non-secure, Privileged context</span></div>
 195 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, DMA can be accessed from a...</span></div>
 196 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    io_rw_32 dma;</div>
 197 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span> </div>
 198 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    _REG_(ACCESSCTRL_USBCTRL_OFFSET) <span class="comment">// ACCESSCTRL_USBCTRL</span></div>
 199 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    <span class="comment">// Control access to USBCTRL. Defaults to Secure access from any master.</span></div>
 200 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, USBCTRL can be accessed by the debugger, at...</span></div>
 201 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, USBCTRL can be accessed by the DMA, at...</span></div>
 202 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, USBCTRL can be accessed by core 1, at...</span></div>
 203 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, USBCTRL can be accessed by core 0, at...</span></div>
 204 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, USBCTRL can be accessed from a Secure, Privileged context</span></div>
 205 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, USBCTRL can be accessed from a...</span></div>
 206 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, USBCTRL can be accessed from a Non-secure,...</span></div>
 207 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, USBCTRL can be accessed from...</span></div>
 208 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    io_rw_32 usbctrl;</div>
 209 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span> </div>
 210 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_PIO0 applies similarly to other array indexes)</span></div>
 211 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    _REG_(ACCESSCTRL_PIO0_OFFSET) <span class="comment">// ACCESSCTRL_PIO0</span></div>
 212 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    <span class="comment">// Control access to PIO0. Defaults to Secure access from any master.</span></div>
 213 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, PIO0 can be accessed by the debugger, at...</span></div>
 214 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, PIO0 can be accessed by the DMA, at...</span></div>
 215 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, PIO0 can be accessed by core 1, at...</span></div>
 216 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, PIO0 can be accessed by core 0, at...</span></div>
 217 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, PIO0 can be accessed from a Secure, Privileged context</span></div>
 218 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, PIO0 can be accessed from a...</span></div>
 219 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, PIO0 can be accessed from a Non-secure, Privileged context</span></div>
 220 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, PIO0 can be accessed from a...</span></div>
 221 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span>    io_rw_32 pio[3];</div>
 222 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span> </div>
 223 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    _REG_(ACCESSCTRL_CORESIGHT_TRACE_OFFSET) <span class="comment">// ACCESSCTRL_CORESIGHT_TRACE</span></div>
 224 <div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    <span class="comment">// Control access to CORESIGHT_TRACE. Defaults to Secure, Privileged processor or debug access only.</span></div>
 225 <div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, CORESIGHT_TRACE can be accessed by the debugger,...</span></div>
 226 <div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, CORESIGHT_TRACE can be accessed by the DMA, at...</span></div>
 227 <div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, CORESIGHT_TRACE can be accessed by core 1, at...</span></div>
 228 <div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, CORESIGHT_TRACE can be accessed by core 0, at...</span></div>
 229 <div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, CORESIGHT_TRACE can be accessed from a Secure,...</span></div>
 230 <div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, CORESIGHT_TRACE can be...</span></div>
 231 <div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, CORESIGHT_TRACE can be accessed from a Non-secure,...</span></div>
 232 <div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, CORESIGHT_TRACE can be...</span></div>
 233 <div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    io_rw_32 coresight_trace;</div>
 234 <div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span> </div>
 235 <div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    _REG_(ACCESSCTRL_CORESIGHT_PERIPH_OFFSET) <span class="comment">// ACCESSCTRL_CORESIGHT_PERIPH</span></div>
 236 <div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span>    <span class="comment">// Control access to CORESIGHT_PERIPH. Defaults to Secure, Privileged processor or debug access only.</span></div>
 237 <div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, CORESIGHT_PERIPH can be accessed by the debugger,...</span></div>
 238 <div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, CORESIGHT_PERIPH can be accessed by the DMA, at...</span></div>
 239 <div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, CORESIGHT_PERIPH can be accessed by core 1, at...</span></div>
 240 <div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, CORESIGHT_PERIPH can be accessed by core 0, at...</span></div>
 241 <div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, CORESIGHT_PERIPH can be accessed from a Secure,...</span></div>
 242 <div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, CORESIGHT_PERIPH can be...</span></div>
 243 <div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, CORESIGHT_PERIPH can be accessed from a...</span></div>
 244 <div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, CORESIGHT_PERIPH can be...</span></div>
 245 <div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>    io_rw_32 coresight_periph;</div>
 246 <div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span> </div>
 247 <div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    _REG_(ACCESSCTRL_SYSINFO_OFFSET) <span class="comment">// ACCESSCTRL_SYSINFO</span></div>
 248 <div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span>    <span class="comment">// Control access to SYSINFO. Defaults to fully open access.</span></div>
 249 <div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, SYSINFO can be accessed by the debugger, at...</span></div>
 250 <div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, SYSINFO can be accessed by the DMA, at...</span></div>
 251 <div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, SYSINFO can be accessed by core 1, at...</span></div>
 252 <div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, SYSINFO can be accessed by core 0, at...</span></div>
 253 <div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, SYSINFO can be accessed from a Secure, Privileged context</span></div>
 254 <div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, SYSINFO can be accessed from a...</span></div>
 255 <div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span>    <span class="comment">// 0x00000002 [1]     NSP          (1) If 1, SYSINFO can be accessed from a Non-secure,...</span></div>
 256 <div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    <span class="comment">// 0x00000001 [0]     NSU          (1) If 1, and NSP is also set, SYSINFO can be accessed from...</span></div>
 257 <div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span>    io_rw_32 sysinfo;</div>
 258 <div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span> </div>
 259 <div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    _REG_(ACCESSCTRL_RESETS_OFFSET) <span class="comment">// ACCESSCTRL_RESETS</span></div>
 260 <div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// Control access to RESETS. Defaults to Secure access from any master.</span></div>
 261 <div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, RESETS can be accessed by the debugger, at...</span></div>
 262 <div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, RESETS can be accessed by the DMA, at...</span></div>
 263 <div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, RESETS can be accessed by core 1, at...</span></div>
 264 <div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, RESETS can be accessed by core 0, at...</span></div>
 265 <div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, RESETS can be accessed from a Secure, Privileged context</span></div>
 266 <div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, RESETS can be accessed from a...</span></div>
 267 <div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, RESETS can be accessed from a Non-secure,...</span></div>
 268 <div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, RESETS can be accessed from a...</span></div>
 269 <div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>    io_rw_32 resets;</div>
 270 <div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span> </div>
 271 <div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_IO_BANK0 applies similarly to other array indexes)</span></div>
 272 <div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span>    _REG_(ACCESSCTRL_IO_BANK0_OFFSET) <span class="comment">// ACCESSCTRL_IO_BANK0</span></div>
 273 <div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span>    <span class="comment">// Control access to IO_BANK0. Defaults to Secure access from any master.</span></div>
 274 <div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, IO_BANK0 can be accessed by the debugger, at...</span></div>
 275 <div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, IO_BANK0 can be accessed by the DMA, at...</span></div>
 276 <div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, IO_BANK0 can be accessed by core 1, at...</span></div>
 277 <div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, IO_BANK0 can be accessed by core 0, at...</span></div>
 278 <div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, IO_BANK0 can be accessed from a Secure, Privileged context</span></div>
 279 <div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, IO_BANK0 can be accessed from...</span></div>
 280 <div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, IO_BANK0 can be accessed from a Non-secure,...</span></div>
 281 <div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, IO_BANK0 can be accessed from...</span></div>
 282 <div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span>    io_rw_32 io_bank[2];</div>
 283 <div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span> </div>
 284 <div class="line"><a id="l00186" name="l00186"></a><span class="lineno">  186</span>    _REG_(ACCESSCTRL_PADS_BANK0_OFFSET) <span class="comment">// ACCESSCTRL_PADS_BANK0</span></div>
 285 <div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span>    <span class="comment">// Control access to PADS_BANK0. Defaults to Secure access from any master.</span></div>
 286 <div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, PADS_BANK0 can be accessed by the debugger, at...</span></div>
 287 <div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, PADS_BANK0 can be accessed by the DMA, at...</span></div>
 288 <div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, PADS_BANK0 can be accessed by core 1, at...</span></div>
 289 <div class="line"><a id="l00191" name="l00191"></a><span class="lineno">  191</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, PADS_BANK0 can be accessed by core 0, at...</span></div>
 290 <div class="line"><a id="l00192" name="l00192"></a><span class="lineno">  192</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, PADS_BANK0 can be accessed from a Secure,...</span></div>
 291 <div class="line"><a id="l00193" name="l00193"></a><span class="lineno">  193</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, PADS_BANK0 can be accessed...</span></div>
 292 <div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, PADS_BANK0 can be accessed from a Non-secure,...</span></div>
 293 <div class="line"><a id="l00195" name="l00195"></a><span class="lineno">  195</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, PADS_BANK0 can be accessed...</span></div>
 294 <div class="line"><a id="l00196" name="l00196"></a><span class="lineno">  196</span>    io_rw_32 pads_bank0;</div>
 295 <div class="line"><a id="l00197" name="l00197"></a><span class="lineno">  197</span> </div>
 296 <div class="line"><a id="l00198" name="l00198"></a><span class="lineno">  198</span>    _REG_(ACCESSCTRL_PADS_QSPI_OFFSET) <span class="comment">// ACCESSCTRL_PADS_QSPI</span></div>
 297 <div class="line"><a id="l00199" name="l00199"></a><span class="lineno">  199</span>    <span class="comment">// Control access to PADS_QSPI. Defaults to Secure access from any master.</span></div>
 298 <div class="line"><a id="l00200" name="l00200"></a><span class="lineno">  200</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, PADS_QSPI can be accessed by the debugger, at...</span></div>
 299 <div class="line"><a id="l00201" name="l00201"></a><span class="lineno">  201</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, PADS_QSPI can be accessed by the DMA, at...</span></div>
 300 <div class="line"><a id="l00202" name="l00202"></a><span class="lineno">  202</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, PADS_QSPI can be accessed by core 1, at...</span></div>
 301 <div class="line"><a id="l00203" name="l00203"></a><span class="lineno">  203</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, PADS_QSPI can be accessed by core 0, at...</span></div>
 302 <div class="line"><a id="l00204" name="l00204"></a><span class="lineno">  204</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, PADS_QSPI can be accessed from a Secure, Privileged context</span></div>
 303 <div class="line"><a id="l00205" name="l00205"></a><span class="lineno">  205</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, PADS_QSPI can be accessed from...</span></div>
 304 <div class="line"><a id="l00206" name="l00206"></a><span class="lineno">  206</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, PADS_QSPI can be accessed from a Non-secure,...</span></div>
 305 <div class="line"><a id="l00207" name="l00207"></a><span class="lineno">  207</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, PADS_QSPI can be accessed...</span></div>
 306 <div class="line"><a id="l00208" name="l00208"></a><span class="lineno">  208</span>    io_rw_32 pads_qspi;</div>
 307 <div class="line"><a id="l00209" name="l00209"></a><span class="lineno">  209</span> </div>
 308 <div class="line"><a id="l00210" name="l00210"></a><span class="lineno">  210</span>    _REG_(ACCESSCTRL_BUSCTRL_OFFSET) <span class="comment">// ACCESSCTRL_BUSCTRL</span></div>
 309 <div class="line"><a id="l00211" name="l00211"></a><span class="lineno">  211</span>    <span class="comment">// Control access to BUSCTRL. Defaults to Secure access from any master.</span></div>
 310 <div class="line"><a id="l00212" name="l00212"></a><span class="lineno">  212</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, BUSCTRL can be accessed by the debugger, at...</span></div>
 311 <div class="line"><a id="l00213" name="l00213"></a><span class="lineno">  213</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, BUSCTRL can be accessed by the DMA, at...</span></div>
 312 <div class="line"><a id="l00214" name="l00214"></a><span class="lineno">  214</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, BUSCTRL can be accessed by core 1, at...</span></div>
 313 <div class="line"><a id="l00215" name="l00215"></a><span class="lineno">  215</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, BUSCTRL can be accessed by core 0, at...</span></div>
 314 <div class="line"><a id="l00216" name="l00216"></a><span class="lineno">  216</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, BUSCTRL can be accessed from a Secure, Privileged context</span></div>
 315 <div class="line"><a id="l00217" name="l00217"></a><span class="lineno">  217</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, BUSCTRL can be accessed from a...</span></div>
 316 <div class="line"><a id="l00218" name="l00218"></a><span class="lineno">  218</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, BUSCTRL can be accessed from a Non-secure,...</span></div>
 317 <div class="line"><a id="l00219" name="l00219"></a><span class="lineno">  219</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, BUSCTRL can be accessed from...</span></div>
 318 <div class="line"><a id="l00220" name="l00220"></a><span class="lineno">  220</span>    io_rw_32 busctrl;</div>
 319 <div class="line"><a id="l00221" name="l00221"></a><span class="lineno">  221</span> </div>
 320 <div class="line"><a id="l00222" name="l00222"></a><span class="lineno">  222</span>    _REG_(ACCESSCTRL_ADC0_OFFSET) <span class="comment">// ACCESSCTRL_ADC0</span></div>
 321 <div class="line"><a id="l00223" name="l00223"></a><span class="lineno">  223</span>    <span class="comment">// Control access to ADC0. Defaults to Secure access from any master.</span></div>
 322 <div class="line"><a id="l00224" name="l00224"></a><span class="lineno">  224</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, ADC0 can be accessed by the debugger, at...</span></div>
 323 <div class="line"><a id="l00225" name="l00225"></a><span class="lineno">  225</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, ADC0 can be accessed by the DMA, at...</span></div>
 324 <div class="line"><a id="l00226" name="l00226"></a><span class="lineno">  226</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, ADC0 can be accessed by core 1, at...</span></div>
 325 <div class="line"><a id="l00227" name="l00227"></a><span class="lineno">  227</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, ADC0 can be accessed by core 0, at...</span></div>
 326 <div class="line"><a id="l00228" name="l00228"></a><span class="lineno">  228</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, ADC0 can be accessed from a Secure, Privileged context</span></div>
 327 <div class="line"><a id="l00229" name="l00229"></a><span class="lineno">  229</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, ADC0 can be accessed from a...</span></div>
 328 <div class="line"><a id="l00230" name="l00230"></a><span class="lineno">  230</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context</span></div>
 329 <div class="line"><a id="l00231" name="l00231"></a><span class="lineno">  231</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, ADC0 can be accessed from a...</span></div>
 330 <div class="line"><a id="l00232" name="l00232"></a><span class="lineno">  232</span>    io_rw_32 adc0;</div>
 331 <div class="line"><a id="l00233" name="l00233"></a><span class="lineno">  233</span> </div>
 332 <div class="line"><a id="l00234" name="l00234"></a><span class="lineno">  234</span>    _REG_(ACCESSCTRL_HSTX_OFFSET) <span class="comment">// ACCESSCTRL_HSTX</span></div>
 333 <div class="line"><a id="l00235" name="l00235"></a><span class="lineno">  235</span>    <span class="comment">// Control access to HSTX. Defaults to Secure access from any master.</span></div>
 334 <div class="line"><a id="l00236" name="l00236"></a><span class="lineno">  236</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, HSTX can be accessed by the debugger, at...</span></div>
 335 <div class="line"><a id="l00237" name="l00237"></a><span class="lineno">  237</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, HSTX can be accessed by the DMA, at...</span></div>
 336 <div class="line"><a id="l00238" name="l00238"></a><span class="lineno">  238</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, HSTX can be accessed by core 1, at...</span></div>
 337 <div class="line"><a id="l00239" name="l00239"></a><span class="lineno">  239</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, HSTX can be accessed by core 0, at...</span></div>
 338 <div class="line"><a id="l00240" name="l00240"></a><span class="lineno">  240</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, HSTX can be accessed from a Secure, Privileged context</span></div>
 339 <div class="line"><a id="l00241" name="l00241"></a><span class="lineno">  241</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, HSTX can be accessed from a...</span></div>
 340 <div class="line"><a id="l00242" name="l00242"></a><span class="lineno">  242</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, HSTX can be accessed from a Non-secure, Privileged context</span></div>
 341 <div class="line"><a id="l00243" name="l00243"></a><span class="lineno">  243</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, HSTX can be accessed from a...</span></div>
 342 <div class="line"><a id="l00244" name="l00244"></a><span class="lineno">  244</span>    io_rw_32 hstx;</div>
 343 <div class="line"><a id="l00245" name="l00245"></a><span class="lineno">  245</span> </div>
 344 <div class="line"><a id="l00246" name="l00246"></a><span class="lineno">  246</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_I2C0 applies similarly to other array indexes)</span></div>
 345 <div class="line"><a id="l00247" name="l00247"></a><span class="lineno">  247</span>    _REG_(ACCESSCTRL_I2C0_OFFSET) <span class="comment">// ACCESSCTRL_I2C0</span></div>
 346 <div class="line"><a id="l00248" name="l00248"></a><span class="lineno">  248</span>    <span class="comment">// Control access to I2C0. Defaults to Secure access from any master.</span></div>
 347 <div class="line"><a id="l00249" name="l00249"></a><span class="lineno">  249</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, I2C0 can be accessed by the debugger, at...</span></div>
 348 <div class="line"><a id="l00250" name="l00250"></a><span class="lineno">  250</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, I2C0 can be accessed by the DMA, at...</span></div>
 349 <div class="line"><a id="l00251" name="l00251"></a><span class="lineno">  251</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, I2C0 can be accessed by core 1, at...</span></div>
 350 <div class="line"><a id="l00252" name="l00252"></a><span class="lineno">  252</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, I2C0 can be accessed by core 0, at...</span></div>
 351 <div class="line"><a id="l00253" name="l00253"></a><span class="lineno">  253</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, I2C0 can be accessed from a Secure, Privileged context</span></div>
 352 <div class="line"><a id="l00254" name="l00254"></a><span class="lineno">  254</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, I2C0 can be accessed from a...</span></div>
 353 <div class="line"><a id="l00255" name="l00255"></a><span class="lineno">  255</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, I2C0 can be accessed from a Non-secure, Privileged context</span></div>
 354 <div class="line"><a id="l00256" name="l00256"></a><span class="lineno">  256</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, I2C0 can be accessed from a...</span></div>
 355 <div class="line"><a id="l00257" name="l00257"></a><span class="lineno">  257</span>    io_rw_32 i2c[2];</div>
 356 <div class="line"><a id="l00258" name="l00258"></a><span class="lineno">  258</span> </div>
 357 <div class="line"><a id="l00259" name="l00259"></a><span class="lineno">  259</span>    _REG_(ACCESSCTRL_PWM_OFFSET) <span class="comment">// ACCESSCTRL_PWM</span></div>
 358 <div class="line"><a id="l00260" name="l00260"></a><span class="lineno">  260</span>    <span class="comment">// Control access to PWM. Defaults to Secure access from any master.</span></div>
 359 <div class="line"><a id="l00261" name="l00261"></a><span class="lineno">  261</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, PWM can be accessed by the debugger, at...</span></div>
 360 <div class="line"><a id="l00262" name="l00262"></a><span class="lineno">  262</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, PWM can be accessed by the DMA, at...</span></div>
 361 <div class="line"><a id="l00263" name="l00263"></a><span class="lineno">  263</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, PWM can be accessed by core 1, at...</span></div>
 362 <div class="line"><a id="l00264" name="l00264"></a><span class="lineno">  264</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, PWM can be accessed by core 0, at...</span></div>
 363 <div class="line"><a id="l00265" name="l00265"></a><span class="lineno">  265</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, PWM can be accessed from a Secure, Privileged context</span></div>
 364 <div class="line"><a id="l00266" name="l00266"></a><span class="lineno">  266</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, PWM can be accessed from a...</span></div>
 365 <div class="line"><a id="l00267" name="l00267"></a><span class="lineno">  267</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, PWM can be accessed from a Non-secure, Privileged context</span></div>
 366 <div class="line"><a id="l00268" name="l00268"></a><span class="lineno">  268</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, PWM can be accessed from a...</span></div>
 367 <div class="line"><a id="l00269" name="l00269"></a><span class="lineno">  269</span>    io_rw_32 pwm;</div>
 368 <div class="line"><a id="l00270" name="l00270"></a><span class="lineno">  270</span> </div>
 369 <div class="line"><a id="l00271" name="l00271"></a><span class="lineno">  271</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_SPI0 applies similarly to other array indexes)</span></div>
 370 <div class="line"><a id="l00272" name="l00272"></a><span class="lineno">  272</span>    _REG_(ACCESSCTRL_SPI0_OFFSET) <span class="comment">// ACCESSCTRL_SPI0</span></div>
 371 <div class="line"><a id="l00273" name="l00273"></a><span class="lineno">  273</span>    <span class="comment">// Control access to SPI0. Defaults to Secure access from any master.</span></div>
 372 <div class="line"><a id="l00274" name="l00274"></a><span class="lineno">  274</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, SPI0 can be accessed by the debugger, at...</span></div>
 373 <div class="line"><a id="l00275" name="l00275"></a><span class="lineno">  275</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, SPI0 can be accessed by the DMA, at...</span></div>
 374 <div class="line"><a id="l00276" name="l00276"></a><span class="lineno">  276</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, SPI0 can be accessed by core 1, at...</span></div>
 375 <div class="line"><a id="l00277" name="l00277"></a><span class="lineno">  277</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, SPI0 can be accessed by core 0, at...</span></div>
 376 <div class="line"><a id="l00278" name="l00278"></a><span class="lineno">  278</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, SPI0 can be accessed from a Secure, Privileged context</span></div>
 377 <div class="line"><a id="l00279" name="l00279"></a><span class="lineno">  279</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, SPI0 can be accessed from a...</span></div>
 378 <div class="line"><a id="l00280" name="l00280"></a><span class="lineno">  280</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, SPI0 can be accessed from a Non-secure, Privileged context</span></div>
 379 <div class="line"><a id="l00281" name="l00281"></a><span class="lineno">  281</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, SPI0 can be accessed from a...</span></div>
 380 <div class="line"><a id="l00282" name="l00282"></a><span class="lineno">  282</span>    io_rw_32 spi[2];</div>
 381 <div class="line"><a id="l00283" name="l00283"></a><span class="lineno">  283</span> </div>
 382 <div class="line"><a id="l00284" name="l00284"></a><span class="lineno">  284</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_TIMER0 applies similarly to other array indexes)</span></div>
 383 <div class="line"><a id="l00285" name="l00285"></a><span class="lineno">  285</span>    _REG_(ACCESSCTRL_TIMER0_OFFSET) <span class="comment">// ACCESSCTRL_TIMER0</span></div>
 384 <div class="line"><a id="l00286" name="l00286"></a><span class="lineno">  286</span>    <span class="comment">// Control access to TIMER0. Defaults to Secure access from any master.</span></div>
 385 <div class="line"><a id="l00287" name="l00287"></a><span class="lineno">  287</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, TIMER0 can be accessed by the debugger, at...</span></div>
 386 <div class="line"><a id="l00288" name="l00288"></a><span class="lineno">  288</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, TIMER0 can be accessed by the DMA, at...</span></div>
 387 <div class="line"><a id="l00289" name="l00289"></a><span class="lineno">  289</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, TIMER0 can be accessed by core 1, at...</span></div>
 388 <div class="line"><a id="l00290" name="l00290"></a><span class="lineno">  290</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, TIMER0 can be accessed by core 0, at...</span></div>
 389 <div class="line"><a id="l00291" name="l00291"></a><span class="lineno">  291</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, TIMER0 can be accessed from a Secure, Privileged context</span></div>
 390 <div class="line"><a id="l00292" name="l00292"></a><span class="lineno">  292</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, TIMER0 can be accessed from a...</span></div>
 391 <div class="line"><a id="l00293" name="l00293"></a><span class="lineno">  293</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, TIMER0 can be accessed from a Non-secure,...</span></div>
 392 <div class="line"><a id="l00294" name="l00294"></a><span class="lineno">  294</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, TIMER0 can be accessed from a...</span></div>
 393 <div class="line"><a id="l00295" name="l00295"></a><span class="lineno">  295</span>    io_rw_32 timer[2];</div>
 394 <div class="line"><a id="l00296" name="l00296"></a><span class="lineno">  296</span> </div>
 395 <div class="line"><a id="l00297" name="l00297"></a><span class="lineno">  297</span>    <span class="comment">// (Description copied from array index 0 register ACCESSCTRL_UART0 applies similarly to other array indexes)</span></div>
 396 <div class="line"><a id="l00298" name="l00298"></a><span class="lineno">  298</span>    _REG_(ACCESSCTRL_UART0_OFFSET) <span class="comment">// ACCESSCTRL_UART0</span></div>
 397 <div class="line"><a id="l00299" name="l00299"></a><span class="lineno">  299</span>    <span class="comment">// Control access to UART0. Defaults to Secure access from any master.</span></div>
 398 <div class="line"><a id="l00300" name="l00300"></a><span class="lineno">  300</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, UART0 can be accessed by the debugger, at...</span></div>
 399 <div class="line"><a id="l00301" name="l00301"></a><span class="lineno">  301</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, UART0 can be accessed by the DMA, at...</span></div>
 400 <div class="line"><a id="l00302" name="l00302"></a><span class="lineno">  302</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, UART0 can be accessed by core 1, at...</span></div>
 401 <div class="line"><a id="l00303" name="l00303"></a><span class="lineno">  303</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, UART0 can be accessed by core 0, at...</span></div>
 402 <div class="line"><a id="l00304" name="l00304"></a><span class="lineno">  304</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, UART0 can be accessed from a Secure, Privileged context</span></div>
 403 <div class="line"><a id="l00305" name="l00305"></a><span class="lineno">  305</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, UART0 can be accessed from a...</span></div>
 404 <div class="line"><a id="l00306" name="l00306"></a><span class="lineno">  306</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, UART0 can be accessed from a Non-secure, Privileged context</span></div>
 405 <div class="line"><a id="l00307" name="l00307"></a><span class="lineno">  307</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, UART0 can be accessed from a...</span></div>
 406 <div class="line"><a id="l00308" name="l00308"></a><span class="lineno">  308</span>    io_rw_32 uart[2];</div>
 407 <div class="line"><a id="l00309" name="l00309"></a><span class="lineno">  309</span> </div>
 408 <div class="line"><a id="l00310" name="l00310"></a><span class="lineno">  310</span>    _REG_(ACCESSCTRL_OTP_OFFSET) <span class="comment">// ACCESSCTRL_OTP</span></div>
 409 <div class="line"><a id="l00311" name="l00311"></a><span class="lineno">  311</span>    <span class="comment">// Control access to OTP. Defaults to Secure access from any master.</span></div>
 410 <div class="line"><a id="l00312" name="l00312"></a><span class="lineno">  312</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, OTP can be accessed by the debugger, at...</span></div>
 411 <div class="line"><a id="l00313" name="l00313"></a><span class="lineno">  313</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, OTP can be accessed by the DMA, at...</span></div>
 412 <div class="line"><a id="l00314" name="l00314"></a><span class="lineno">  314</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, OTP can be accessed by core 1, at...</span></div>
 413 <div class="line"><a id="l00315" name="l00315"></a><span class="lineno">  315</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, OTP can be accessed by core 0, at...</span></div>
 414 <div class="line"><a id="l00316" name="l00316"></a><span class="lineno">  316</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, OTP can be accessed from a Secure, Privileged context</span></div>
 415 <div class="line"><a id="l00317" name="l00317"></a><span class="lineno">  317</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, OTP can be accessed from a...</span></div>
 416 <div class="line"><a id="l00318" name="l00318"></a><span class="lineno">  318</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, OTP can be accessed from a Non-secure, Privileged context</span></div>
 417 <div class="line"><a id="l00319" name="l00319"></a><span class="lineno">  319</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, OTP can be accessed from a...</span></div>
 418 <div class="line"><a id="l00320" name="l00320"></a><span class="lineno">  320</span>    io_rw_32 otp;</div>
 419 <div class="line"><a id="l00321" name="l00321"></a><span class="lineno">  321</span> </div>
 420 <div class="line"><a id="l00322" name="l00322"></a><span class="lineno">  322</span>    _REG_(ACCESSCTRL_TBMAN_OFFSET) <span class="comment">// ACCESSCTRL_TBMAN</span></div>
 421 <div class="line"><a id="l00323" name="l00323"></a><span class="lineno">  323</span>    <span class="comment">// Control access to TBMAN. Defaults to Secure access from any master.</span></div>
 422 <div class="line"><a id="l00324" name="l00324"></a><span class="lineno">  324</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, TBMAN can be accessed by the debugger, at...</span></div>
 423 <div class="line"><a id="l00325" name="l00325"></a><span class="lineno">  325</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, TBMAN can be accessed by the DMA, at...</span></div>
 424 <div class="line"><a id="l00326" name="l00326"></a><span class="lineno">  326</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, TBMAN can be accessed by core 1, at...</span></div>
 425 <div class="line"><a id="l00327" name="l00327"></a><span class="lineno">  327</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, TBMAN can be accessed by core 0, at...</span></div>
 426 <div class="line"><a id="l00328" name="l00328"></a><span class="lineno">  328</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, TBMAN can be accessed from a Secure, Privileged context</span></div>
 427 <div class="line"><a id="l00329" name="l00329"></a><span class="lineno">  329</span>    <span class="comment">// 0x00000004 [2]     SU           (1) If 1, and SP is also set, TBMAN can be accessed from a...</span></div>
 428 <div class="line"><a id="l00330" name="l00330"></a><span class="lineno">  330</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, TBMAN can be accessed from a Non-secure, Privileged context</span></div>
 429 <div class="line"><a id="l00331" name="l00331"></a><span class="lineno">  331</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, TBMAN can be accessed from a...</span></div>
 430 <div class="line"><a id="l00332" name="l00332"></a><span class="lineno">  332</span>    io_rw_32 tbman;</div>
 431 <div class="line"><a id="l00333" name="l00333"></a><span class="lineno">  333</span> </div>
 432 <div class="line"><a id="l00334" name="l00334"></a><span class="lineno">  334</span>    _REG_(ACCESSCTRL_POWMAN_OFFSET) <span class="comment">// ACCESSCTRL_POWMAN</span></div>
 433 <div class="line"><a id="l00335" name="l00335"></a><span class="lineno">  335</span>    <span class="comment">// Control access to POWMAN. Defaults to Secure, Privileged processor or debug access only.</span></div>
 434 <div class="line"><a id="l00336" name="l00336"></a><span class="lineno">  336</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, POWMAN can be accessed by the debugger, at...</span></div>
 435 <div class="line"><a id="l00337" name="l00337"></a><span class="lineno">  337</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, POWMAN can be accessed by the DMA, at...</span></div>
 436 <div class="line"><a id="l00338" name="l00338"></a><span class="lineno">  338</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, POWMAN can be accessed by core 1, at...</span></div>
 437 <div class="line"><a id="l00339" name="l00339"></a><span class="lineno">  339</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, POWMAN can be accessed by core 0, at...</span></div>
 438 <div class="line"><a id="l00340" name="l00340"></a><span class="lineno">  340</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, POWMAN can be accessed from a Secure, Privileged context</span></div>
 439 <div class="line"><a id="l00341" name="l00341"></a><span class="lineno">  341</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, POWMAN can be accessed from a...</span></div>
 440 <div class="line"><a id="l00342" name="l00342"></a><span class="lineno">  342</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, POWMAN can be accessed from a Non-secure,...</span></div>
 441 <div class="line"><a id="l00343" name="l00343"></a><span class="lineno">  343</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, POWMAN can be accessed from a...</span></div>
 442 <div class="line"><a id="l00344" name="l00344"></a><span class="lineno">  344</span>    io_rw_32 powman;</div>
 443 <div class="line"><a id="l00345" name="l00345"></a><span class="lineno">  345</span> </div>
 444 <div class="line"><a id="l00346" name="l00346"></a><span class="lineno">  346</span>    _REG_(ACCESSCTRL_TRNG_OFFSET) <span class="comment">// ACCESSCTRL_TRNG</span></div>
 445 <div class="line"><a id="l00347" name="l00347"></a><span class="lineno">  347</span>    <span class="comment">// Control access to TRNG. Defaults to Secure, Privileged processor or debug access only.</span></div>
 446 <div class="line"><a id="l00348" name="l00348"></a><span class="lineno">  348</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, TRNG can be accessed by the debugger, at...</span></div>
 447 <div class="line"><a id="l00349" name="l00349"></a><span class="lineno">  349</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, TRNG can be accessed by the DMA, at...</span></div>
 448 <div class="line"><a id="l00350" name="l00350"></a><span class="lineno">  350</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, TRNG can be accessed by core 1, at...</span></div>
 449 <div class="line"><a id="l00351" name="l00351"></a><span class="lineno">  351</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, TRNG can be accessed by core 0, at...</span></div>
 450 <div class="line"><a id="l00352" name="l00352"></a><span class="lineno">  352</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, TRNG can be accessed from a Secure, Privileged context</span></div>
 451 <div class="line"><a id="l00353" name="l00353"></a><span class="lineno">  353</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, TRNG can be accessed from a...</span></div>
 452 <div class="line"><a id="l00354" name="l00354"></a><span class="lineno">  354</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, TRNG can be accessed from a Non-secure, Privileged context</span></div>
 453 <div class="line"><a id="l00355" name="l00355"></a><span class="lineno">  355</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, TRNG can be accessed from a...</span></div>
 454 <div class="line"><a id="l00356" name="l00356"></a><span class="lineno">  356</span>    io_rw_32 trng;</div>
 455 <div class="line"><a id="l00357" name="l00357"></a><span class="lineno">  357</span> </div>
 456 <div class="line"><a id="l00358" name="l00358"></a><span class="lineno">  358</span>    _REG_(ACCESSCTRL_SHA256_OFFSET) <span class="comment">// ACCESSCTRL_SHA256</span></div>
 457 <div class="line"><a id="l00359" name="l00359"></a><span class="lineno">  359</span>    <span class="comment">// Control access to SHA256. Defaults to Secure, Privileged access only.</span></div>
 458 <div class="line"><a id="l00360" name="l00360"></a><span class="lineno">  360</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, SHA256 can be accessed by the debugger, at...</span></div>
 459 <div class="line"><a id="l00361" name="l00361"></a><span class="lineno">  361</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, SHA256 can be accessed by the DMA, at...</span></div>
 460 <div class="line"><a id="l00362" name="l00362"></a><span class="lineno">  362</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, SHA256 can be accessed by core 1, at...</span></div>
 461 <div class="line"><a id="l00363" name="l00363"></a><span class="lineno">  363</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, SHA256 can be accessed by core 0, at...</span></div>
 462 <div class="line"><a id="l00364" name="l00364"></a><span class="lineno">  364</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, SHA256 can be accessed from a Secure, Privileged context</span></div>
 463 <div class="line"><a id="l00365" name="l00365"></a><span class="lineno">  365</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, SHA256 can be accessed from a...</span></div>
 464 <div class="line"><a id="l00366" name="l00366"></a><span class="lineno">  366</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, SHA256 can be accessed from a Non-secure,...</span></div>
 465 <div class="line"><a id="l00367" name="l00367"></a><span class="lineno">  367</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, SHA256 can be accessed from a...</span></div>
 466 <div class="line"><a id="l00368" name="l00368"></a><span class="lineno">  368</span>    io_rw_32 sha256;</div>
 467 <div class="line"><a id="l00369" name="l00369"></a><span class="lineno">  369</span> </div>
 468 <div class="line"><a id="l00370" name="l00370"></a><span class="lineno">  370</span>    _REG_(ACCESSCTRL_SYSCFG_OFFSET) <span class="comment">// ACCESSCTRL_SYSCFG</span></div>
 469 <div class="line"><a id="l00371" name="l00371"></a><span class="lineno">  371</span>    <span class="comment">// Control access to SYSCFG. Defaults to Secure, Privileged processor or debug access only.</span></div>
 470 <div class="line"><a id="l00372" name="l00372"></a><span class="lineno">  372</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, SYSCFG can be accessed by the debugger, at...</span></div>
 471 <div class="line"><a id="l00373" name="l00373"></a><span class="lineno">  373</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, SYSCFG can be accessed by the DMA, at...</span></div>
 472 <div class="line"><a id="l00374" name="l00374"></a><span class="lineno">  374</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, SYSCFG can be accessed by core 1, at...</span></div>
 473 <div class="line"><a id="l00375" name="l00375"></a><span class="lineno">  375</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, SYSCFG can be accessed by core 0, at...</span></div>
 474 <div class="line"><a id="l00376" name="l00376"></a><span class="lineno">  376</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, SYSCFG can be accessed from a Secure, Privileged context</span></div>
 475 <div class="line"><a id="l00377" name="l00377"></a><span class="lineno">  377</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, SYSCFG can be accessed from a...</span></div>
 476 <div class="line"><a id="l00378" name="l00378"></a><span class="lineno">  378</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, SYSCFG can be accessed from a Non-secure,...</span></div>
 477 <div class="line"><a id="l00379" name="l00379"></a><span class="lineno">  379</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, SYSCFG can be accessed from a...</span></div>
 478 <div class="line"><a id="l00380" name="l00380"></a><span class="lineno">  380</span>    io_rw_32 syscfg;</div>
 479 <div class="line"><a id="l00381" name="l00381"></a><span class="lineno">  381</span> </div>
 480 <div class="line"><a id="l00382" name="l00382"></a><span class="lineno">  382</span>    _REG_(ACCESSCTRL_CLOCKS_OFFSET) <span class="comment">// ACCESSCTRL_CLOCKS</span></div>
 481 <div class="line"><a id="l00383" name="l00383"></a><span class="lineno">  383</span>    <span class="comment">// Control access to CLOCKS. Defaults to Secure, Privileged processor or debug access only.</span></div>
 482 <div class="line"><a id="l00384" name="l00384"></a><span class="lineno">  384</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, CLOCKS can be accessed by the debugger, at...</span></div>
 483 <div class="line"><a id="l00385" name="l00385"></a><span class="lineno">  385</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, CLOCKS can be accessed by the DMA, at...</span></div>
 484 <div class="line"><a id="l00386" name="l00386"></a><span class="lineno">  386</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, CLOCKS can be accessed by core 1, at...</span></div>
 485 <div class="line"><a id="l00387" name="l00387"></a><span class="lineno">  387</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, CLOCKS can be accessed by core 0, at...</span></div>
 486 <div class="line"><a id="l00388" name="l00388"></a><span class="lineno">  388</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, CLOCKS can be accessed from a Secure, Privileged context</span></div>
 487 <div class="line"><a id="l00389" name="l00389"></a><span class="lineno">  389</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, CLOCKS can be accessed from a...</span></div>
 488 <div class="line"><a id="l00390" name="l00390"></a><span class="lineno">  390</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, CLOCKS can be accessed from a Non-secure,...</span></div>
 489 <div class="line"><a id="l00391" name="l00391"></a><span class="lineno">  391</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, CLOCKS can be accessed from a...</span></div>
 490 <div class="line"><a id="l00392" name="l00392"></a><span class="lineno">  392</span>    io_rw_32 clocks;</div>
 491 <div class="line"><a id="l00393" name="l00393"></a><span class="lineno">  393</span> </div>
 492 <div class="line"><a id="l00394" name="l00394"></a><span class="lineno">  394</span>    _REG_(ACCESSCTRL_XOSC_OFFSET) <span class="comment">// ACCESSCTRL_XOSC</span></div>
 493 <div class="line"><a id="l00395" name="l00395"></a><span class="lineno">  395</span>    <span class="comment">// Control access to XOSC. Defaults to Secure, Privileged processor or debug access only.</span></div>
 494 <div class="line"><a id="l00396" name="l00396"></a><span class="lineno">  396</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, XOSC can be accessed by the debugger, at...</span></div>
 495 <div class="line"><a id="l00397" name="l00397"></a><span class="lineno">  397</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, XOSC can be accessed by the DMA, at...</span></div>
 496 <div class="line"><a id="l00398" name="l00398"></a><span class="lineno">  398</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, XOSC can be accessed by core 1, at...</span></div>
 497 <div class="line"><a id="l00399" name="l00399"></a><span class="lineno">  399</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, XOSC can be accessed by core 0, at...</span></div>
 498 <div class="line"><a id="l00400" name="l00400"></a><span class="lineno">  400</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, XOSC can be accessed from a Secure, Privileged context</span></div>
 499 <div class="line"><a id="l00401" name="l00401"></a><span class="lineno">  401</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, XOSC can be accessed from a...</span></div>
 500 <div class="line"><a id="l00402" name="l00402"></a><span class="lineno">  402</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, XOSC can be accessed from a Non-secure, Privileged context</span></div>
 501 <div class="line"><a id="l00403" name="l00403"></a><span class="lineno">  403</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, XOSC can be accessed from a...</span></div>
 502 <div class="line"><a id="l00404" name="l00404"></a><span class="lineno">  404</span>    io_rw_32 xosc;</div>
 503 <div class="line"><a id="l00405" name="l00405"></a><span class="lineno">  405</span> </div>
 504 <div class="line"><a id="l00406" name="l00406"></a><span class="lineno">  406</span>    _REG_(ACCESSCTRL_ROSC_OFFSET) <span class="comment">// ACCESSCTRL_ROSC</span></div>
 505 <div class="line"><a id="l00407" name="l00407"></a><span class="lineno">  407</span>    <span class="comment">// Control access to ROSC. Defaults to Secure, Privileged processor or debug access only.</span></div>
 506 <div class="line"><a id="l00408" name="l00408"></a><span class="lineno">  408</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, ROSC can be accessed by the debugger, at...</span></div>
 507 <div class="line"><a id="l00409" name="l00409"></a><span class="lineno">  409</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, ROSC can be accessed by the DMA, at...</span></div>
 508 <div class="line"><a id="l00410" name="l00410"></a><span class="lineno">  410</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, ROSC can be accessed by core 1, at...</span></div>
 509 <div class="line"><a id="l00411" name="l00411"></a><span class="lineno">  411</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, ROSC can be accessed by core 0, at...</span></div>
 510 <div class="line"><a id="l00412" name="l00412"></a><span class="lineno">  412</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, ROSC can be accessed from a Secure, Privileged context</span></div>
 511 <div class="line"><a id="l00413" name="l00413"></a><span class="lineno">  413</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, ROSC can be accessed from a...</span></div>
 512 <div class="line"><a id="l00414" name="l00414"></a><span class="lineno">  414</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, ROSC can be accessed from a Non-secure, Privileged context</span></div>
 513 <div class="line"><a id="l00415" name="l00415"></a><span class="lineno">  415</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, ROSC can be accessed from a...</span></div>
 514 <div class="line"><a id="l00416" name="l00416"></a><span class="lineno">  416</span>    io_rw_32 rosc;</div>
 515 <div class="line"><a id="l00417" name="l00417"></a><span class="lineno">  417</span> </div>
 516 <div class="line"><a id="l00418" name="l00418"></a><span class="lineno">  418</span>    _REG_(ACCESSCTRL_PLL_SYS_OFFSET) <span class="comment">// ACCESSCTRL_PLL_SYS</span></div>
 517 <div class="line"><a id="l00419" name="l00419"></a><span class="lineno">  419</span>    <span class="comment">// Control access to PLL_SYS. Defaults to Secure, Privileged processor or debug access only.</span></div>
 518 <div class="line"><a id="l00420" name="l00420"></a><span class="lineno">  420</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, PLL_SYS can be accessed by the debugger, at...</span></div>
 519 <div class="line"><a id="l00421" name="l00421"></a><span class="lineno">  421</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, PLL_SYS can be accessed by the DMA, at...</span></div>
 520 <div class="line"><a id="l00422" name="l00422"></a><span class="lineno">  422</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, PLL_SYS can be accessed by core 1, at...</span></div>
 521 <div class="line"><a id="l00423" name="l00423"></a><span class="lineno">  423</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, PLL_SYS can be accessed by core 0, at...</span></div>
 522 <div class="line"><a id="l00424" name="l00424"></a><span class="lineno">  424</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, PLL_SYS can be accessed from a Secure, Privileged context</span></div>
 523 <div class="line"><a id="l00425" name="l00425"></a><span class="lineno">  425</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, PLL_SYS can be accessed from a...</span></div>
 524 <div class="line"><a id="l00426" name="l00426"></a><span class="lineno">  426</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, PLL_SYS can be accessed from a Non-secure,...</span></div>
 525 <div class="line"><a id="l00427" name="l00427"></a><span class="lineno">  427</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, PLL_SYS can be accessed from...</span></div>
 526 <div class="line"><a id="l00428" name="l00428"></a><span class="lineno">  428</span>    io_rw_32 pll_sys;</div>
 527 <div class="line"><a id="l00429" name="l00429"></a><span class="lineno">  429</span> </div>
 528 <div class="line"><a id="l00430" name="l00430"></a><span class="lineno">  430</span>    _REG_(ACCESSCTRL_PLL_USB_OFFSET) <span class="comment">// ACCESSCTRL_PLL_USB</span></div>
 529 <div class="line"><a id="l00431" name="l00431"></a><span class="lineno">  431</span>    <span class="comment">// Control access to PLL_USB. Defaults to Secure, Privileged processor or debug access only.</span></div>
 530 <div class="line"><a id="l00432" name="l00432"></a><span class="lineno">  432</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, PLL_USB can be accessed by the debugger, at...</span></div>
 531 <div class="line"><a id="l00433" name="l00433"></a><span class="lineno">  433</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, PLL_USB can be accessed by the DMA, at...</span></div>
 532 <div class="line"><a id="l00434" name="l00434"></a><span class="lineno">  434</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, PLL_USB can be accessed by core 1, at...</span></div>
 533 <div class="line"><a id="l00435" name="l00435"></a><span class="lineno">  435</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, PLL_USB can be accessed by core 0, at...</span></div>
 534 <div class="line"><a id="l00436" name="l00436"></a><span class="lineno">  436</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, PLL_USB can be accessed from a Secure, Privileged context</span></div>
 535 <div class="line"><a id="l00437" name="l00437"></a><span class="lineno">  437</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, PLL_USB can be accessed from a...</span></div>
 536 <div class="line"><a id="l00438" name="l00438"></a><span class="lineno">  438</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, PLL_USB can be accessed from a Non-secure,...</span></div>
 537 <div class="line"><a id="l00439" name="l00439"></a><span class="lineno">  439</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, PLL_USB can be accessed from...</span></div>
 538 <div class="line"><a id="l00440" name="l00440"></a><span class="lineno">  440</span>    io_rw_32 pll_usb;</div>
 539 <div class="line"><a id="l00441" name="l00441"></a><span class="lineno">  441</span> </div>
 540 <div class="line"><a id="l00442" name="l00442"></a><span class="lineno">  442</span>    _REG_(ACCESSCTRL_TICKS_OFFSET) <span class="comment">// ACCESSCTRL_TICKS</span></div>
 541 <div class="line"><a id="l00443" name="l00443"></a><span class="lineno">  443</span>    <span class="comment">// Control access to TICKS. Defaults to Secure, Privileged processor or debug access only.</span></div>
 542 <div class="line"><a id="l00444" name="l00444"></a><span class="lineno">  444</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, TICKS can be accessed by the debugger, at...</span></div>
 543 <div class="line"><a id="l00445" name="l00445"></a><span class="lineno">  445</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, TICKS can be accessed by the DMA, at...</span></div>
 544 <div class="line"><a id="l00446" name="l00446"></a><span class="lineno">  446</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, TICKS can be accessed by core 1, at...</span></div>
 545 <div class="line"><a id="l00447" name="l00447"></a><span class="lineno">  447</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, TICKS can be accessed by core 0, at...</span></div>
 546 <div class="line"><a id="l00448" name="l00448"></a><span class="lineno">  448</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, TICKS can be accessed from a Secure, Privileged context</span></div>
 547 <div class="line"><a id="l00449" name="l00449"></a><span class="lineno">  449</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, TICKS can be accessed from a...</span></div>
 548 <div class="line"><a id="l00450" name="l00450"></a><span class="lineno">  450</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, TICKS can be accessed from a Non-secure, Privileged context</span></div>
 549 <div class="line"><a id="l00451" name="l00451"></a><span class="lineno">  451</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, TICKS can be accessed from a...</span></div>
 550 <div class="line"><a id="l00452" name="l00452"></a><span class="lineno">  452</span>    io_rw_32 ticks;</div>
 551 <div class="line"><a id="l00453" name="l00453"></a><span class="lineno">  453</span> </div>
 552 <div class="line"><a id="l00454" name="l00454"></a><span class="lineno">  454</span>    _REG_(ACCESSCTRL_WATCHDOG_OFFSET) <span class="comment">// ACCESSCTRL_WATCHDOG</span></div>
 553 <div class="line"><a id="l00455" name="l00455"></a><span class="lineno">  455</span>    <span class="comment">// Control access to WATCHDOG. Defaults to Secure, Privileged processor or debug access only.</span></div>
 554 <div class="line"><a id="l00456" name="l00456"></a><span class="lineno">  456</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, WATCHDOG can be accessed by the debugger, at...</span></div>
 555 <div class="line"><a id="l00457" name="l00457"></a><span class="lineno">  457</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, WATCHDOG can be accessed by the DMA, at...</span></div>
 556 <div class="line"><a id="l00458" name="l00458"></a><span class="lineno">  458</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, WATCHDOG can be accessed by core 1, at...</span></div>
 557 <div class="line"><a id="l00459" name="l00459"></a><span class="lineno">  459</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, WATCHDOG can be accessed by core 0, at...</span></div>
 558 <div class="line"><a id="l00460" name="l00460"></a><span class="lineno">  460</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, WATCHDOG can be accessed from a Secure, Privileged context</span></div>
 559 <div class="line"><a id="l00461" name="l00461"></a><span class="lineno">  461</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, WATCHDOG can be accessed from...</span></div>
 560 <div class="line"><a id="l00462" name="l00462"></a><span class="lineno">  462</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, WATCHDOG can be accessed from a Non-secure,...</span></div>
 561 <div class="line"><a id="l00463" name="l00463"></a><span class="lineno">  463</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, WATCHDOG can be accessed from...</span></div>
 562 <div class="line"><a id="l00464" name="l00464"></a><span class="lineno">  464</span>    io_rw_32 watchdog;</div>
 563 <div class="line"><a id="l00465" name="l00465"></a><span class="lineno">  465</span> </div>
 564 <div class="line"><a id="l00466" name="l00466"></a><span class="lineno">  466</span>    _REG_(ACCESSCTRL_RSM_OFFSET) <span class="comment">// ACCESSCTRL_RSM</span></div>
 565 <div class="line"><a id="l00467" name="l00467"></a><span class="lineno">  467</span>    <span class="comment">// Control access to RSM. Defaults to Secure, Privileged processor or debug access only.</span></div>
 566 <div class="line"><a id="l00468" name="l00468"></a><span class="lineno">  468</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, RSM can be accessed by the debugger, at...</span></div>
 567 <div class="line"><a id="l00469" name="l00469"></a><span class="lineno">  469</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, RSM can be accessed by the DMA, at...</span></div>
 568 <div class="line"><a id="l00470" name="l00470"></a><span class="lineno">  470</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, RSM can be accessed by core 1, at...</span></div>
 569 <div class="line"><a id="l00471" name="l00471"></a><span class="lineno">  471</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, RSM can be accessed by core 0, at...</span></div>
 570 <div class="line"><a id="l00472" name="l00472"></a><span class="lineno">  472</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, RSM can be accessed from a Secure, Privileged context</span></div>
 571 <div class="line"><a id="l00473" name="l00473"></a><span class="lineno">  473</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, RSM can be accessed from a...</span></div>
 572 <div class="line"><a id="l00474" name="l00474"></a><span class="lineno">  474</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, RSM can be accessed from a Non-secure, Privileged context</span></div>
 573 <div class="line"><a id="l00475" name="l00475"></a><span class="lineno">  475</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, RSM can be accessed from a...</span></div>
 574 <div class="line"><a id="l00476" name="l00476"></a><span class="lineno">  476</span>    io_rw_32 rsm;</div>
 575 <div class="line"><a id="l00477" name="l00477"></a><span class="lineno">  477</span> </div>
 576 <div class="line"><a id="l00478" name="l00478"></a><span class="lineno">  478</span>    _REG_(ACCESSCTRL_XIP_CTRL_OFFSET) <span class="comment">// ACCESSCTRL_XIP_CTRL</span></div>
 577 <div class="line"><a id="l00479" name="l00479"></a><span class="lineno">  479</span>    <span class="comment">// Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only.</span></div>
 578 <div class="line"><a id="l00480" name="l00480"></a><span class="lineno">  480</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, XIP_CTRL can be accessed by the debugger, at...</span></div>
 579 <div class="line"><a id="l00481" name="l00481"></a><span class="lineno">  481</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, XIP_CTRL can be accessed by the DMA, at...</span></div>
 580 <div class="line"><a id="l00482" name="l00482"></a><span class="lineno">  482</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, XIP_CTRL can be accessed by core 1, at...</span></div>
 581 <div class="line"><a id="l00483" name="l00483"></a><span class="lineno">  483</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, XIP_CTRL can be accessed by core 0, at...</span></div>
 582 <div class="line"><a id="l00484" name="l00484"></a><span class="lineno">  484</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, XIP_CTRL can be accessed from a Secure, Privileged context</span></div>
 583 <div class="line"><a id="l00485" name="l00485"></a><span class="lineno">  485</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, XIP_CTRL can be accessed from...</span></div>
 584 <div class="line"><a id="l00486" name="l00486"></a><span class="lineno">  486</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, XIP_CTRL can be accessed from a Non-secure,...</span></div>
 585 <div class="line"><a id="l00487" name="l00487"></a><span class="lineno">  487</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, XIP_CTRL can be accessed from...</span></div>
 586 <div class="line"><a id="l00488" name="l00488"></a><span class="lineno">  488</span>    io_rw_32 xip_ctrl;</div>
 587 <div class="line"><a id="l00489" name="l00489"></a><span class="lineno">  489</span> </div>
 588 <div class="line"><a id="l00490" name="l00490"></a><span class="lineno">  490</span>    _REG_(ACCESSCTRL_XIP_QMI_OFFSET) <span class="comment">// ACCESSCTRL_XIP_QMI</span></div>
 589 <div class="line"><a id="l00491" name="l00491"></a><span class="lineno">  491</span>    <span class="comment">// Control access to XIP_QMI. Defaults to Secure, Privileged processor or debug access only.</span></div>
 590 <div class="line"><a id="l00492" name="l00492"></a><span class="lineno">  492</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, XIP_QMI can be accessed by the debugger, at...</span></div>
 591 <div class="line"><a id="l00493" name="l00493"></a><span class="lineno">  493</span>    <span class="comment">// 0x00000040 [6]     DMA          (0) If 1, XIP_QMI can be accessed by the DMA, at...</span></div>
 592 <div class="line"><a id="l00494" name="l00494"></a><span class="lineno">  494</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, XIP_QMI can be accessed by core 1, at...</span></div>
 593 <div class="line"><a id="l00495" name="l00495"></a><span class="lineno">  495</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, XIP_QMI can be accessed by core 0, at...</span></div>
 594 <div class="line"><a id="l00496" name="l00496"></a><span class="lineno">  496</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, XIP_QMI can be accessed from a Secure, Privileged context</span></div>
 595 <div class="line"><a id="l00497" name="l00497"></a><span class="lineno">  497</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, XIP_QMI can be accessed from a...</span></div>
 596 <div class="line"><a id="l00498" name="l00498"></a><span class="lineno">  498</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, XIP_QMI can be accessed from a Non-secure,...</span></div>
 597 <div class="line"><a id="l00499" name="l00499"></a><span class="lineno">  499</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, XIP_QMI can be accessed from...</span></div>
 598 <div class="line"><a id="l00500" name="l00500"></a><span class="lineno">  500</span>    io_rw_32 xip_qmi;</div>
 599 <div class="line"><a id="l00501" name="l00501"></a><span class="lineno">  501</span> </div>
 600 <div class="line"><a id="l00502" name="l00502"></a><span class="lineno">  502</span>    _REG_(ACCESSCTRL_XIP_AUX_OFFSET) <span class="comment">// ACCESSCTRL_XIP_AUX</span></div>
 601 <div class="line"><a id="l00503" name="l00503"></a><span class="lineno">  503</span>    <span class="comment">// Control access to XIP_AUX. Defaults to Secure, Privileged access only.</span></div>
 602 <div class="line"><a id="l00504" name="l00504"></a><span class="lineno">  504</span>    <span class="comment">// 0x00000080 [7]     DBG          (1) If 1, XIP_AUX can be accessed by the debugger, at...</span></div>
 603 <div class="line"><a id="l00505" name="l00505"></a><span class="lineno">  505</span>    <span class="comment">// 0x00000040 [6]     DMA          (1) If 1, XIP_AUX can be accessed by the DMA, at...</span></div>
 604 <div class="line"><a id="l00506" name="l00506"></a><span class="lineno">  506</span>    <span class="comment">// 0x00000020 [5]     CORE1        (1) If 1, XIP_AUX can be accessed by core 1, at...</span></div>
 605 <div class="line"><a id="l00507" name="l00507"></a><span class="lineno">  507</span>    <span class="comment">// 0x00000010 [4]     CORE0        (1) If 1, XIP_AUX can be accessed by core 0, at...</span></div>
 606 <div class="line"><a id="l00508" name="l00508"></a><span class="lineno">  508</span>    <span class="comment">// 0x00000008 [3]     SP           (1) If 1, XIP_AUX can be accessed from a Secure, Privileged context</span></div>
 607 <div class="line"><a id="l00509" name="l00509"></a><span class="lineno">  509</span>    <span class="comment">// 0x00000004 [2]     SU           (0) If 1, and SP is also set, XIP_AUX can be accessed from a...</span></div>
 608 <div class="line"><a id="l00510" name="l00510"></a><span class="lineno">  510</span>    <span class="comment">// 0x00000002 [1]     NSP          (0) If 1, XIP_AUX can be accessed from a Non-secure,...</span></div>
 609 <div class="line"><a id="l00511" name="l00511"></a><span class="lineno">  511</span>    <span class="comment">// 0x00000001 [0]     NSU          (0) If 1, and NSP is also set, XIP_AUX can be accessed from...</span></div>
 610 <div class="line"><a id="l00512" name="l00512"></a><span class="lineno">  512</span>    io_rw_32 xip_aux;</div>
 611 <div class="line"><a id="l00513" name="l00513"></a><span class="lineno">  513</span>} <a class="code hl_struct" href="structaccessctrl__hw__t.html">accessctrl_hw_t</a>;</div>
 612 <div class="line"><a id="l00514" name="l00514"></a><span class="lineno">  514</span> </div>
 613 <div class="line"><a id="l00515" name="l00515"></a><span class="lineno">  515</span><span class="preprocessor">#define accessctrl_hw ((accessctrl_hw_t *)ACCESSCTRL_BASE)</span></div>
 614 <div class="line"><a id="l00516" name="l00516"></a><span class="lineno">  516</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structaccessctrl__hw__t.html">accessctrl_hw_t</a>) == 0x00ec, <span class="stringliteral">&quot;&quot;</span>);</div>
 615 <div class="line"><a id="l00517" name="l00517"></a><span class="lineno">  517</span> </div>
 616 <div class="line"><a id="l00518" name="l00518"></a><span class="lineno">  518</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_ACCESSCTRL_H</span></div>
 617 <div class="line"><a id="l00519" name="l00519"></a><span class="lineno">  519</span> </div>
 618 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 619 <div class="ttc" id="astructaccessctrl__hw__t_html"><div class="ttname"><a href="structaccessctrl__hw__t.html">accessctrl_hw_t</a></div><div class="ttdef"><b>Definition:</b> accessctrl.h:26</div></div>
 620 </div><!-- fragment --></div><!-- contents -->
 621 </div><!-- doc-content -->
 622
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