L: Mailing list that is relevant to this area
W: Web-page with status/info
Q: Patchwork web based patch tracking system site
- T: SCM tree type and location. Type is one of: git, hg, quilt, stgit, topgit.
+ T: SCM tree type and location.
+ Type is one of: git, hg, quilt, stgit, topgit
S: Status, one of the following:
Supported: Someone is actually paid to look after this.
Maintained: Someone actually looks after it.
F: drivers/platform/x86/acer-wmi.c
ACPI
W: https://01.org/linux-acpi
Q: https://patchwork.kernel.org/project/linux-acpi/list/
AGPGART DRIVER
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6.git
+T: git git://people.freedesktop.org/~airlied/linux (part of drm maint)
S: Maintained
F: drivers/char/agp/
F: include/linux/agp*
F: arch/alpha/
+ALTERA TRIPLE SPEED ETHERNET DRIVER
+S: Maintained
+F: drivers/net/ethernet/altera/
+
ALTERA UART/JTAG UART SERIAL DRIVERS
-L: nios2-dev@sopc.et.ntust.edu.tw (moderated for non-subscribers)
+L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
S: Maintained
F: drivers/tty/serial/altera_uart.c
F: drivers/tty/serial/altera_jtaguart.c
S: Odd Fixes
-F: arch/arm/mach-clps711x/
+N: clps711x
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
F: arch/arm/mach-footbridge/
ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
-M: Shawn Guo <shawn.guo@linaro.org>
+M: Shawn Guo <shawn.guo@freescale.com>
S: Maintained
-T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
F: arch/arm/mach-imx/
F: arch/arm/boot/dts/imx*
F: arch/arm/configs/imx*_defconfig
F: drivers/clk/socfpga/
ARM/STI ARCHITECTURE
W: http://www.stlinux.com
S: Maintained
F: arch/arm/mach-sti/
+ F: arch/arm/boot/dts/sti*
+ F: drivers/clocksource/arm_global_timer.c
+ F: drivers/reset/sti/
+ F: drivers/pinctrl/pinctrl-st.c
+ F: drivers/media/rc/st_rc.c
+ F: drivers/i2c/busses/i2c-st.c
+ F: drivers/tty/serial/st-asc.c
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
S: Supported
F: arch/arm/mach-u300/
+F: drivers/clocksource/timer-u300.c
F: drivers/i2c/busses/i2c-stu300.c
F: drivers/rtc/rtc-coh901331.c
F: drivers/watchdog/coh901327_wdt.c
F: drivers/net/wireless/atmel*
ATTO EXPRESSSAS SAS/SATA RAID SCSI DRIVER
-W: http://www.attotech.com
-S: Supported
-F: drivers/scsi/esas2r
+W: http://www.attotech.com
+S: Supported
+F: drivers/scsi/esas2r
AUDIT SUBSYSTEM
BACKLIGHT CLASS/SUBSYSTEM
S: Maintained
F: drivers/video/backlight/
F: include/linux/backlight.h
BLACKFIN ARCHITECTURE
+T: git git://git.code.sf.net/p/adi-linux/code
W: http://blackfin.uclinux.org
S: Supported
F: arch/blackfin/
F: include/net/bluetooth/
BONDING DRIVER
-M: Veaceslav Falico <vfalico@redhat.com>
+M: Jay Vosburgh <j.vosburgh@gmail.com>
+M: Veaceslav Falico <vfalico@gmail.com>
W: http://sourceforge.net/projects/bonding/
S: Supported
F: drivers/net/ethernet/broadcom/b44.*
+BROADCOM GENET ETHERNET DRIVER
+S: Supported
+F: drivers/net/ethernet/broadcom/genet/
+
BROADCOM BNX2 GIGABIT ETHERNET DRIVER
T: git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git
S: Maintained
-F: arch/arm/mach-bcm2835/
+F: arch/arm/mach-bcm/board_bcm2835.c
F: arch/arm/boot/dts/bcm2835*
F: arch/arm/configs/bcm2835_defconfig
F: drivers/*/*bcm2835*
+ BROADCOM BCM5301X ARM ARCHICTURE
+ S: Maintained
+ F: arch/arm/mach-bcm/bcm_5301x.c
+ F: arch/arm/boot/dts/bcm5301x.dtsi
+ F: arch/arm/boot/dts/bcm470*
+
BROADCOM TG3 GIGABIT ETHERNET DRIVER
S: Supported
F: drivers/scsi/bnx2i/
+BROADCOM KONA GPIO DRIVER
+S: Supported
+F: drivers/gpio/gpio-bcm-kona.c
+F: Documentation/devicetree/bindings/gpio/gpio-bcm-kona.txt
+
BROADCOM SPECIFIC AMBA DRIVER (BCMA)
F: include/linux/bcma/
BROCADE BFA FC SCSI DRIVER
-M: Anil Gurumurthy <agurumur@brocade.com>
-M: Vijaya Mohan Guvva <vmohan@brocade.com>
+M: Anil Gurumurthy <anil.gurumurthy@qlogic.com>
+M: Sudarsana Kalluru <sudarsana.kalluru@qlogic.com>
S: Supported
F: drivers/scsi/bfa/
CHIPIDEA USB HIGH SPEED DUAL ROLE CONTROLLER
-T: git://github.com/hzpeterchen/linux-usb.git
+T: git git://github.com/hzpeterchen/linux-usb.git
S: Maintained
F: drivers/usb/chipidea/
F: drivers/net/ethernet/cisco/enic/
CISCO VIC LOW LATENCY NIC DRIVER
-S: Supported
-F: drivers/infiniband/hw/usnic
+S: Supported
+F: drivers/infiniband/hw/usnic
CIRRUS LOGIC EP93XX ETHERNET DRIVER
S: Odd Fixes
F: sound/soc/codecs/cs4270*
+CIRRUS LOGIC AUDIO CODEC DRIVERS
+S: Maintained
+F: sound/soc/codecs/cs*
+
CLEANCACHE API
F: drivers/cpufreq/arm_big_little_dt.c
CPUIDLE DRIVER - ARM BIG LITTLE
-T: git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
-S: Maintained
-F: drivers/cpuidle/cpuidle-big_little.c
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
+S: Maintained
+F: drivers/cpuidle/cpuidle-big_little.c
CPUIDLE DRIVERS
S: Maintained
-T: git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
F: drivers/cpuidle/*
F: include/linux/cpuidle.h
F: sound/pci/cs5535audio/
CW1200 WLAN driver
-S: Maintained
-F: drivers/net/wireless/cw1200/
+S: Maintained
+F: drivers/net/wireless/cw1200/
CX18 VIDEO4LINUX DRIVER
-W: http://twibble.org/dist/dc395x/
-L: http://lists.twibble.org/mailman/listinfo/dc395x/
+W: http://twibble.org/dist/dc395x/
+W: http://lists.twibble.org/mailman/listinfo/dc395x/
S: Maintained
F: Documentation/scsi/dc395x.txt
F: drivers/scsi/dc395x.*
F: include/linux/dm-*.h
F: include/uapi/linux/dm-*.h
+DIALOG SEMICONDUCTOR DRIVERS
+W: http://www.dialog-semiconductor.com/products
+S: Supported
+F: Documentation/hwmon/da90??
+F: drivers/gpio/gpio-da90??.c
+F: drivers/hwmon/da90??-hwmon.c
+F: drivers/input/misc/da90??_onkey.c
+F: drivers/input/touchscreen/da9052_tsi.c
+F: drivers/leds/leds-da90??.c
+F: drivers/mfd/da903x.c
+F: drivers/mfd/da90??-*.c
+F: drivers/power/da9052-battery.c
+F: drivers/regulator/da903x.c
+F: drivers/regulator/da9???-regulator.[ch]
+F: drivers/rtc/rtc-da90??.c
+F: drivers/video/backlight/da90??_bl.c
+F: drivers/watchdog/da90??_wdt.c
+F: include/linux/mfd/da903x.h
+F: include/linux/mfd/da9052/
+F: include/linux/mfd/da9055/
+F: include/linux/mfd/da9063/
+F: include/sound/da[79]*.h
+F: sound/soc/codecs/da[79]*.[ch]
+
DIGI NEO AND CLASSIC PCI PRODUCTS
F: drivers/acpi/dock.c
DOCUMENTATION
-T: TBD
+T: quilt http://www.infradead.org/~rdunlap/Doc/patches/
S: Maintained
F: Documentation/
DRM DRIVERS
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6.git
+T: git git://people.freedesktop.org/~airlied/linux
S: Maintained
F: drivers/gpu/drm/
F: include/drm/
F: include/uapi/drm/
+RADEON DRM DRIVERS
+T: git git://people.freedesktop.org/~agd5f/linux
+S: Supported
+F: drivers/gpu/drm/radeon/
+F: include/drm/radeon*
+F: include/uapi/drm/radeon*
+
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
EDAC-CORE
W: bluesmoke.sourceforge.net
S: Supported
F: fs/ext4/
Extended Verification Module (EVM)
S: Supported
F: security/integrity/evm/
F: include/uapi/scsi/fc/
FILE LOCKING (flock() and fcntl()/lockf())
S: Maintained
F: include/linux/fcntl.h
F: fs/freevxfs/
FREEZER
S: Supported
F: Documentation/power/freezing-of-tasks.txt
F: drivers/video/hgafb.c
HIBERNATION (aka Software Suspend, aka swsusp)
S: Supported
F: arch/x86/power/
F: include/uapi/linux/hpet.h
HPET: x86
-S: Maintained
+S: Orphan
F: arch/x86/kernel/hpet.c
F: arch/x86/include/asm/hpet.h
F: drivers/ipack/
INTEGRITY MEASUREMENT ARCHITECTURE (IMA)
-M: Mimi Zohar <zohar@us.ibm.com>
+M: Mimi Zohar <zohar@linux.vnet.ibm.com>
S: Supported
F: security/integrity/ima/
W: http://www.intel.com/support/feedback.htm
W: http://e1000.sourceforge.net/
F: Documentation/networking/i40e.txt
F: Documentation/networking/i40evf.txt
F: drivers/net/ethernet/intel/
+F: drivers/net/ethernet/intel/*/
INTEL-MID GPIO DRIVER
INTEL WIRELESS WIMAX CONNECTION 2400
S: Supported
W: http://linuxwimax.org
F: Documentation/wimax/README.i2400m
F: Documentation/hwmon/it87
F: drivers/hwmon/it87.c
-IT913X MEDIA DRIVER
-W: http://linuxtv.org/
-Q: http://patchwork.linuxtv.org/project/linux-media/list/
-S: Maintained
-F: drivers/media/usb/dvb-usb-v2/it913x*
-
-IT913X FE MEDIA DRIVER
-W: http://linuxtv.org/
-Q: http://patchwork.linuxtv.org/project/linux-media/list/
-S: Maintained
-F: drivers/media/dvb-frontends/it913x-fe*
-
IT913X MEDIA DRIVER
KCONFIG
-T: git://gitorious.org/linux-kconfig/linux-kconfig
+T: git git://gitorious.org/linux-kconfig/linux-kconfig
S: Maintained
F: Documentation/kbuild/kconfig-language.txt
F: scripts/kconfig/
F: security/keys/
KEYS-TRUSTED
-M: David Safford <safford@watson.ibm.com>
-M: Mimi Zohar <zohar@us.ibm.com>
+M: David Safford <safford@us.ibm.com>
+M: Mimi Zohar <zohar@linux.vnet.ibm.com>
S: Supported
F: security/keys/trusted.h
KEYS-ENCRYPTED
-M: Mimi Zohar <zohar@us.ibm.com>
-M: David Safford <safford@watson.ibm.com>
+M: Mimi Zohar <zohar@linux.vnet.ibm.com>
+M: David Safford <safford@us.ibm.com>
S: Supported
F: arch/powerpc/platforms/52xx/
LINUX FOR POWERPC EMBEDDED PPC4XX
W: http://www.penguinppc.org/
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
S: Maintained
F: arch/powerpc/platforms/40x/
F: arch/powerpc/platforms/44x/
F: drivers/media/tuners/m88ts2022*
MA901 MASTERKIT USB FM RADIO DRIVER
-T: git git://linuxtv.org/media_tree.git
-S: Maintained
-F: drivers/media/radio/radio-ma901.c
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: drivers/media/radio/radio-ma901.c
MAC80211
S: Maintained
+MARVELL ARMADA DRM SUPPORT
+S: Maintained
+F: drivers/gpu/drm/armada/
+
MARVELL GIGABIT ETHERNET DRIVERS (skge/sky2)
MELLANOX ETHERNET DRIVER (mlx4_en)
S: Supported
W: http://www.mellanox.com
Q: http://patchwork.ozlabs.org/project/netdev/list/
F: include/uapi/mtd/
MEN A21 WATCHDOG DRIVER
S: Supported
F: drivers/watchdog/mena21_wdt.c
+MEN CHAMELEON BUS (mcb)
+S: Supported
+F: drivers/mcb/
+F: include/linux/mcb.h
+
METAG ARCHITECTURE
MICROBLAZE ARCHITECTURE
W: http://www.monstr.eu/fdt/
T: git git://git.monstr.eu/linux-2.6-microblaze.git
S: Supported
W: http://www.mellanox.com
Q: http://patchwork.ozlabs.org/project/netdev/list/
Q: http://patchwork.kernel.org/project/linux-rdma/list/
-T: git://openfabrics.org/~eli/connect-ib.git
+T: git git://openfabrics.org/~eli/connect-ib.git
S: Supported
F: drivers/net/ethernet/mellanox/mlx5/core/
F: include/linux/mlx5/
Mellanox MLX5 IB driver
-W: http://www.mellanox.com
-Q: http://patchwork.kernel.org/project/linux-rdma/list/
-T: git://openfabrics.org/~eli/connect-ib.git
-S: Supported
-F: include/linux/mlx5/
-F: drivers/infiniband/hw/mlx5/
+W: http://www.mellanox.com
+Q: http://patchwork.kernel.org/project/linux-rdma/list/
+T: git git://openfabrics.org/~eli/connect-ib.git
+S: Supported
+F: include/linux/mlx5/
+F: drivers/infiniband/hw/mlx5/
MODULE SUPPORT
S: Supported
F: drivers/platform/x86/msi-wmi.c
+MSI001 MEDIA DRIVER
+W: http://linuxtv.org/
+W: http://palosaari.fi/linux/
+Q: http://patchwork.linuxtv.org/project/linux-media/list/
+T: git git://linuxtv.org/anttip/media_tree.git
+S: Maintained
+F: drivers/staging/media/msi3101/msi001*
+
+MSI3101 MEDIA DRIVER
+W: http://linuxtv.org/
+W: http://palosaari.fi/linux/
+Q: http://patchwork.linuxtv.org/project/linux-media/list/
+T: git git://linuxtv.org/anttip/media_tree.git
+S: Maintained
+F: drivers/staging/media/msi3101/sdr-msi3101*
+
MT9M032 APTINA SENSOR DRIVER
F: include/uapi/linux/in.h
F: include/uapi/linux/net.h
F: include/uapi/linux/netdevice.h
+F: tools/net/
+F: tools/testing/selftests/net/
+F: lib/random32.c
NETWORKING [IPv4/IPv6]
T: git git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec-next.git
S: Maintained
+F: net/core/flow.c
F: net/xfrm/
F: net/key/
F: net/ipv4/xfrm*
F: include/uapi/linux/nfc.h
F: drivers/nfc/
F: include/linux/platform_data/pn544.h
+F: Documentation/devicetree/bindings/net/nfc/
NFS, SUNRPC, AND LOCKD CLIENTS
F: include/uapi/linux/sunrpc/
NILFS2 FILESYSTEM
-W: http://www.nilfs.org/en/
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/ryusuke/nilfs2.git
+W: http://nilfs.sourceforge.net/
+T: git git://github.com/konis/nilfs2.git
S: Supported
F: Documentation/filesystems/nilfs2.txt
F: fs/nilfs2/
F: drivers/block/nvme*
F: include/linux/nvme.h
+NXP TDA998X DRM DRIVER
+S: Supported
+F: drivers/gpu/drm/i2c/tda998x_drv.c
+F: include/drm/i2c/tda998x.h
+
OMAP SUPPORT
F: drivers/net/ethernet/qlogic/qla3xxx.*
QLOGIC QLCNIC (1/10)Gb ETHERNET DRIVER
S: Supported
F: drivers/net/ethernet/qlogic/qlcnic/
S: Maintained
F: drivers/media/dvb-frontends/rtl2832*
+RTL2832_SDR MEDIA DRIVER
+W: http://linuxtv.org/
+W: http://palosaari.fi/linux/
+Q: http://patchwork.linuxtv.org/project/linux-media/list/
+T: git git://linuxtv.org/anttip/media_tree.git
+S: Maintained
+F: drivers/staging/media/rtl2832u_sdr/rtl2832_sdr*
+
RTL8180 WIRELESS DRIVER
S: Supported
F: arch/s390/
F: drivers/s390/
-F: block/partitions/ibm.c
F: Documentation/s390/
F: Documentation/DocBook/s390*
+S390 COMMON I/O LAYER
+W: http://www.ibm.com/developerworks/linux/linux390/
+S: Supported
+F: drivers/s390/cio/
+
+S390 DASD DRIVER
+W: http://www.ibm.com/developerworks/linux/linux390/
+S: Supported
+F: drivers/s390/block/dasd*
+F: block/partitions/ibm.c
+
S390 NETWORK DRIVERS
S: Supported
F: drivers/s390/net/
+S390 PCI SUBSYSTEM
+W: http://www.ibm.com/developerworks/linux/linux390/
+S: Supported
+F: arch/s390/pci/
+F: drivers/pci/hotplug/s390_pci_hpc.c
+
S390 ZCRYPT DRIVER
F: drivers/clk/samsung/
+SAMSUNG SXGBE DRIVERS
+S: Supported
+F: drivers/net/ethernet/samsung/sxgbe/
+
SERIAL DRIVERS
S: Supported
SELINUX SECURITY MODULE
W: http://selinuxproject.org
T: git git://git.infradead.org/users/pcmoore/selinux
S: Supported
F: drivers/tty/serial/ioc?_serial.c
F: include/linux/ioc?.h
-SGI VISUAL WORKSTATION 320 AND 540
-W: http://linux-visws.sf.net
-S: Maintained for 2.6.
-F: Documentation/sgi-visws.txt
-
SGI XP/XPC/XPNET DRIVER
F: drivers/media/mmc/siano/
SH_VEU V4L2 MEM2MEM DRIVER
-S: Maintained
+S: Orphan
F: drivers/media/platform/sh_veu.c
SH_VOU V4L2 OUTPUT DRIVER
-S: Odd Fixes
+S: Orphan
F: drivers/media/platform/sh_vou.c
F: include/media/sh_vou.h
S: Odd Fixes
F: drivers/staging/sm7xxfb/
+STAGING - SLICOSS
+S: Odd Fixes
+F: drivers/staging/slicoss/
+
STAGING - SOFTLOGIC 6x10 MPEG CODEC
S: Supported
F: drivers/net/ethernet/dlink/sundance.c
SUPERH
W: http://www.linux-sh.org
Q: http://patchwork.kernel.org/project/linux-sh/list/
-T: git git://github.com/pmundt/linux-sh.git sh-latest
-S: Supported
+S: Orphan
F: Documentation/sh/
F: arch/sh/
F: drivers/sh/
SUSPEND TO RAM
S: Supported
F: Documentation/power/
-L: http://groups.google.com/group/linux-iscsi-target-dev
W: http://www.linux-iscsi.org
+W: http://groups.google.com/group/linux-iscsi-target-dev
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending.git master
S: Supported
F: drivers/target/
S: Maintained
F: arch/xtensa/
+F: drivers/irqchip/irq-xtensa-*
THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
F: drivers/media/radio/radio-raremono.c
THERMAL
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git
-Q: https://patchwork.kernel.org/project/linux-pm/list/
-S: Supported
-F: drivers/thermal/
-F: include/linux/thermal.h
-F: include/linux/cpu_cooling.h
-F: Documentation/devicetree/bindings/thermal/
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git
+Q: https://patchwork.kernel.org/project/linux-pm/list/
+S: Supported
+F: drivers/thermal/
+F: include/linux/thermal.h
+F: include/linux/cpu_cooling.h
+F: Documentation/devicetree/bindings/thermal/
THINGM BLINK(1) USB RGB LED DRIVER
F: include/linux/cdrom.h
F: include/uapi/linux/cdrom.h
+UNISYS S-PAR DRIVERS
+S: Supported
+F: drivers/staging/unisys/
+
UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER
F: drivers/net/wireless/ath/ar5523/
USB ATTACHED SCSI
F: drivers/net/wireless/rndis_wlan.c
USB XHCI DRIVER
-M: Sarah Sharp <sarah.a.sharp@linux.intel.com>
+M: Mathias Nyman <mathias.nyman@intel.com>
S: Supported
F: drivers/usb/host/xhci*
VIRTIO CONSOLE DRIVER
S: Maintained
F: drivers/char/virtio_console.c
VIRTIO CORE, NET AND BLOCK DRIVERS
S: Maintained
F: drivers/virtio/
VIRTIO HOST (VHOST)
S: Maintained
WIMAX STACK
S: Supported
W: http://linuxwimax.org
F: Documentation/wimax/README.wimax
S: Maintained
F: drivers/tty/serial/uartlite.c
+XTENSA XTFPGA PLATFORM SUPPORT
+S: Maintained
+F: drivers/spi/spi-xtensa-xtfpga.c
+
YAM DRIVER FOR AX.25
W: http://mjpeg.sourceforge.net/driver-zoran/
-T: Mercurial http://linuxtv.org/hg/v4l-dvb
+T: hg http://linuxtv.org/hg/v4l-dvb
S: Odd Fixes
F: drivers/media/pci/zoran/
config NEED_DMA_MAP_STATE
def_bool y
+config ARCH_SUPPORTS_UPROBES
+ def_bool y
+
config ARCH_HAS_DMA_SET_COHERENT_MASK
bool
bool "Allow multiple platforms to be selected"
depends on MMU
select ARCH_WANT_OPTIONAL_GPIOLIB
+ select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR
select COMMON_CLK
select CPU_ARM720T
select GENERIC_CLOCKEVENTS
select MFD_SYSCON
- select MULTI_IRQ_HANDLER
- select SPARSE_IRQ
help
Support for Cirrus Logic 711x/721x/731x based boards.
bool "Energy Micro efm32"
depends on !MMU
select ARCH_REQUIRE_GPIOLIB
+ select AUTO_ZRELADDR
select ARM_NVIC
- # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
- # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
- select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select CPU_V7M
select PINCTRL
select PINCTRL_DOVE
select PLAT_ORION_LEGACY
- select USB_ARCH_HAS_EHCI
help
Support for the Marvell Dove SoC 88AP510
select GENERIC_CLOCKEVENTS
select HAVE_IDE
select HAVE_PWM
- select USB_ARCH_HAS_OHCI
select USE_OF
help
Support for the NXP LPC32XX family of processors
select ARCH_MAY_HAVE_PC_FDC
select ARCH_SPARSEMEM_ENABLE
select ARCH_USES_GETTIMEOFFSET
+ select CPU_SA110
select FIQ
select HAVE_IDE
select HAVE_PATA_PLATFORM
bool "Samsung S3C24XX SoCs"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
+ select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_VIC
+ select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select COMMON_CLK
select HAVE_TCM
select NO_IOPORT
select PLAT_SAMSUNG
- select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS if PM
select S3C_DEV_NAND
select S3C_GPIO_TRACK
select SAMSUNG_ATAGS
select SAMSUNG_WAKEMASK
select SAMSUNG_WDT_RESET
- select USB_ARCH_HAS_OHCI
help
Samsung S3C64XX series based systems
config ARCH_S5P64X0
bool "Samsung S5P6440 S5P6450"
+ select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V6
config ARCH_S5PC100
bool "Samsung S5PC100"
select ARCH_REQUIRE_GPIOLIB
+ select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V7
select ARCH_HAS_CPUFREQ
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
+ select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V7
comment "CPU Core family selection"
+config ARCH_MULTI_V4
+ bool "ARMv4 based platforms (FA526)"
+ depends on !ARCH_MULTI_V6_V7
+ select ARCH_MULTI_V4_V5
+ select CPU_FA526
+
config ARCH_MULTI_V4T
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
depends on !ARCH_MULTI_V6_V7
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
depends on !ARCH_MULTI_V6_V7
select ARCH_MULTI_V4_V5
- select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
+ select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
source "arch/arm/mach-bcm/Kconfig"
-source "arch/arm/mach-bcm2835/Kconfig"
-
source "arch/arm/mach-berlin/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
choice
prompt "Memory split"
+ depends on MMU
default VMSPLIT_3G
help
Select the desired split between kernel and user memory.
config PAGE_OFFSET
hex
+ default PHYS_OFFSET if !MMU
default 0x40000000 if VMSPLIT_1G
default 0x80000000 if VMSPLIT_2G
default 0xC0000000
depends on ARM && AEABI && OF
depends on CPU_V7 && !CPU_V6
depends on !GENERIC_ATOMIC64
+ depends on MMU
select ARM_PSCI
select SWIOTLB_XEN
select ARCH_DMA_ADDR_T_64BIT
select IRQ_DOMAIN
select OF
select OF_EARLY_FLATTREE
+ select OF_RESERVED_MEM
help
Include support for flattened device tree machine descriptions.
config ARCH_SUSPEND_POSSIBLE
depends on !ARCH_S5PC100
depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
- CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
+ CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
def_bool y
config ARM_CPU_SUSPEND
depends on ARCH_BCM2835
select DEBUG_UART_PL01X
+ config DEBUG_BCM_5301X
+ bool "Kernel low-level debugging on BCM5301X UART1"
+ depends on ARCH_BCM_5301X
+ select DEBUG_UART_PL01X
+
config DEBUG_BCM_KONA_UART
bool "Kernel low-level debugging messages via BCM KONA UART"
- depends on ARCH_BCM
+ depends on ARCH_BCM_MOBILE
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
Say Y here if you want the debug print routines to direct
their output to UART0 serial port on DaVinci DMx devices.
- config DEBUG_DAVINCI_TNETV107X_UART1
- bool "Kernel low-level debugging on DaVinci TNETV107x using UART1"
- depends on ARCH_DAVINCI_TNETV107X
- select DEBUG_UART_8250
- help
- Say Y here if you want the debug print routines to direct
- their output to UART1 serial port on DaVinci TNETV107X
- devices.
-
config DEBUG_ZYNQ_UART0
bool "Kernel low-level debugging on Xilinx Zynq using UART0"
depends on ARCH_ZYNQ
default 0x02530c00 if DEBUG_KEYSTONE_UART0
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
- default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \
DEBUG_VEXPRESS_UART0_CA9
default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
default 0x101f1000 if ARCH_VERSATILE
default 0x101fb000 if DEBUG_NOMADIK_UART
default 0x16000000 if ARCH_INTEGRATOR
+ default 0x18000300 if DEBUG_BCM_5301X
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x20060000 if DEBUG_RK29_UART0
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0xf0009000 if DEBUG_CNS3XXX
default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835
+ default 0xf1000300 if DEBUG_BCM_5301X
default 0xf11f1000 if ARCH_VERSATILE
default 0xf1600000 if ARCH_INTEGRATOR
default 0xf1c28000 if DEBUG_SUNXI_UART0
default 0xfed12000 if ARCH_KIRKWOOD
default 0xfedc0000 if ARCH_EP93XX
default 0xfee003f8 if FOOTBRIDGE
- default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfee82340 if ARCH_IOP13XX
default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
- DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
+ DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_KONA_UART
config DEBUG_UART_8250_FLOW_CONTROL
config DEBUG_UNCOMPRESS
bool
- depends on ARCH_MULTIPLATFORM || ARCH_MSM
+ depends on ARCH_MULTIPLATFORM || ARCH_MSM || ARCH_EXYNOS
default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM)
help
config UNCOMPRESS_INCLUDE
string
- default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM
+ default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
+ ARCH_EXYNOS || ARCH_EFM32
default "mach/uncompress.h"
config EARLY_PRINTK
dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
+# sam9261
+dtb-$(CONFIG_ARCH_AT91) += at91sam9261ek.dtb
# sam9263
dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
# sam9n12
dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
+# sam9rl
+dtb-$(CONFIG_ARCH_AT91) += at91sam9rlek.dtb
# sam9x5
dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
berlin2cd-google-chromecast.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
- dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
dove-cubox.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
ecx-2000.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
integratorcp.dtb
- dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
- dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+ kirkwood := \
+ kirkwood-cloudbox.dtb \
kirkwood-db-88f6281.dtb \
kirkwood-db-88f6282.dtb \
kirkwood-dns320.dtb \
kirkwood-topkick.dtb \
kirkwood-ts219-6281.dtb \
kirkwood-ts219-6282.dtb
+ dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
+ dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
+ dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
zynq-zc706.dtb \
zynq-zed.dtb
-targets += dtbs
+targets += dtbs dtbs_install
targets += $(dtb-y)
endif
$(Q)rm -f $(obj)/../*.dtb
clean-files := *.dtb
+
+dtbs_install: $(addsuffix _dtbinst_, $(dtb-y))
CONFIG_ARCH_DAVINCI_DM355=y
CONFIG_ARCH_DAVINCI_DM646x=y
CONFIG_ARCH_DAVINCI_DM365=y
+ CONFIG_ARCH_DAVINCI_DA830=y
+ CONFIG_ARCH_DAVINCI_DA850=y
+ CONFIG_MACH_DA8XX_DT=y
CONFIG_MACH_SFFSDR=y
CONFIG_MACH_NEUROS_OSD2=y
CONFIG_MACH_DM355_LEOPARD=y
+ CONFIG_MACH_MITYOMAPL138=y
+ CONFIG_MACH_OMAPL138_HAWKBOARD=y
CONFIG_DAVINCI_MUX_DEBUG=y
CONFIG_DAVINCI_MUX_WARNINGS=y
CONFIG_DAVINCI_RESET_CLOCKS=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_LEDS=y
+ CONFIG_USE_OF=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
+ CONFIG_ARM_APPENDED_DTB=y
+ CONFIG_ARM_ATAG_DTB_COMPAT=y
+ CONFIG_AUTO_ZRELADDR=y
+ CONFIG_CPU_FREQ=y
+ CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+ CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
+ CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+ CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+ CONFIG_CPU_IDLE=y
CONFIG_PM_RUNTIME=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_NAND=m
CONFIG_MTD_NAND_DAVINCI=m
+ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_LXT_PHY=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_NET_ETHERNET=y
+ CONFIG_MII=y
CONFIG_TI_DAVINCI_EMAC=y
CONFIG_DM9000=y
# CONFIG_NETDEV_1000 is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
# CONFIG_HW_RANDOM is not set
+ CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DAVINCI=y
+ CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIO_PCF857X=y
CONFIG_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_MFD_DM355EVM_MSP=y
+ CONFIG_TPS6507X=y
CONFIG_VIDEO_OUTPUT_CONTROL=m
+ CONFIG_REGULATOR=y
+ CONFIG_REGULATOR_TPS6507X=y
CONFIG_FB=y
+ CONFIG_FB_DA8XX=y
CONFIG_FIRMWARE_EDID=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_T10DIF=m
+CONFIG_GPIO_PCA953X=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
};
extern struct secondary_data secondary_data;
extern volatile int pen_release;
+extern void secondary_startup(void);
extern int __cpu_disable(void);
#endif
};
+ struct of_cpu_method {
+ const char *method;
+ struct smp_operations *ops;
+ };
+
+ #define CPU_METHOD_OF_DECLARE(name, _method, _ops) \
+ static const struct of_cpu_method __cpu_method_of_table_##name \
+ __used __section(__cpu_method_of_table) \
+ = { .method = _method, .ops = _ops }
/*
* set platform specific SMP operations
*/
BCM11130, BCM11140, BCM11351, BCM28145 and
BCM28155 variants.
+config ARCH_BCM2835
+ bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_AMBA
+ select ARM_ERRATA_411920
+ select ARM_TIMER_SP804
+ select CLKDEV_LOOKUP
+ select CLKSRC_OF
+ select CPU_V6
+ select GENERIC_CLOCKEVENTS
+ select PINCTRL
+ select PINCTRL_BCM2835
+ help
+ This enables support for the Broadcom BCM2835 SoC. This SoC is
+ used in the Raspberry Pi and Roku 2 devices.
+
+ config ARCH_BCM_5301X
+ bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+ depends on MMU
+ select ARM_GIC
+ select CACHE_L2X0
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select HAVE_SMP
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
+ select ARM_GLOBAL_TIMER
+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+ select MIGHT_HAVE_PCI
+ help
+ Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+ This is a network SoC line mostly used in home routers and
+ wifi access points, it's internal name is Northstar.
+ This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+ BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+ BCM4708 and BCM4709.
+
+ Do not confuse this with the BCM4760 which is a totally
+ different SoC or with the older BCM47XX and BCM53XX based
+ network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+
endmenu
endif
#
- # Copyright (C) 2012-2013 Broadcom Corporation
+ # Copyright (C) 2012-2014 Broadcom Corporation
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
- obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+ obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o board_bcm21664.o \
+ bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
+ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
-#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3)
+#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 4)
/* LCD contrast digital potentiometer */
#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0)
MACHINE_START(AUTCPU12, "autronix autcpu12")
/* Maintainer: Thomas Gleixner */
.atag_offset = 0x20000,
- .nr_irqs = CLPS711X_NR_IRQS,
.map_io = clps711x_map_io,
.init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.init_machine = autcpu12_init,
.init_late = autcpu12_init_late,
- .handle_irq = clps711x_handle_irq,
.restart = clps711x_restart,
MACHINE_END
select AINTC
select ARCH_DAVINCI_DMx
- config ARCH_DAVINCI_TNETV107X
- bool "TNETV107X based system"
- select CPU_V6
- select CP_INTC
-
comment "DaVinci Board Type"
config MACH_DA8XX_DT
Say Y if you want to use a wl1271 expansion card connected to the
AM18x EVM.
-config GPIO_PCA953X
- default MACH_DAVINCI_DA850_EVM
-
-config KEYBOARD_GPIO_POLLED
- default MACH_DAVINCI_DA850_EVM
- config MACH_TNETV107X
- bool "TI TNETV107X Reference Platform"
- default ARCH_DAVINCI_TNETV107X
- depends on ARCH_DAVINCI_TNETV107X
- help
- Say Y here to select the TI TNETV107X Evaluation Module.
-
config MACH_MITYOMAPL138
bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
depends on ARCH_DAVINCI_DA850
--- /dev/null
- struct irq_desc *iomuxc_irq_desc;
+ /*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+ #include <linux/delay.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+ #include <linux/genalloc.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
+ #include <linux/regmap.h>
+ #include <linux/suspend.h>
+ #include <asm/cacheflush.h>
+ #include <asm/fncpy.h>
+ #include <asm/proc-fns.h>
+ #include <asm/suspend.h>
+ #include <asm/tlb.h>
+
+ #include "common.h"
+ #include "hardware.h"
+
+ #define CCR 0x0
+ #define BM_CCR_WB_COUNT (0x7 << 16)
+ #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
+ #define BM_CCR_RBC_EN (0x1 << 27)
+
+ #define CLPCR 0x54
+ #define BP_CLPCR_LPM 0
+ #define BM_CLPCR_LPM (0x3 << 0)
+ #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
+ #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+ #define BM_CLPCR_SBYOS (0x1 << 6)
+ #define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
+ #define BM_CLPCR_VSTBY (0x1 << 8)
+ #define BP_CLPCR_STBY_COUNT 9
+ #define BM_CLPCR_STBY_COUNT (0x3 << 9)
+ #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+ #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
+ #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
+ #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
+ #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
+ #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
+ #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
+ #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
+ #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
+ #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
+ #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
+
+ #define CGPR 0x64
+ #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
+
+ #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
+ #define MX6_MAX_MMDC_IO_NUM 33
+
+ static void __iomem *ccm_base;
+ static void __iomem *suspend_ocram_base;
+ static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+
+ /*
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ * .
+ * .
+ * .
+ * ^
+ * ^
+ * ^
+ * imx6_suspend code
+ * PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+
+ struct imx6_pm_base {
+ phys_addr_t pbase;
+ void __iomem *vbase;
+ };
+
+ struct imx6_pm_socdata {
+ u32 cpu_type;
+ const char *mmdc_compat;
+ const char *src_compat;
+ const char *iomuxc_compat;
+ const char *gpc_compat;
+ const u32 mmdc_io_num;
+ const u32 *mmdc_io_offset;
+ };
+
+ static const u32 imx6q_mmdc_io_offset[] __initconst = {
+ 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
+ 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
+ 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+ 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
+ 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
+ 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
+ 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+ 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
+ 0x74c, /* GPR_ADDS */
+ };
+
+ static const u32 imx6dl_mmdc_io_offset[] __initconst = {
+ 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
+ 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
+ 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+ 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
+ 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
+ 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
+ 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+ 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
+ 0x74c, /* GPR_ADDS */
+ };
+
+ static const u32 imx6sl_mmdc_io_offset[] __initconst = {
+ 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
+ 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
+ 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+ 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
+ 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
+ };
+
+ static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
+ .cpu_type = MXC_CPU_IMX6Q,
+ .mmdc_compat = "fsl,imx6q-mmdc",
+ .src_compat = "fsl,imx6q-src",
+ .iomuxc_compat = "fsl,imx6q-iomuxc",
+ .gpc_compat = "fsl,imx6q-gpc",
+ .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
+ .mmdc_io_offset = imx6q_mmdc_io_offset,
+ };
+
+ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
+ .cpu_type = MXC_CPU_IMX6DL,
+ .mmdc_compat = "fsl,imx6q-mmdc",
+ .src_compat = "fsl,imx6q-src",
+ .iomuxc_compat = "fsl,imx6dl-iomuxc",
+ .gpc_compat = "fsl,imx6q-gpc",
+ .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
+ .mmdc_io_offset = imx6dl_mmdc_io_offset,
+ };
+
+ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
+ .cpu_type = MXC_CPU_IMX6SL,
+ .mmdc_compat = "fsl,imx6sl-mmdc",
+ .src_compat = "fsl,imx6sl-src",
+ .iomuxc_compat = "fsl,imx6sl-iomuxc",
+ .gpc_compat = "fsl,imx6sl-gpc",
+ .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
+ .mmdc_io_offset = imx6sl_mmdc_io_offset,
+ };
+
+ /*
+ * This structure is for passing necessary data for low level ocram
+ * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
+ * definition is changed, the offset definition in
+ * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
+ * otherwise, the suspend to ocram function will be broken!
+ */
+ struct imx6_cpu_pm_info {
+ phys_addr_t pbase; /* The physical address of pm_info. */
+ phys_addr_t resume_addr; /* The physical resume address for asm code */
+ u32 cpu_type;
+ u32 pm_info_size; /* Size of pm_info. */
+ struct imx6_pm_base mmdc_base;
+ struct imx6_pm_base src_base;
+ struct imx6_pm_base iomuxc_base;
+ struct imx6_pm_base ccm_base;
+ struct imx6_pm_base gpc_base;
+ struct imx6_pm_base l2_base;
+ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
+ u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
+ } __aligned(8);
+
+ void imx6q_set_int_mem_clk_lpm(void)
+ {
+ u32 val = readl_relaxed(ccm_base + CGPR);
+
+ val |= BM_CGPR_INT_MEM_CLK_LPM;
+ writel_relaxed(val, ccm_base + CGPR);
+ }
+
+ static void imx6q_enable_rbc(bool enable)
+ {
+ u32 val;
+
+ /*
+ * need to mask all interrupts in GPC before
+ * operating RBC configurations
+ */
+ imx_gpc_mask_all();
+
+ /* configure RBC enable bit */
+ val = readl_relaxed(ccm_base + CCR);
+ val &= ~BM_CCR_RBC_EN;
+ val |= enable ? BM_CCR_RBC_EN : 0;
+ writel_relaxed(val, ccm_base + CCR);
+
+ /* configure RBC count */
+ val = readl_relaxed(ccm_base + CCR);
+ val &= ~BM_CCR_RBC_BYPASS_COUNT;
+ val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+ writel(val, ccm_base + CCR);
+
+ /*
+ * need to delay at least 2 cycles of CKIL(32K)
+ * due to hardware design requirement, which is
+ * ~61us, here we use 65us for safe
+ */
+ udelay(65);
+
+ /* restore GPC interrupt mask settings */
+ imx_gpc_restore_all();
+ }
+
+ static void imx6q_enable_wb(bool enable)
+ {
+ u32 val;
+
+ /* configure well bias enable bit */
+ val = readl_relaxed(ccm_base + CLPCR);
+ val &= ~BM_CLPCR_WB_PER_AT_LPM;
+ val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+ writel_relaxed(val, ccm_base + CLPCR);
+
+ /* configure well bias count */
+ val = readl_relaxed(ccm_base + CCR);
+ val &= ~BM_CCR_WB_COUNT;
+ val |= enable ? BM_CCR_WB_COUNT : 0;
+ writel_relaxed(val, ccm_base + CCR);
+ }
+
+ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+ {
- iomuxc_irq_desc = irq_to_desc(32);
- imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
++ struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
+ u32 val = readl_relaxed(ccm_base + CLPCR);
+
+ val &= ~BM_CLPCR_LPM;
+ switch (mode) {
+ case WAIT_CLOCKED:
+ break;
+ case WAIT_UNCLOCKED:
+ val |= 0x1 << BP_CLPCR_LPM;
+ val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+ break;
+ case STOP_POWER_ON:
+ val |= 0x2 << BP_CLPCR_LPM;
+ break;
+ case WAIT_UNCLOCKED_POWER_OFF:
+ val |= 0x1 << BP_CLPCR_LPM;
+ val &= ~BM_CLPCR_VSTBY;
+ val &= ~BM_CLPCR_SBYOS;
+ break;
+ case STOP_POWER_OFF:
+ val |= 0x2 << BP_CLPCR_LPM;
+ val |= 0x3 << BP_CLPCR_STBY_COUNT;
+ val |= BM_CLPCR_VSTBY;
+ val |= BM_CLPCR_SBYOS;
+ if (cpu_is_imx6sl()) {
+ val |= BM_CLPCR_BYPASS_PMIC_READY;
+ val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+ } else {
+ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * ERR007265: CCM: When improper low-power sequence is used,
+ * the SoC enters low power mode before the ARM core executes WFI.
+ *
+ * Software workaround:
+ * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
+ * by setting IOMUX_GPR1_GINT.
+ * 2) Software should then unmask IRQ #32 in GPC before setting CCM
+ * Low-Power mode.
+ * 3) Software should mask IRQ #32 right after CCM Low-Power mode
+ * is set (set bits 0-1 of CCM_CLPCR).
+ */
- imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
++ imx_gpc_irq_unmask(iomuxc_irq_data);
+ writel_relaxed(val, ccm_base + CLPCR);
++ imx_gpc_irq_mask(iomuxc_irq_data);
+
+ return 0;
+ }
+
+ static int imx6q_suspend_finish(unsigned long val)
+ {
+ if (!imx6_suspend_in_ocram_fn) {
+ cpu_do_idle();
+ } else {
+ /*
+ * call low level suspend function in ocram,
+ * as we need to float DDR IO.
+ */
+ local_flush_tlb_all();
+ imx6_suspend_in_ocram_fn(suspend_ocram_base);
+ }
+
+ return 0;
+ }
+
+ static int imx6q_pm_enter(suspend_state_t state)
+ {
+ switch (state) {
+ case PM_SUSPEND_MEM:
+ imx6q_set_lpm(STOP_POWER_OFF);
+ imx6q_enable_wb(true);
+ /*
+ * For suspend into ocram, asm code already take care of
+ * RBC setting, so we do NOT need to do that here.
+ */
+ if (!imx6_suspend_in_ocram_fn)
+ imx6q_enable_rbc(true);
+ imx_gpc_pre_suspend();
+ imx_anatop_pre_suspend();
+ imx_set_cpu_jump(0, v7_cpu_resume);
+ /* Zzz ... */
+ cpu_suspend(0, imx6q_suspend_finish);
+ if (cpu_is_imx6q() || cpu_is_imx6dl())
+ imx_smp_prepare();
+ imx_anatop_post_resume();
+ imx_gpc_post_resume();
+ imx6q_enable_rbc(false);
+ imx6q_enable_wb(false);
+ imx6q_set_lpm(WAIT_CLOCKED);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+ }
+
+ static const struct platform_suspend_ops imx6q_pm_ops = {
+ .enter = imx6q_pm_enter,
+ .valid = suspend_valid_only_mem,
+ };
+
+ void __init imx6q_pm_set_ccm_base(void __iomem *base)
+ {
+ ccm_base = base;
+ }
+
+ static int __init imx6_pm_get_base(struct imx6_pm_base *base,
+ const char *compat)
+ {
+ struct device_node *node;
+ struct resource res;
+ int ret = 0;
+
+ node = of_find_compatible_node(NULL, NULL, compat);
+ if (!node) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ ret = of_address_to_resource(node, 0, &res);
+ if (ret)
+ goto put_node;
+
+ base->pbase = res.start;
+ base->vbase = ioremap(res.start, resource_size(&res));
+ if (!base->vbase)
+ ret = -ENOMEM;
+
+ put_node:
+ of_node_put(node);
+ out:
+ return ret;
+ }
+
+ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
+ {
+ phys_addr_t ocram_pbase;
+ struct device_node *node;
+ struct platform_device *pdev;
+ struct imx6_cpu_pm_info *pm_info;
+ struct gen_pool *ocram_pool;
+ unsigned long ocram_base;
+ int i, ret = 0;
+ const u32 *mmdc_offset_array;
+
+ suspend_set_ops(&imx6q_pm_ops);
+
+ if (!socdata) {
+ pr_warn("%s: invalid argument!\n", __func__);
+ return -EINVAL;
+ }
+
+ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
+ if (!node) {
+ pr_warn("%s: failed to find ocram node!\n", __func__);
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev) {
+ pr_warn("%s: failed to find ocram device!\n", __func__);
+ ret = -ENODEV;
+ goto put_node;
+ }
+
+ ocram_pool = dev_get_gen_pool(&pdev->dev);
+ if (!ocram_pool) {
+ pr_warn("%s: ocram pool unavailable!\n", __func__);
+ ret = -ENODEV;
+ goto put_node;
+ }
+
+ ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
+ if (!ocram_base) {
+ pr_warn("%s: unable to alloc ocram!\n", __func__);
+ ret = -ENOMEM;
+ goto put_node;
+ }
+
+ ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
+
+ suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
+ MX6Q_SUSPEND_OCRAM_SIZE, false);
+
+ pm_info = suspend_ocram_base;
+ pm_info->pbase = ocram_pbase;
+ pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+ pm_info->pm_info_size = sizeof(*pm_info);
+
+ /*
+ * ccm physical address is not used by asm code currently,
+ * so get ccm virtual address directly, as we already have
+ * it from ccm driver.
+ */
+ pm_info->ccm_base.vbase = ccm_base;
+
+ ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
+ if (ret) {
+ pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
+ goto put_node;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
+ if (ret) {
+ pr_warn("%s: failed to get src base %d!\n", __func__, ret);
+ goto src_map_failed;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
+ if (ret) {
+ pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
+ goto iomuxc_map_failed;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
+ if (ret) {
+ pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
+ goto gpc_map_failed;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
+ if (ret) {
+ pr_warn("%s: failed to get pl310-cache base %d!\n",
+ __func__, ret);
+ goto pl310_cache_map_failed;
+ }
+
+ pm_info->cpu_type = socdata->cpu_type;
+ pm_info->mmdc_io_num = socdata->mmdc_io_num;
+ mmdc_offset_array = socdata->mmdc_io_offset;
+
+ for (i = 0; i < pm_info->mmdc_io_num; i++) {
+ pm_info->mmdc_io_val[i][0] =
+ mmdc_offset_array[i];
+ pm_info->mmdc_io_val[i][1] =
+ readl_relaxed(pm_info->iomuxc_base.vbase +
+ mmdc_offset_array[i]);
+ }
+
+ imx6_suspend_in_ocram_fn = fncpy(
+ suspend_ocram_base + sizeof(*pm_info),
+ &imx6_suspend,
+ MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
+
+ goto put_node;
+
+ pl310_cache_map_failed:
+ iounmap(&pm_info->gpc_base.vbase);
+ gpc_map_failed:
+ iounmap(&pm_info->iomuxc_base.vbase);
+ iomuxc_map_failed:
+ iounmap(&pm_info->src_base.vbase);
+ src_map_failed:
+ iounmap(&pm_info->mmdc_base.vbase);
+ put_node:
+ of_node_put(node);
+
+ return ret;
+ }
+
+ static void __init imx6_pm_common_init(const struct imx6_pm_socdata
+ *socdata)
+ {
+ struct regmap *gpr;
+ int ret;
+
+ WARN_ON(!ccm_base);
+
+ if (IS_ENABLED(CONFIG_SUSPEND)) {
+ ret = imx6q_suspend_init(socdata);
+ if (ret)
+ pr_warn("%s: No DDR LPM support with suspend %d!\n",
+ __func__, ret);
+ }
+
+ /*
+ * This is for SW workaround step #1 of ERR007265, see comments
+ * in imx6q_set_lpm for details of this errata.
+ * Force IOMUXC irq pending, so that the interrupt to GPC can be
+ * used to deassert dsm_request signal when the signal gets
+ * asserted unexpectedly.
+ */
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr))
+ regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
+ IMX6Q_GPR1_GINT);
+ }
+
+ void __init imx6q_pm_init(void)
+ {
+ imx6_pm_common_init(&imx6q_pm_data);
+ }
+
+ void __init imx6dl_pm_init(void)
+ {
+ imx6_pm_common_init(&imx6dl_pm_data);
+ }
+
+ void __init imx6sl_pm_init(void)
+ {
+ imx6_pm_common_init(&imx6sl_pm_data);
+ }
config ARCH_MVEBU
- bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+ bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5)
select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select ARCH_REQUIRE_GPIOLIB
select MIGHT_HAVE_PCI
select PCI_QUIRKS if PCI
+ select OF_ADDRESS_PCI
if ARCH_MVEBU
- menu "Marvell SOC with device tree"
+ menu "Marvell EBU SoC variants"
- config MACH_ARMADA_370_XP
+ config MACH_MVEBU_V7
bool
select ARMADA_370_XP_TIMER
select CACHE_L2X0
- select CPU_PJ4B
config MACH_ARMADA_370
- bool "Marvell Armada 370 boards"
+ bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
select ARMADA_370_CLK
- select MACH_ARMADA_370_XP
+ select CPU_PJ4B
+ select MACH_MVEBU_V7
select PINCTRL_ARMADA_370
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 370 SoC with device tree.
+ config MACH_ARMADA_375
+ bool "Marvell Armada 375 boards" if ARCH_MULTI_V7
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_753970
+ select ARM_GIC
+ select ARMADA_375_CLK
+ select CPU_V7
+ select MACH_MVEBU_V7
+ select PINCTRL_ARMADA_375
+ help
+ Say 'Y' here if you want your kernel to support boards based
+ on the Marvell Armada 375 SoC with device tree.
+
+ config MACH_ARMADA_38X
+ bool "Marvell Armada 380/385 boards" if ARCH_MULTI_V7
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_753970
+ select ARM_GIC
+ select ARMADA_38X_CLK
+ select CPU_V7
+ select MACH_MVEBU_V7
+ select PINCTRL_ARMADA_38X
+ help
+ Say 'Y' here if you want your kernel to support boards based
+ on the Marvell Armada 380/385 SoC with device tree.
+
config MACH_ARMADA_XP
- bool "Marvell Armada XP boards"
+ bool "Marvell Armada XP boards" if ARCH_MULTI_V7
select ARMADA_XP_CLK
- select MACH_ARMADA_370_XP
+ select CPU_PJ4B
+ select MACH_MVEBU_V7
select PINCTRL_ARMADA_XP
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada XP SoC with device tree.
+ config MACH_DOVE
+ bool "Marvell Dove boards" if ARCH_MULTI_V7
+ select CACHE_L2X0
+ select CPU_PJ4
+ select DOVE_CLK
+ select ORION_IRQCHIP
+ select ORION_TIMER
+ select PINCTRL_DOVE
+ help
+ Say 'Y' here if you want your kernel to support the
+ Marvell Dove using flattened device tree.
+
+ config MACH_KIRKWOOD
+ bool "Marvell Kirkwood boards" if ARCH_MULTI_V5
+ select ARCH_HAS_CPUFREQ
+ select ARCH_REQUIRE_GPIOLIB
+ select CPU_FEROCEON
+ select KIRKWOOD_CLK
+ select OF_IRQ
+ select ORION_IRQCHIP
+ select ORION_TIMER
+ select PCI
+ select PCI_QUIRKS
+ select PINCTRL_KIRKWOOD
+ select USE_OF
+ help
+ Say 'Y' here if you want your kernel to support boards based
+ on the Marvell Kirkwood device tree.
+
+ config MACH_T5325
+ bool "HP T5325 thin client"
+ depends on MACH_KIRKWOOD
+ help
+ Say 'Y' here if you want your kernel to support the
+ HP T5325 Thin client
+
endmenu
endif
--- /dev/null
+ /*
+ * Device Tree support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/clk-provider.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
+ #include <linux/io.h>
+ #include <linux/clocksource.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/mbus.h>
++#include <linux/signal.h>
+ #include <linux/slab.h>
+ #include <asm/hardware/cache-l2x0.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/time.h>
+ #include "armada-370-xp.h"
+ #include "common.h"
+ #include "coherency.h"
+ #include "mvebu-soc-id.h"
+
+ /*
+ * Early versions of Armada 375 SoC have a bug where the BootROM
+ * leaves an external data abort pending. The kernel is hit by this
+ * data abort as soon as it enters userspace, because it unmasks the
+ * data aborts at this moment. We register a custom abort handler
+ * below to ignore the first data abort to work around this
+ * problem.
+ */
+ static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
+ struct pt_regs *regs)
+ {
+ static int ignore_first;
+
+ if (!ignore_first && fsr == 0x1406) {
+ ignore_first = 1;
+ return 0;
+ }
+
+ return 1;
+ }
+
+ static void __init mvebu_timer_and_clk_init(void)
+ {
+ of_clk_init(NULL);
+ clocksource_of_init();
+ coherency_init();
+ BUG_ON(mvebu_mbus_dt_init());
+ #ifdef CONFIG_CACHE_L2X0
+ l2x0_of_init(0, ~0UL);
+ #endif
+
+ if (of_machine_is_compatible("marvell,armada375"))
+ hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
+ "imprecise external abort");
+ }
+
+ static void __init i2c_quirk(void)
+ {
+ struct device_node *np;
+ u32 dev, rev;
+
+ /*
+ * Only revisons more recent than A0 support the offload
+ * mechanism. We can exit only if we are sure that we can
+ * get the SoC revision and it is more recent than A0.
+ */
+ if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV)
+ return;
+
+ for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
+ struct property *new_compat;
+
+ new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
+
+ new_compat->name = kstrdup("compatible", GFP_KERNEL);
+ new_compat->length = sizeof("marvell,mv78230-a0-i2c");
+ new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
+ GFP_KERNEL);
+
+ of_update_property(np, new_compat);
+ }
+ return;
+ }
+
+ static void __init mvebu_dt_init(void)
+ {
+ if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
+ i2c_quirk();
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+
+ static const char * const armada_370_xp_dt_compat[] = {
+ "marvell,armada-370-xp",
+ NULL,
+ };
+
+ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
+ .smp = smp_ops(armada_xp_smp_ops),
+ .init_machine = mvebu_dt_init,
+ .init_time = mvebu_timer_and_clk_init,
+ .restart = mvebu_restart,
+ .dt_compat = armada_370_xp_dt_compat,
+ MACHINE_END
+
+ static const char * const armada_375_dt_compat[] = {
+ "marvell,armada375",
+ NULL,
+ };
+
+ DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
+ .init_time = mvebu_timer_and_clk_init,
+ .restart = mvebu_restart,
+ .dt_compat = armada_375_dt_compat,
+ MACHINE_END
+
+ static const char * const armada_38x_dt_compat[] = {
+ "marvell,armada380",
+ "marvell,armada385",
+ NULL,
+ };
+
+ DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
+ .init_time = mvebu_timer_and_clk_init,
+ .restart = mvebu_restart,
+ .dt_compat = armada_38x_dt_compat,
+ MACHINE_END
select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE
select SOC_HAS_OMAP2_SDRC
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
config ARCH_OMAP4
bool "TI OMAP4"
select PL310_ERRATA_727915
select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select MACH_OMAP_GENERIC
select OMAP_DM_TIMER
select PINCTRL
- select PROC_DEVICETREE if PROC_FS
select SOC_BUS
select TI_PRIV_EDMA
help
depends on ARCH_OMAP3
default y
- config OMAP_PACKAGE_ZAF
- bool
-
- config OMAP_PACKAGE_ZAC
- bool
-
config OMAP_PACKAGE_CBC
bool
default y
select MACH_NOKIA_N810
select MACH_NOKIA_N810_WIMAX
- select OMAP_PACKAGE_ZAC
config MACH_NOKIA_RX51
bool "Nokia N900 (RX-51) phone"
* stuff is inherited for free
*/
- if (!ret)
+ if (!ret && clk_get_parent(hw->clk) != new_parent)
__clk_reparent(hw->clk, new_parent);
return 0;
/* Clock control for DPLL outputs */
+/* Find the parent DPLL for the given clkoutx2 clock */
+static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
+{
+ struct clk_hw_omap *pclk = NULL;
+ struct clk *parent;
+
+ /* Walk up the parents of clk, looking for a DPLL */
+ do {
+ do {
+ parent = __clk_get_parent(hw->clk);
+ hw = __clk_get_hw(parent);
+ } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
+ if (!hw)
+ break;
+ pclk = to_clk_hw_omap(hw);
+ } while (pclk && !pclk->dpll_data);
+
+ /* clk does not have a DPLL as a parent? error in the clock data */
+ if (!pclk) {
+ WARN_ON(1);
+ return NULL;
+ }
+
+ return pclk;
+}
+
/**
* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
* @clk: DPLL output struct clk
unsigned long rate;
u32 v;
struct clk_hw_omap *pclk = NULL;
- struct clk *parent;
if (!parent_rate)
return 0;
- /* Walk up the parents of clk, looking for a DPLL */
- do {
- do {
- parent = __clk_get_parent(hw->clk);
- hw = __clk_get_hw(parent);
- } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
- if (!hw)
- break;
- pclk = to_clk_hw_omap(hw);
- } while (pclk && !pclk->dpll_data);
+ pclk = omap3_find_clkoutx2_dpll(hw);
- /* clk does not have a DPLL as a parent? error in the clock data */
- if (!pclk) {
- WARN_ON(1);
+ if (!pclk)
return 0;
- }
dd = pclk->dpll_data;
return rate;
}
+int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ return 0;
+}
+
+long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ const struct dpll_data *dd;
+ u32 v;
+ struct clk_hw_omap *pclk = NULL;
+
+ if (!*prate)
+ return 0;
+
+ pclk = omap3_find_clkoutx2_dpll(hw);
+
+ if (!pclk)
+ return 0;
+
+ dd = pclk->dpll_data;
+
+ /* TYPE J does not have a clkoutx2 */
+ if (dd->flags & DPLL_J_TYPE) {
+ *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);
+ return *prate;
+ }
+
+ WARN_ON(!dd->enable_mask);
+
+ v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
+ v >>= __ffs(dd->enable_mask);
+
+ /* If in bypass, the rate is fixed to the bypass rate*/
+ if (v != OMAP3XXX_EN_DPLL_LOCKED)
+ return *prate;
+
+ if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+ unsigned long best_parent;
+
+ best_parent = (rate / 2);
+ *prate = __clk_round_rate(__clk_get_parent(hw->clk),
+ best_parent);
+ }
+
+ return *prate * 2;
+}
+
/* OMAP3/4 non-CORE DPLL clkops */
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
.allow_idle = omap3_dpll_allow_idle,
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
+ #include "prcm43xx.h"
#include "prcm_mpu44xx.h"
#include "soc.h"
dev_inst = OMAP54XX_PRM_DEVICE_INST;
else if (soc_is_dra7xx())
dev_inst = DRA7XX_PRM_DEVICE_INST;
+ else if (soc_is_am43xx())
+ dev_inst = AM43XX_PRM_DEVICE_INST;
else
return;
OMAP4_PRM_RSTCTRL_OFFSET);
v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
- OMAP4430_PRM_DEVICE_INST,
+ dev_inst,
OMAP4_PRM_RSTCTRL_OFFSET);
/* OCP barrier */
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
- OMAP4430_PRM_DEVICE_INST,
+ dev_inst,
OMAP4_PRM_RSTCTRL_OFFSET);
}
select HAVE_ARM_TWD if SMP
select ARM_GIC
select MIGHT_HAVE_PCI
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select NO_IOPORT
select PINCTRL
select ARCH_REQUIRE_GPIOLIB
config ARCH_EMEV2
bool "Emma Mobile EV2"
+ select SYS_SUPPORTS_EM_STI
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
+ select SYS_SUPPORTS_SH_MTU2
config ARCH_R8A7790
bool "R-Car H2 (R8A77900)"
select RENESAS_IRQC
+ select SYS_SUPPORTS_SH_CMT
config ARCH_R8A7791
bool "R-Car M2 (R8A77910)"
select RENESAS_IRQC
+ select SYS_SUPPORTS_SH_CMT
comment "Renesas ARM SoCs Board Type"
select ARM_CPU_SUSPEND if PM || CPU_IDLE
select CPU_V7
select SH_CLK_CPG
+ select SYS_SUPPORTS_SH_CMT
+ select SYS_SUPPORTS_SH_TMU
config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select I2C
select SH_CLK_CPG
select RENESAS_INTC_IRQPIN
+ select SYS_SUPPORTS_SH_CMT
+ select SYS_SUPPORTS_SH_TMU
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
select RENESAS_IRQC
select ARCH_HAS_CPUFREQ
select ARCH_HAS_OPP
+ select SYS_SUPPORTS_SH_CMT
+ select SYS_SUPPORTS_SH_TMU
config ARCH_R8A7740
bool "R-Mobile A1 (R8A77400)"
select CPU_V7
select SH_CLK_CPG
select RENESAS_INTC_IRQPIN
+ select SYS_SUPPORTS_SH_CMT
+ select SYS_SUPPORTS_SH_TMU
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select CPU_V7
select SH_CLK_CPG
select ARM_GIC
- select USB_ARCH_HAS_EHCI
- select USB_ARCH_HAS_OHCI
+ select SYS_SUPPORTS_SH_TMU
config ARCH_R8A7779
bool "R-Car H1 (R8A77790)"
select ARM_GIC
select CPU_V7
select SH_CLK_CPG
- select USB_ARCH_HAS_EHCI
- select USB_ARCH_HAS_OHCI
select RENESAS_INTC_IRQPIN
+ select SYS_SUPPORTS_SH_TMU
config ARCH_R8A7790
bool "R-Car H2 (R8A77900)"
select MIGHT_HAVE_PCI
select SH_CLK_CPG
select RENESAS_IRQC
+ select SYS_SUPPORTS_SH_CMT
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
config ARCH_R8A7791
bool "R-Car M2 (R8A77910)"
select MIGHT_HAVE_PCI
select SH_CLK_CPG
select RENESAS_IRQC
+ select SYS_SUPPORTS_SH_CMT
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
config ARCH_EMEV2
bool "Emma Mobile EV2"
select MIGHT_HAVE_PCI
select USE_OF
select AUTO_ZRELADDR
+ select SYS_SUPPORTS_EM_STI
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select ARM_GIC
select CPU_V7
select SH_CLK_CPG
+ select SYS_SUPPORTS_SH_MTU2
comment "Renesas ARM SoCs Board Type"
want to select a HZ value such as 128 that can evenly divide RCLK.
A HZ value that does not divide evenly may cause timer drift.
-config SH_TIMER_CMT
- bool "CMT timer driver"
- default y
- help
- This enables build of the CMT timer driver.
-
-config SH_TIMER_TMU
- bool "TMU timer driver"
- default y
- help
- This enables build of the TMU timer driver.
-
-config EM_TIMER_STI
- bool "STI timer driver"
- default y
- help
- This enables build of the STI timer driver.
-
endmenu
endif
# SA110
config CPU_SA110
- bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
+ bool
select CPU_32v3 if ARCH_RPC
select CPU_32v4 if !ARCH_RPC
select CPU_ABRT_EV4
config CPU_32v6
bool
- select CPU_USE_DOMAINS if CPU_V6 && MMU
select TLS_REG_EMUL if !CPU_32v6K && !MMU
config CPU_32v6K
config SWP_EMULATE
bool "Emulate SWP/SWPB instructions"
- depends on !CPU_USE_DOMAINS && CPU_V7
+ depends on CPU_V7
default y if SMP
select HAVE_PROC_CPU if PROC_FS
help
config CACHE_FEROCEON_L2
bool "Enable the Feroceon L2 cache controller"
- depends on ARCH_KIRKWOOD || ARCH_MV78XX0
+ depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU
default y
select OUTER_CACHE
help
*/
#include <linux/init.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
#include <linux/highmem.h>
+ #include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
- #include <plat/cache-feroceon-l2.h>
+ #include <asm/hardware/cache-feroceon-l2.h>
+
+ #define L2_WRITETHROUGH_KIRKWOOD BIT(4)
/*
* Low-level cache maintenance operations.
enable_icache();
if (d)
enable_dcache();
- }
+ } else
+ pr_err(FW_BUG
+ "Feroceon L2: bootloader left the L2 cache on!\n");
}
void __init feroceon_l2_init(int __l2_wt_override)
printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
l2_wt_override ? ", in WT override mode" : "");
}
+ #ifdef CONFIG_OF
+ static const struct of_device_id feroceon_ids[] __initconst = {
+ { .compatible = "marvell,kirkwood-cache"},
+ { .compatible = "marvell,feroceon-cache"},
+ {}
+ };
+
+ int __init feroceon_of_init(void)
+ {
+ struct device_node *node;
+ void __iomem *base;
+ bool l2_wt_override = false;
+ struct resource res;
+
+ #if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
+ l2_wt_override = true;
+ #endif
+
+ node = of_find_matching_node(NULL, feroceon_ids);
+ if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
+ if (of_address_to_resource(node, 0, &res))
+ return -ENODEV;
+
+ base = ioremap(res.start, resource_size(&res));
+ if (!base)
+ return -ENOMEM;
+
+ if (l2_wt_override)
+ writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
+ else
+ writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
+ }
+
+ feroceon_l2_init(l2_wt_override);
+
+ return 0;
+ }
+ #endif
obj-$(CONFIG_METAG) += irq-metag-ext.o
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
+ obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
+obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
obj-$(CONFIG_ARM_GIC) += irq-gic.o
obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
#define CLK_OF_TABLES()
#endif
+#ifdef CONFIG_OF_RESERVED_MEM
+#define RESERVEDMEM_OF_TABLES() \
+ . = ALIGN(8); \
+ VMLINUX_SYMBOL(__reservedmem_of_table) = .; \
+ *(__reservedmem_of_table) \
+ *(__reservedmem_of_table_end)
+#else
+#define RESERVEDMEM_OF_TABLES()
+#endif
+
+ #ifdef CONFIG_SMP
+ #define CPU_METHOD_OF_TABLES() . = ALIGN(8); \
+ VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \
+ *(__cpu_method_of_table) \
+ VMLINUX_SYMBOL(__cpu_method_of_table_end) = .;
+ #else
+ #define CPU_METHOD_OF_TABLES()
+ #endif
+
#define KERNEL_DTB() \
STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__dtb_start) = .; \
TRACE_SYSCALLS() \
MEM_DISCARD(init.rodata) \
CLK_OF_TABLES() \
+ RESERVEDMEM_OF_TABLES() \
CLKSRC_OF_TABLES() \
+ CPU_METHOD_OF_TABLES() \
KERNEL_DTB() \
IRQCHIP_OF_MATCH_TABLE()
projects / linux.git / commitdiff