]> Git Repo - linux.git/commitdiff
Merge branch 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
authorLinus Torvalds <[email protected]>
Fri, 14 Oct 2016 18:41:28 +0000 (11:41 -0700)
committerLinus Torvalds <[email protected]>
Fri, 14 Oct 2016 18:41:28 +0000 (11:41 -0700)
Pull libata updates from Tejun Heo:
 - Write same support added
 - Minor ahci MSIX irq handling updates
 - Non-critical SCSI command translation fixes
 - Controller specific changes

* 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
  ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC"
  libata: remove <asm-generic/libata-portmap.h>
  libata: remove unused definitions from <asm/libata-portmap.h>
  pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
  ata: Replace BUG() with BUG_ON().
  ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc.
  libata: Some drives failing on SCT Write Same
  ahci: use pci_alloc_irq_vectors
  libata: SCT Write Same handle ATA_DFLAG_PIO
  libata: SCT Write Same / DSM Trim
  libata: Add support for SCT Write Same
  libata: Safely overwrite attached page in WRITE SAME xlat
  ahci: also use a per-port lock for the multi-MSIX case
  ARM: dts: STiH407-family: Add ports-implemented property in sata nodes
  ahci: st: Add ports-implemented property in support
  ahci: qoriq: enable snoopable sata read and write
  ahci: qoriq: adjust sata parameter
  libata-scsi: fix MODE SELECT translation for Control mode page
  libata-scsi: use u8 array to store mode page copy

1  2 
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

index 58635f7f4668abbc8ebfd52ba96abafe63d817db,e8e4c3ed1b7ec9784e95aa8102162d711f7aa804..220ac7057d1284fa97d5ccf1787e09a2aafd60a4
  
        timer {
                compatible = "arm,armv8-timer";
 -              interrupts = <1 13 0x1>, /* Physical Secure PPI */
 -                           <1 14 0x1>, /* Physical Non-Secure PPI */
 -                           <1 11 0x1>, /* Virtual PPI */
 -                           <1 10 0x1>; /* Hypervisor PPI */
 +              interrupts = <1 13 0xf08>, /* Physical Secure PPI */
 +                           <1 14 0xf08>, /* Physical Non-Secure PPI */
 +                           <1 11 0xf08>, /* Virtual PPI */
 +                           <1 10 0xf08>; /* Hypervisor PPI */
        };
  
        pmu {
                        bus-width = <4>;
                };
  
 +              ddr: memory-controller@1080000 {
 +                      compatible = "fsl,qoriq-memory-controller";
 +                      reg = <0x0 0x1080000 0x0 0x1000>;
 +                      interrupts = <0 144 0x4>;
 +                      big-endian;
 +              };
 +
                dspi0: dspi@2100000 {
                        compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
                        #address-cells = <1>;
                };
  
                sata: sata@3200000 {
-                       compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
+                       compatible = "fsl,ls1043a-ahci";
                        reg = <0x0 0x3200000 0x0 0x10000>;
                        interrupts = <0 69 0x4>;
                        clocks = <&clockgen 4 0>;
+                       dma-coherent;
                };
  
                msi1: msi-controller1@1571000 {
index d1059765dfee4ac41831ff5faf1f2d71df9fc241,5ead17c05bb832cbaae063da289e69342b3486ee..337da90bd7dade6df0d74d49a9794b6b20cc8510
  
        timer {
                compatible = "arm,armv8-timer";
 -              interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
 -                           <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
 -                           <1 11 0x8>, /* Virtual PPI, active-low */
 -                           <1 10 0x8>; /* Hypervisor PPI, active-low */
 +              interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
 +                           <1 14 4>, /* Physical Non-Secure PPI, active-low */
 +                           <1 11 4>, /* Virtual PPI, active-low */
 +                           <1 10 4>; /* Hypervisor PPI, active-low */
        };
  
        pmu {
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
 +                      dma-coherent;
                        num-lanes = <4>;
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
 +                      dma-coherent;
                        num-lanes = <4>;
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
 +                      dma-coherent;
                        num-lanes = <8>;
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
 +                      dma-coherent;
                        num-lanes = <4>;
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
                        reg = <0x0 0x3200000 0x0 0x10000>;
                        interrupts = <0 133 0x4>; /* Level high type */
                        clocks = <&clockgen 4 3>;
+                       dma-coherent;
                };
  
                sata1: sata@3210000 {
                        reg = <0x0 0x3210000 0x0 0x10000>;
                        interrupts = <0 136 0x4>; /* Level high type */
                        clocks = <&clockgen 4 3>;
+                       dma-coherent;
                };
  
                usb0: usb3@3100000 {
                        interrupts = <0 12 4>;
                };
        };
 +
 +      ddr1: memory-controller@1080000 {
 +              compatible = "fsl,qoriq-memory-controller";
 +              reg = <0x0 0x1080000 0x0 0x1000>;
 +              interrupts = <0 17 0x4>;
 +              little-endian;
 +      };
 +
 +      ddr2: memory-controller@1090000 {
 +              compatible = "fsl,qoriq-memory-controller";
 +              reg = <0x0 0x1090000 0x0 0x1000>;
 +              interrupts = <0 18 0x4>;
 +              little-endian;
 +      };
  };
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