select ARCH_32BIT_OFF_T
select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
select ARCH_HAS_BINFMT_FLAT
+ select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CPU_FINALIZE_INIT if MMU
select ARCH_HAS_CURRENT_STACK_POINTER
select ARCH_HAS_DEBUG_VIRTUAL if MMU
select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_KEEP_MEMBLOCK
- select ARCH_HAS_UBSAN_SANITIZE_ALL
+ select ARCH_HAS_UBSAN
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
select ARCH_SUPPORTS_ATOMIC_RMW
+ ++ select ARCH_SUPPORTS_CFI_CLANG
select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
select ARCH_SUPPORTS_PER_VMA_LOCK
select ARCH_USE_BUILTIN_BSWAP
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_NMI
select HAVE_OPTPROBES if !THUMB2_KERNEL
+ select HAVE_PAGE_SIZE_4KB
select HAVE_PCI if MMU
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
config IWMMXT
bool "Enable iWMMXt support"
- depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
- default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
+ depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
+ default y if PXA27x || PXA3xx || ARCH_MMP
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
consumed by page tables. Setting this option will allow
user-space 2nd level page tables to reside in high memory.
--- config CPU_SW_DOMAIN_PAN
--- bool "Enable use of CPU domains to implement privileged no-access"
--- depends on MMU && !ARM_LPAE
+++ config ARM_PAN
+++ bool "Enable privileged no-access"
+++ depends on MMU
default y
help
Increase kernel security by ensuring that normal kernel accesses
by ensuring that magic values (such as LIST_POISON) will always
fault when dereferenced.
+++ The implementation uses CPU domains when !CONFIG_ARM_LPAE and
+++ disabling of TTBR0 page table walks with CONFIG_ARM_LPAE.
+++
+++ config CPU_SW_DOMAIN_PAN
+++ def_bool y
+++ depends on ARM_PAN && !ARM_LPAE
+++ help
+++ Enable use of CPU domains to implement privileged no-access.
+++
CPUs with low-vector mappings use a best-efforts implementation.
Their lower 1MB needs to remain accessible for the vectors, but
the remainder of userspace will become appropriately inaccessible.
+++ config CPU_TTBR0_PAN
+++ def_bool y
+++ depends on ARM_PAN && ARM_LPAE
+++ help
+++ Enable privileged no-access by disabling TTBR0 page table walks when
+++ running in kernel mode.
+++
config HW_PERF_EVENTS
def_bool y
depends on ARM_PMU
mutex_unlock(&clocks_mutex);
}
- #define MAX_DEV_ID 20
+ #define MAX_DEV_ID 24
#define MAX_CON_ID 16
struct clk_lookup_alloc {
va_list ap)
{
struct clk_lookup_alloc *cla;
++ + struct va_format vaf;
++ + const char *failure;
++ + va_list ap_copy;
++ + size_t max_size;
++ + ssize_t res;
cla = kzalloc(sizeof(*cla), GFP_KERNEL);
if (!cla)
return NULL;
++ + va_copy(ap_copy, ap);
++ +
cla->cl.clk_hw = hw;
if (con_id) {
-- - strscpy(cla->con_id, con_id, sizeof(cla->con_id));
++ + res = strscpy(cla->con_id, con_id, sizeof(cla->con_id));
++ + if (res < 0) {
++ + max_size = sizeof(cla->con_id);
++ + failure = "connection";
++ + goto fail;
++ + }
cla->cl.con_id = cla->con_id;
}
if (dev_fmt) {
-- - vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
++ + res = vsnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
++ + if (res >= sizeof(cla->dev_id)) {
++ + max_size = sizeof(cla->dev_id);
++ + failure = "device";
++ + goto fail;
++ + }
cla->cl.dev_id = cla->dev_id;
}
++ + va_end(ap_copy);
++ +
return &cla->cl;
++ +
++ +fail:
++ + if (dev_fmt)
++ + vaf.fmt = dev_fmt;
++ + else
++ + vaf.fmt = "null-device";
++ + vaf.va = &ap_copy;
++ + pr_err("%pV:%s: %s ID is greater than %zu\n",
++ + &vaf, con_id, failure, max_size);
++ + va_end(ap_copy);
++ + kfree(cla);
++ + return NULL;
}
static struct clk_lookup *