drm/amd/powerplay: correct power reading on fiji

Set sampling period as 500ms to provide a smooth power
reading output. Also, correct the register for power
reading.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 48187acac59e7bf1181565e852584fe856f26efc..83d3d935f3acc899cf682d7e4fa616094e746a58 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3491,14 +3491,14 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
 
        smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                                                       ixSMU_PM_STATUS_94, 0);
+                                                       ixSMU_PM_STATUS_95, 0);
 
        for (i = 0; i < 10; i++) {
-               mdelay(1);
+               mdelay(500);
                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
                tmp = cgs_read_ind_register(hwmgr->device,
                                                CGS_IND_REG__SMC,
-                                               ixSMU_PM_STATUS_94);
+                                               ixSMU_PM_STATUS_95);
                if (tmp != 0)
                        break;
        }