drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz

The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.

Signed-off-by: Kaustabh Chakraborty <[email protected]>
Signed-off-by: Inki Dae <[email protected]>

diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index e994779694f03c1a175ab0dcf939a7eb78731e5e..76a3f4b0341dfd63372f22681e0bef17f9b6407d 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx)
 static u32 decon_calc_clkdiv(struct decon_context *ctx,
                const struct drm_display_mode *mode)
 {
-       unsigned long ideal_clk = mode->clock;
+       unsigned long ideal_clk = mode->clock * 1000;
        u32 clkdiv;
 
        /* Find the clock divider value that gets us closest to ideal_clk */