]> Git Repo - linux.git/commitdiff
drm/xe: Write all slices if its mcr register
authorTejas Upadhyay <[email protected]>
Wed, 14 Aug 2024 09:56:13 +0000 (15:26 +0530)
committerLucas De Marchi <[email protected]>
Wed, 14 Aug 2024 19:29:09 +0000 (12:29 -0700)
Register GAMREQSTRM_CTRL should be considered mcr register
which should write to all slices as per documentation.

Bspec: 71185
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Reviewed-by: Matt Roper <[email protected]>
Signed-off-by: Tejas Upadhyay <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Signed-off-by: Lucas De Marchi <[email protected]>
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_gt.c

index 5f33dee35f8a07cd7709dcd58fe16b846afd3aca..aeb17fcb27acce79a5ec3254144489837f275f23 100644 (file)
@@ -83,7 +83,7 @@
 #define STATELESS_COMPRESSION_CTRL             XE_REG(0x4148)
 #define   UNIFIED_COMPRESSION_FORMAT           REG_GENMASK(3, 0)
 
-#define XE2_GAMREQSTRM_CTRL                    XE_REG(0x4194)
+#define XE2_GAMREQSTRM_CTRL                    XE_REG_MCR(0x4194)
 #define   CG_DIS_CNTLBUS                       REG_BIT(6)
 
 #define CCS_AUX_INV                            XE_REG(0x4208)
index 238c7d1053f0c3135bb61a148f23fd8c971b8363..224c137967c3cd7f9dcbbd3752c3c51a41711a61 100644 (file)
@@ -110,9 +110,9 @@ static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
 
        if (!xe_gt_is_media_type(gt)) {
                xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
-               reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+               reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
                reg |= CG_DIS_CNTLBUS;
-               xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+               xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
        }
 
        xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3);
@@ -134,9 +134,9 @@ static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
        if (WARN_ON(err))
                return;
 
-       reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+       reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
        reg &= ~CG_DIS_CNTLBUS;
-       xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+       xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
 
        xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
 }
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