drm/xe: Move IRQ-related registers to dedicated header

IRQ registers have a well-defined scope and make sense to collect in a
dedicated header file.  This also reduces confusion about the GT IRQ
registers --- even though those registers relate to the GTs, they
actually live outside the GT (in the sgunit) and thus do not need to
worry about GT-specific register concepts like forcewake, steering, etc.

Signed-off-by: Matt Roper <[email protected]>
Reviewed-by: Gustavo Sousa <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 94ac537f251456e285142e41d57de9b7d98e579c..26b2cae11d46de98c98107d1c0249d3a929aaf7e 100644 (file)
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -4,7 +4,7 @@
  */
 
 #include "xe_display.h"
-#include "regs/xe_regs.h"
+#include "regs/xe_irq_regs.h"
 
 #include <linux/fb.h>
 

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 8d8f6a113a86628596900e7f1dc22c2925c5498a..fb80042cbe0d98a9ce186d81fbf154d2aa762240 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -567,62 +567,4 @@
 #define GT_PERF_STATUS                         XE_REG(0x1381b4)
 #define   VOLTAGE_MASK                         REG_GENMASK(10, 0)
 
-/*
- * Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
- *       On newer platforms, VFs are using memory-based interrupts instead.
- *       However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
- */
-
-#define GT_INTR_DW(x)                          XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
-#define   INTR_GSC                             REG_BIT(31)
-#define   INTR_GUC                             REG_BIT(25)
-#define   INTR_MGUC                            REG_BIT(24)
-#define   INTR_BCS8                            REG_BIT(23)
-#define   INTR_BCS(x)                          REG_BIT(15 - (x))
-#define   INTR_CCS(x)                          REG_BIT(4 + (x))
-#define   INTR_RCS0                            REG_BIT(0)
-#define   INTR_VECS(x)                         REG_BIT(31 - (x))
-#define   INTR_VCS(x)                          REG_BIT(x)
-
-#define RENDER_COPY_INTR_ENABLE                        XE_REG(0x190030, XE_REG_OPTION_VF)
-#define VCS_VECS_INTR_ENABLE                   XE_REG(0x190034, XE_REG_OPTION_VF)
-#define GUC_SG_INTR_ENABLE                     XE_REG(0x190038, XE_REG_OPTION_VF)
-#define   ENGINE1_MASK                         REG_GENMASK(31, 16)
-#define   ENGINE0_MASK                         REG_GENMASK(15, 0)
-#define GPM_WGBOXPERF_INTR_ENABLE              XE_REG(0x19003c, XE_REG_OPTION_VF)
-#define GUNIT_GSC_INTR_ENABLE                  XE_REG(0x190044, XE_REG_OPTION_VF)
-#define CCS_RSVD_INTR_ENABLE                   XE_REG(0x190048, XE_REG_OPTION_VF)
-
-#define INTR_IDENTITY_REG(x)                   XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
-#define   INTR_DATA_VALID                      REG_BIT(31)
-#define   INTR_ENGINE_INSTANCE(x)              REG_FIELD_GET(GENMASK(25, 20), x)
-#define   INTR_ENGINE_CLASS(x)                 REG_FIELD_GET(GENMASK(18, 16), x)
-#define   INTR_ENGINE_INTR(x)                  REG_FIELD_GET(GENMASK(15, 0), x)
-#define   OTHER_GUC_INSTANCE                   0
-#define   OTHER_GSC_HECI2_INSTANCE             3
-#define   OTHER_GSC_INSTANCE                   6
-
-#define IIR_REG_SELECTOR(x)                    XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
-#define RCS0_RSVD_INTR_MASK                    XE_REG(0x190090, XE_REG_OPTION_VF)
-#define BCS_RSVD_INTR_MASK                     XE_REG(0x1900a0, XE_REG_OPTION_VF)
-#define VCS0_VCS1_INTR_MASK                    XE_REG(0x1900a8, XE_REG_OPTION_VF)
-#define VCS2_VCS3_INTR_MASK                    XE_REG(0x1900ac, XE_REG_OPTION_VF)
-#define VECS0_VECS1_INTR_MASK                  XE_REG(0x1900d0, XE_REG_OPTION_VF)
-#define HECI2_RSVD_INTR_MASK                   XE_REG(0x1900e4)
-#define GUC_SG_INTR_MASK                       XE_REG(0x1900e8, XE_REG_OPTION_VF)
-#define GPM_WGBOXPERF_INTR_MASK                        XE_REG(0x1900ec, XE_REG_OPTION_VF)
-#define GUNIT_GSC_INTR_MASK                    XE_REG(0x1900f4, XE_REG_OPTION_VF)
-#define CCS0_CCS1_INTR_MASK                    XE_REG(0x190100)
-#define CCS2_CCS3_INTR_MASK                    XE_REG(0x190104)
-#define XEHPC_BCS1_BCS2_INTR_MASK              XE_REG(0x190110)
-#define XEHPC_BCS3_BCS4_INTR_MASK              XE_REG(0x190114)
-#define XEHPC_BCS5_BCS6_INTR_MASK              XE_REG(0x190118)
-#define XEHPC_BCS7_BCS8_INTR_MASK              XE_REG(0x19011c)
-#define   GT_WAIT_SEMAPHORE_INTERRUPT          REG_BIT(11)
-#define   GT_CONTEXT_SWITCH_INTERRUPT          REG_BIT(8)
-#define   GSC_ER_COMPLETE                      REG_BIT(5)
-#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT   REG_BIT(4)
-#define   GT_CS_MASTER_ERROR_INTERRUPT         REG_BIT(3)
-#define   GT_RENDER_USER_INTERRUPT             REG_BIT(0)
-
 #endif

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
new file mode 100644 (file)
index 0000000..1776b3f
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+#ifndef _XE_IRQ_REGS_H_
+#define _XE_IRQ_REGS_H_
+
+#include "regs/xe_reg_defs.h"
+
+#define PCU_IRQ_OFFSET                         0x444e0
+#define GU_MISC_IRQ_OFFSET                     0x444f0
+#define   GU_MISC_GSE                          REG_BIT(27)
+
+#define DG1_MSTR_TILE_INTR                     XE_REG(0x190008)
+#define   DG1_MSTR_IRQ                         REG_BIT(31)
+#define   DG1_MSTR_TILE(t)                     REG_BIT(t)
+
+#define GFX_MSTR_IRQ                           XE_REG(0x190010, XE_REG_OPTION_VF)
+#define   MASTER_IRQ                           REG_BIT(31)
+#define   GU_MISC_IRQ                          REG_BIT(29)
+#define   DISPLAY_IRQ                          REG_BIT(16)
+#define   GT_DW_IRQ(x)                         REG_BIT(x)
+
+/*
+ * Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
+ *       On newer platforms, VFs are using memory-based interrupts instead.
+ *       However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
+ */
+
+#define GT_INTR_DW(x)                          XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
+#define   INTR_GSC                             REG_BIT(31)
+#define   INTR_GUC                             REG_BIT(25)
+#define   INTR_MGUC                            REG_BIT(24)
+#define   INTR_BCS8                            REG_BIT(23)
+#define   INTR_BCS(x)                          REG_BIT(15 - (x))
+#define   INTR_CCS(x)                          REG_BIT(4 + (x))
+#define   INTR_RCS0                            REG_BIT(0)
+#define   INTR_VECS(x)                         REG_BIT(31 - (x))
+#define   INTR_VCS(x)                          REG_BIT(x)
+
+#define RENDER_COPY_INTR_ENABLE                        XE_REG(0x190030, XE_REG_OPTION_VF)
+#define VCS_VECS_INTR_ENABLE                   XE_REG(0x190034, XE_REG_OPTION_VF)
+#define GUC_SG_INTR_ENABLE                     XE_REG(0x190038, XE_REG_OPTION_VF)
+#define   ENGINE1_MASK                         REG_GENMASK(31, 16)
+#define   ENGINE0_MASK                         REG_GENMASK(15, 0)
+#define GPM_WGBOXPERF_INTR_ENABLE              XE_REG(0x19003c, XE_REG_OPTION_VF)
+#define GUNIT_GSC_INTR_ENABLE                  XE_REG(0x190044, XE_REG_OPTION_VF)
+#define CCS_RSVD_INTR_ENABLE                   XE_REG(0x190048, XE_REG_OPTION_VF)
+
+#define INTR_IDENTITY_REG(x)                   XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
+#define   INTR_DATA_VALID                      REG_BIT(31)
+#define   INTR_ENGINE_INSTANCE(x)              REG_FIELD_GET(GENMASK(25, 20), x)
+#define   INTR_ENGINE_CLASS(x)                 REG_FIELD_GET(GENMASK(18, 16), x)
+#define   INTR_ENGINE_INTR(x)                  REG_FIELD_GET(GENMASK(15, 0), x)
+#define   OTHER_GUC_INSTANCE                   0
+#define   OTHER_GSC_HECI2_INSTANCE             3
+#define   OTHER_GSC_INSTANCE                   6
+
+#define IIR_REG_SELECTOR(x)                    XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
+#define RCS0_RSVD_INTR_MASK                    XE_REG(0x190090, XE_REG_OPTION_VF)
+#define BCS_RSVD_INTR_MASK                     XE_REG(0x1900a0, XE_REG_OPTION_VF)
+#define VCS0_VCS1_INTR_MASK                    XE_REG(0x1900a8, XE_REG_OPTION_VF)
+#define VCS2_VCS3_INTR_MASK                    XE_REG(0x1900ac, XE_REG_OPTION_VF)
+#define VECS0_VECS1_INTR_MASK                  XE_REG(0x1900d0, XE_REG_OPTION_VF)
+#define HECI2_RSVD_INTR_MASK                   XE_REG(0x1900e4)
+#define GUC_SG_INTR_MASK                       XE_REG(0x1900e8, XE_REG_OPTION_VF)
+#define GPM_WGBOXPERF_INTR_MASK                        XE_REG(0x1900ec, XE_REG_OPTION_VF)
+#define GUNIT_GSC_INTR_MASK                    XE_REG(0x1900f4, XE_REG_OPTION_VF)
+#define CCS0_CCS1_INTR_MASK                    XE_REG(0x190100)
+#define CCS2_CCS3_INTR_MASK                    XE_REG(0x190104)
+#define XEHPC_BCS1_BCS2_INTR_MASK              XE_REG(0x190110)
+#define XEHPC_BCS3_BCS4_INTR_MASK              XE_REG(0x190114)
+#define XEHPC_BCS5_BCS6_INTR_MASK              XE_REG(0x190118)
+#define XEHPC_BCS7_BCS8_INTR_MASK              XE_REG(0x19011c)
+#define   GT_WAIT_SEMAPHORE_INTERRUPT          REG_BIT(11)
+#define   GT_CONTEXT_SWITCH_INTERRUPT          REG_BIT(8)
+#define   GSC_ER_COMPLETE                      REG_BIT(5)
+#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT   REG_BIT(4)
+#define   GT_CS_MASTER_ERROR_INTERRUPT         REG_BIT(3)
+#define   GT_RENDER_USER_INTERRUPT             REG_BIT(0)
+
+#endif

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index dfa869f0ddddc4495c21f3713c57cd7811cc3d76..3293172b01285df5ce962f19af141a24e4e84163 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -11,10 +11,6 @@
 #define   TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK       REG_GENMASK(15, 12)
 #define   TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK           REG_GENMASK(9, 0)
 
-#define PCU_IRQ_OFFSET                         0x444e0
-#define GU_MISC_IRQ_OFFSET                     0x444f0
-#define   GU_MISC_GSE                          REG_BIT(27)
-
 #define GU_CNTL_PROTECTED                      XE_REG(0x10100C)
 #define   DRIVERINT_FLR_DIS                    REG_BIT(31)
 
@@ -57,16 +53,6 @@
 #define MTL_MPE_FREQUENCY                      XE_REG(0x13802c)
 #define   MTL_RPE_MASK                         REG_GENMASK(8, 0)
 
-#define DG1_MSTR_TILE_INTR                     XE_REG(0x190008)
-#define   DG1_MSTR_IRQ                         REG_BIT(31)
-#define   DG1_MSTR_TILE(t)                     REG_BIT(t)
-
-#define GFX_MSTR_IRQ                           XE_REG(0x190010, XE_REG_OPTION_VF)
-#define   MASTER_IRQ                           REG_BIT(31)
-#define   GU_MISC_IRQ                          REG_BIT(29)
-#define   DISPLAY_IRQ                          REG_BIT(16)
-#define   GT_DW_IRQ(x)                         REG_BIT(x)
-
 #define VF_CAP_REG                             XE_REG(0x1901f8, XE_REG_OPTION_VF)
 #define   VF_CAP                               REG_BIT(0)
 

diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
index 9cb326af5931e38f2c7bc2e0a6ef98d9e03767ca..783b09bf368160e142cdbf624291d9278be20196 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gsc.c
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -34,6 +34,7 @@
 #include "instructions/xe_gsc_commands.h"
 #include "regs/xe_gsc_regs.h"
 #include "regs/xe_gt_regs.h"
+#include "regs/xe_irq_regs.h"
 
 static struct xe_gt *
 gsc_to_gt(struct xe_gsc *gsc)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index b6cd5e941f1971b0fae9279b3c9248b7a4f9deff..c2ddf883702b3b19d2ec52780f15d02c02f946a6 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -14,6 +14,7 @@
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_gtt_defs.h"
 #include "regs/xe_guc_regs.h"
+#include "regs/xe_irq_regs.h"
 #include "xe_bo.h"
 #include "xe_device.h"
 #include "xe_force_wake.h"

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index d7408d06ee207b88ac0f5e356f6b959d067ed94f..ea6d9ef7fab60bc8a01ae7ce52447cb10871857a 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -12,6 +12,7 @@
 
 #include "regs/xe_engine_regs.h"
 #include "regs/xe_gt_regs.h"
+#include "regs/xe_irq_regs.h"
 #include "xe_assert.h"
 #include "xe_bo.h"
 #include "xe_device.h"

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 5eb7775c0fd20f4d4b1c78b80602f8bb310d00b3..b7995ebd54abde767c41b923d17aaf0df8474246 100644 (file)
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -10,8 +10,7 @@
 #include <drm/drm_managed.h>
 
 #include "display/xe_display.h"
-#include "regs/xe_gt_regs.h"
-#include "regs/xe_regs.h"
+#include "regs/xe_irq_regs.h"
 #include "xe_device.h"
 #include "xe_drv.h"
 #include "xe_gsc_proxy.h"

diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 3f8d4ca6430212254d6e0ddb60c6b8adccb243e5..e3610cb90bb9defa1a5c391d816ddf2c80c48cb7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -5,8 +5,8 @@
 
 #include <drm/drm_managed.h>
 
-#include "regs/xe_gt_regs.h"
 #include "regs/xe_guc_regs.h"
+#include "regs/xe_irq_regs.h"
 #include "regs/xe_regs.h"
 
 #include "xe_assert.h"