Merge branch 'mellanox/mlx5-next' into rdma.git for-next

From git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git

This is required to resolve dependencies of the next series of RDMA
patches.

* branch 'mellanox/mlx5-next':
  net/mlx5: Add support for flow table destination number
  net/mlx5: Add forward compatible support for the FTE match data
  net/mlx5: Fix tristate and description for MLX5 module
  net/mlx5: Better return types for CQE API
  net/mlx5: Use ERR_CAST() instead of coding it
  net/mlx5: Add missing SET_DRIVER_VERSION command translation
  net/mlx5: Add XRQ commands definitions
  net/mlx5: Add core support for double vlan push/pop steering action
  net/mlx5: Expose MPEGC (Management PCIe General Configuration) structures
  net/mlx5: FW tracer, add hardware structures
  net/mlx5: fix uaccess beyond "count" in debugfs read/write handlers

Signed-off-by: Jason Gunthorpe <[email protected]>

diff --combined drivers/net/ethernet/mellanox/mlx5/core/cmd.c
index 7dd878b00196d330207f0852c78f0857f6319803,041c18faea46bd01f7359962fdf13e1f4f77a3d6..381dbfa6a68ea5b27616fc3eb2023e7ee593746a
--- 1/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
--- 2/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c
@@@ -278,6 -278,7 +278,7 @@@ static int mlx5_internal_err_ret_value(
        case MLX5_CMD_OP_DESTROY_PSV:
        case MLX5_CMD_OP_DESTROY_SRQ:
        case MLX5_CMD_OP_DESTROY_XRC_SRQ:
+       case MLX5_CMD_OP_DESTROY_XRQ:
        case MLX5_CMD_OP_DESTROY_DCT:
        case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
        case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
@@@ -347,6 -348,9 +348,9 @@@
        case MLX5_CMD_OP_CREATE_XRC_SRQ:
        case MLX5_CMD_OP_QUERY_XRC_SRQ:
        case MLX5_CMD_OP_ARM_XRC_SRQ:
+       case MLX5_CMD_OP_CREATE_XRQ:
+       case MLX5_CMD_OP_QUERY_XRQ:
+       case MLX5_CMD_OP_ARM_XRQ:
        case MLX5_CMD_OP_CREATE_DCT:
        case MLX5_CMD_OP_DRAIN_DCT:
        case MLX5_CMD_OP_QUERY_DCT:
@@@ -429,8 -433,6 +433,8 @@@
        case MLX5_CMD_OP_FPGA_QUERY_QP:
        case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
        case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
 +      case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
 +      case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
                *status = MLX5_DRIVER_STATUS_ABORTED;
                *synd = MLX5_DRIVER_SYND;
                return -EIO;
@@@ -456,6 -458,7 +460,7 @@@ const char *mlx5_command_str(int comman
        MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
        MLX5_COMMAND_STR_CASE(QUERY_ISSI);
        MLX5_COMMAND_STR_CASE(SET_ISSI);
+       MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
        MLX5_COMMAND_STR_CASE(CREATE_MKEY);
        MLX5_COMMAND_STR_CASE(QUERY_MKEY);
        MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
@@@ -603,11 -606,12 +608,15 @@@
        MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
        MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
        MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
+       MLX5_COMMAND_STR_CASE(CREATE_XRQ);
+       MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
+       MLX5_COMMAND_STR_CASE(QUERY_XRQ);
+       MLX5_COMMAND_STR_CASE(ARM_XRQ);
        MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
        MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
 +      MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
 +      MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
 +      MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
        default: return "unknown command opcode";
        }
  }
@@@ -1037,7 -1041,10 +1046,10 @@@ static ssize_t dbg_write(struct file *f
        if (!dbg->in_msg || !dbg->out_msg)
                return -ENOMEM;
  
-       if (copy_from_user(lbuf, buf, sizeof(lbuf)))
+       if (count < sizeof(lbuf) - 1)
+               return -EINVAL;
+ 
+       if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
                return -EFAULT;
  
        lbuf[sizeof(lbuf) - 1] = 0;
@@@ -1241,21 -1248,12 +1253,12 @@@ static ssize_t data_read(struct file *f
  {
        struct mlx5_core_dev *dev = filp->private_data;
        struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
-       int copy;
- 
-       if (*pos)
-               return 0;
  
        if (!dbg->out_msg)
                return -ENOMEM;
  
-       copy = min_t(int, count, dbg->outlen);
-       if (copy_to_user(buf, dbg->out_msg, copy))
-               return -EFAULT;
- 
-       *pos += copy;
- 
-       return copy;
+       return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
+                                      dbg->outlen);
  }
  
  static const struct file_operations dfops = {
@@@ -1273,19 -1271,11 +1276,11 @@@ static ssize_t outlen_read(struct file 
        char outlen[8];
        int err;
  
-       if (*pos)
-               return 0;
- 
        err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
        if (err < 0)
                return err;
  
-       if (copy_to_user(buf, &outlen, err))
-               return -EFAULT;
- 
-       *pos += err;
- 
-       return err;
+       return simple_read_from_buffer(buf, count, pos, outlen, err);
  }
  
  static ssize_t outlen_write(struct file *filp, const char __user *buf,

diff --combined include/linux/mlx5/mlx5_ifc.h
index 44a6ce01c3bbd3c3341da8f9608e9a6ce460661b,c14b815595056ecc783adc8cb06bcc2975f8aa5c..5e04e2053fd7c4fe5ae1543af2461462586ce500
--- 1/include/linux/mlx5/mlx5_ifc.h
--- 2/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@@ -82,7 -82,6 +82,7 @@@ enum 
  
  enum {
        MLX5_OBJ_TYPE_UCTX = 0x0004,
 +      MLX5_OBJ_TYPE_UMEM = 0x0005,
  };
  
  enum {
@@@ -247,15 -246,12 +247,15 @@@
        MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
        MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
        MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 +      MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
        MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
        MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
        MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
        MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
        MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
        MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 +      MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 +      MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
        MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
        MLX5_CMD_OP_MAX
  };
@@@ -341,7 -337,10 +341,10 @@@ struct mlx5_ifc_flow_table_prop_layout_
        u8         reserved_at_9[0x1];
        u8         pop_vlan[0x1];
        u8         push_vlan[0x1];
-       u8         reserved_at_c[0x14];
+       u8         reserved_at_c[0x1];
+       u8         pop_vlan_2[0x1];
+       u8         push_vlan_2[0x1];
+       u8         reserved_at_f[0x11];
  
        u8         reserved_at_20[0x2];
        u8         log_max_ft_size[0x6];
@@@ -1181,6 -1180,7 +1184,7 @@@ enum mlx5_flow_destination_type 
  
        MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
        MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
+       MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
  };
  
  struct mlx5_ifc_dest_format_struct_bits {
@@@ -2390,6 -2390,8 +2394,8 @@@ enum 
        MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
        MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
        MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
  };
  
  struct mlx5_ifc_vlan_bits {
@@@ -2420,7 -2422,9 +2426,9 @@@ struct mlx5_ifc_flow_context_bits 
  
        u8         modify_header_id[0x20];
  
-       u8         reserved_at_100[0x100];
+       struct mlx5_ifc_vlan_bits push_vlan_2;
+ 
+       u8         reserved_at_120[0xe0];
  
        struct mlx5_ifc_fte_match_param_bits match_value;
  
@@@ -8053,6 -8057,19 +8061,19 @@@ struct mlx5_ifc_peir_reg_bits 
        u8         error_type[0x8];
  };
  
+ struct mlx5_ifc_mpegc_reg_bits {
+       u8         reserved_at_0[0x30];
+       u8         field_select[0x10];
+ 
+       u8         tx_overflow_sense[0x1];
+       u8         mark_cqe[0x1];
+       u8         mark_cnp[0x1];
+       u8         reserved_at_43[0x1b];
+       u8         tx_lossy_overflow_oper[0x2];
+ 
+       u8         reserved_at_60[0x100];
+ };
+ 
  struct mlx5_ifc_pcam_enhanced_features_bits {
        u8         reserved_at_0[0x6d];
        u8         rx_icrc_encapsulated_counter[0x1];
@@@ -8101,7 -8118,11 +8122,11 @@@ struct mlx5_ifc_pcam_reg_bits 
  };
  
  struct mlx5_ifc_mcam_enhanced_features_bits {
-       u8         reserved_at_0[0x7b];
+       u8         reserved_at_0[0x74];
+       u8         mark_tx_action_cnp[0x1];
+       u8         mark_tx_action_cqe[0x1];
+       u8         dynamic_tx_overflow[0x1];
+       u8         reserved_at_77[0x4];
        u8         pcie_outbound_stalled[0x1];
        u8         tx_overflow_buffer_pkt[0x1];
        u8         mtpps_enh_out_per_adj[0x1];
@@@ -8116,7 -8137,11 +8141,11 @@@ struct mlx5_ifc_mcam_access_reg_bits 
        u8         mcqi[0x1];
        u8         reserved_at_1f[0x1];
  
-       u8         regs_95_to_64[0x20];
+       u8         regs_95_to_87[0x9];
+       u8         mpegc[0x1];
+       u8         regs_85_to_68[0x12];
+       u8         tracer_registers[0x4];
+ 
        u8         regs_63_to_32[0x20];
        u8         regs_31_to_0[0x20];
  };
@@@ -9191,4 -9216,61 +9220,61 @@@ struct mlx5_ifc_create_uctx_in_bits 
        struct mlx5_ifc_uctx_bits                     uctx;
  };
  
+ struct mlx5_ifc_mtrc_string_db_param_bits {
+       u8         string_db_base_address[0x20];
+ 
+       u8         reserved_at_20[0x8];
+       u8         string_db_size[0x18];
+ };
+ 
+ struct mlx5_ifc_mtrc_cap_bits {
+       u8         trace_owner[0x1];
+       u8         trace_to_memory[0x1];
+       u8         reserved_at_2[0x4];
+       u8         trc_ver[0x2];
+       u8         reserved_at_8[0x14];
+       u8         num_string_db[0x4];
+ 
+       u8         first_string_trace[0x8];
+       u8         num_string_trace[0x8];
+       u8         reserved_at_30[0x28];
+ 
+       u8         log_max_trace_buffer_size[0x8];
+ 
+       u8         reserved_at_60[0x20];
+ 
+       struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
+ 
+       u8         reserved_at_280[0x180];
+ };
+ 
+ struct mlx5_ifc_mtrc_conf_bits {
+       u8         reserved_at_0[0x1c];
+       u8         trace_mode[0x4];
+       u8         reserved_at_20[0x18];
+       u8         log_trace_buffer_size[0x8];
+       u8         trace_mkey[0x20];
+       u8         reserved_at_60[0x3a0];
+ };
+ 
+ struct mlx5_ifc_mtrc_stdb_bits {
+       u8         string_db_index[0x4];
+       u8         reserved_at_4[0x4];
+       u8         read_size[0x18];
+       u8         start_offset[0x20];
+       u8         string_db_data[0];
+ };
+ 
+ struct mlx5_ifc_mtrc_ctrl_bits {
+       u8         trace_status[0x2];
+       u8         reserved_at_2[0x2];
+       u8         arm_event[0x1];
+       u8         reserved_at_5[0xb];
+       u8         modify_field_select[0x10];
+       u8         reserved_at_20[0x2b];
+       u8         current_timestamp52_32[0x15];
+       u8         current_timestamp31_0[0x20];
+       u8         reserved_at_80[0x180];
+ };
+ 
  #endif /* MLX5_IFC_H */