This change reverts
aba3a882a178: "mtd: spi-nor: intel: provide a range
for poll_timout". That change introduces a performance regression when
reading sequentially from flash. Logging calls to intel_spi_read without
this change we get:
Start MTD read
[ 20.045527] intel_spi_read(from=
1800000, len=400000)
[ 20.045527] intel_spi_read(from=
1800000, len=400000)
[ 282.199274] intel_spi_read(from=
1c00000, len=400000)
[ 282.199274] intel_spi_read(from=
1c00000, len=400000)
[ 544.351528] intel_spi_read(from=
2000000, len=400000)
[ 544.351528] intel_spi_read(from=
2000000, len=400000)
End MTD read
With this change:
Start MTD read
[ 21.942922] intel_spi_read(from=
1c00000, len=400000)
[ 21.942922] intel_spi_read(from=
1c00000, len=400000)
[ 23.784058] intel_spi_read(from=
2000000, len=400000)
[ 23.784058] intel_spi_read(from=
2000000, len=400000)
[ 25.625006] intel_spi_read(from=
2400000, len=400000)
[ 25.625006] intel_spi_read(from=
2400000, len=400000)
End MTD read
Signed-off-by: Luis Alberto Herrera <[email protected]>
Tested-by: Alexander Sverdlin <[email protected]>
Acked-by: Mika Westerberg <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Tudor Ambarus <[email protected]>
u32 val;
return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
- !(val & HSFSTS_CTL_SCIP), 40,
+ !(val & HSFSTS_CTL_SCIP), 0,
INTEL_SPI_TIMEOUT * 1000);
}
u32 val;
return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
- !(val & SSFSTS_CTL_SCIP), 40,
+ !(val & SSFSTS_CTL_SCIP), 0,
INTEL_SPI_TIMEOUT * 1000);
}