drm/nouveau: create grctx on the fly on all chipsets

Signed-off-by: Ben Skeggs <[email protected]>

diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index a57a1d2f3a1110fdb5a60401b95b6de5fe0a2208..3960d66d7abab27504cac39ab85e6698a4dcf0ea 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -121,7 +121,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
                      uint32_t vram_handle, uint32_t gart_handle)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
                      uint32_t vram_handle, uint32_t gart_handle)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;

-       struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;

        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
        struct nouveau_channel *chan;
        unsigned long flags;
        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
        struct nouveau_channel *chan;
        unsigned long flags;


@@ -202,15 +201,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
        /* disable the fifo caches */
        pfifo->reassign(dev, false);
 
        /* disable the fifo caches */
        pfifo->reassign(dev, false);
 

-       /* Create a graphics context for new channel */
-       if (dev_priv->card_type < NV_50) {
-               ret = pgraph->create_context(chan);
-               if (ret) {
-                       nouveau_channel_put(&chan);
-                       return ret;
-               }
-       }
-

        /* Construct inital RAMFC for new channel */
        ret = pfifo->create_context(chan);
        if (ret) {
        /* Construct inital RAMFC for new channel */
        ret = pfifo->create_context(chan);
        if (ret) {

diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index d77b1fcd19d4ed1c957914a12300f3079e1a301e..30b6544467ca87032b014b0287497363eb6657b8 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -651,7 +651,8 @@ found:
                }
                break;
        case NVOBJ_ENGINE_GR:
                }
                break;
        case NVOBJ_ENGINE_GR:

-               if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) {
+               if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) ||
+                   (dev_priv->card_type  < NV_20 && !chan->pgraph_ctx)) {

                        struct nouveau_pgraph_engine *pgraph =
                                &dev_priv->engine.graph;
 
                        struct nouveau_pgraph_engine *pgraph =
                                &dev_priv->engine.graph;
 

diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c
index c86e4d4e9b967a864b208009200e394ce79e9f03..49b9a35a9cd6c79857fab54e69590f3e046cac53 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv40_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -64,7 +64,6 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 #endif
                              0x30000000 /* no idea.. */);
                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 #endif
                              0x30000000 /* no idea.. */);

-       nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4);

        nv_wi32(dev, fc + 60, 0x0001FFFF);
 
        /* enable the fifo dma operation */
        nv_wi32(dev, fc + 60, 0x0001FFFF);
 
        /* enable the fifo dma operation */

diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 0618846a97ce4292b9bd21625cca36e3d090a521..19ef92a0375a8220e7f8e4563006057a3d21f8a4 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -62,6 +62,7 @@ nv40_graph_create_context(struct nouveau_channel *chan)
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
        struct nouveau_grctx ctx = {};
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
        struct nouveau_grctx ctx = {};

+       unsigned long flags;

        int ret;
 
        ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
        int ret;
 
        ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,


@@ -76,6 +77,17 @@ nv40_graph_create_context(struct nouveau_channel *chan)
        nv40_grctx_init(&ctx);
 
        nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
        nv40_grctx_init(&ctx);
 
        nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);

+
+       /* init grctx pointer in ramfc, and on PFIFO if channel is
+        * already active there
+        */
+       spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+       nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);
+       nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
+       if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
+               nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);
+       nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
+       spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

        return 0;
 }
 
        return 0;
 }