drm/amdgpu/nbio7.4: use original HDP_FLUSH bits

The extended bits were not available for use on vega20 and
presumably arcturus as well.

Fixes: a0f9f854666834 ("drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12")
Reviewed-and-tested-by: Guchun Chen <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 814e9620fac57da9a76f1c737421e830e12f72ed..208a784475bd5f28a9a171a760cccaab20a95fb8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1125,10 +1125,13 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
                break;
        case IP_VERSION(7, 4, 0):
        case IP_VERSION(7, 4, 1):
-       case IP_VERSION(7, 4, 4):
                adev->nbio.funcs = &nbio_v7_4_funcs;
                adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
                break;
+       case IP_VERSION(7, 4, 4):
+               adev->nbio.funcs = &nbio_v7_4_funcs;
+               adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
+               break;
        case IP_VERSION(7, 2, 0):
        case IP_VERSION(7, 2, 1):
        case IP_VERSION(7, 5, 0):

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 3b7775d74bb2c2b47bec336310e85bd25b90cff7..b8bd03d16dbaf13ec5634a92b60e6babf08b9885 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -325,6 +325,21 @@ static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
 }
 
 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
+       .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
+       .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
+       .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
+       .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
+       .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
+       .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
+       .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
+       .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
+       .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
+       .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
+       .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
+       .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
+};
+
+const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg_ald = {
        .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
        .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
        .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
index b8216581ec8d3fcf6cc6b60ff2fe072e0534204e..cc5692db6f9808c3eeddf1546c367fcaa240afb7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
@@ -27,6 +27,7 @@
 #include "soc15_common.h"
 
 extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg;
+extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg_ald;
 extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
 extern const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs;