RISC-V: replace cbom instructions with an insn-def

Using the cbom instructions directly in ALT_CMO_OP, requires toolchain
support for the instructions. Using an insn-def will allow for removal
of toolchain version checks in the build system & simplification of the
proposed [1] function-based CMO scheme.

Link: https://lore.kernel.org/linux-riscv/[email protected]/
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 4180312d2a70107cd532c1eb2a3bf7ed96f56b37..b71e3ccd3110c5dcf6ad8f740eaaa42f8a4432aa 100644 (file)
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -7,6 +7,7 @@
 
 #include <asm/alternative.h>
 #include <asm/csr.h>
+#include <asm/insn-def.h>
 #include <asm/vendorid_list.h>
 
 #ifdef CONFIG_ERRATA_SIFIVE
@@ -125,7 +126,7 @@ asm volatile(ALTERNATIVE_2(                                         \
        "mv a0, %1\n\t"                                                 \
        "j 2f\n\t"                                                      \
        "3:\n\t"                                                        \
-       "cbo." __stringify(_op) " (a0)\n\t"                             \
+       CBO_##_op(a0)                                                   \
        "add a0, a0, %0\n\t"                                            \
        "2:\n\t"                                                        \
        "bltu a0, %2, 3b\n\t"                                           \

diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
index 39f9e08935647d0003ea193cc9a0e72d16c6de5e..e01ab51f50d27d8f31d36c7ae0e43f601cc57e09 100644 (file)
--- a/arch/riscv/include/asm/insn-def.h
+++ b/arch/riscv/include/asm/insn-def.h
@@ -180,4 +180,16 @@
        INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51),              \
               __RD(0), RS1(gaddr), RS2(vmid))
 
+#define CBO_inval(base)                                                \
+       INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),              \
+              RS1(base), SIMM12(0))
+
+#define CBO_clean(base)                                                \
+       INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),              \
+              RS1(base), SIMM12(1))
+
+#define CBO_flush(base)                                                \
+       INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),              \
+              RS1(base), SIMM12(2))
+
 #endif /* __ASM_INSN_DEF_H */