clk: renesas: r8a779f0: Add Z0 and Z1 clock support

Add support for the Z0 and Z1 (Cortex-A55 Sub-System 0 (CPU 0-3) and
Sub-System 1 (CPU 4-7)) clocks on R-Car S4-8, based on the existing
support for Z clocks on R-Car Gen4.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/43009e25be1223a717e00c392cb2d416f5d47032.1654695893.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index e6f41b9f765a1abd457071bda5a170d5142485c8..ac0383c38aeebc518f9df3f2271c6310c5161b17 100644 (file)
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -77,6 +77,8 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
        DEF_BASE(".rpcsrc",     CLK_RPCSRC,     CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
 
        /* Core Clock Outputs */
+       DEF_GEN4_Z("z0",        R8A779F0_CLK_Z0,        CLK_TYPE_GEN4_Z,        CLK_PLL2,       2, 0),
+       DEF_GEN4_Z("z1",        R8A779F0_CLK_Z1,        CLK_TYPE_GEN4_Z,        CLK_PLL2,       2, 8),
        DEF_FIXED("s0d2",       R8A779F0_CLK_S0D2,      CLK_S0,         2, 1),
        DEF_FIXED("s0d3",       R8A779F0_CLK_S0D3,      CLK_S0,         3, 1),
        DEF_FIXED("s0d4",       R8A779F0_CLK_S0D4,      CLK_S0,         4, 1),