Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra...

From Stephen Warren:
ARM: tegra: SoC-specific core code changes

This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.

* tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC
  ARM: tegra: use section-sized static mappings for LPAE too
  ARM: tegra: don't hard-code DEBUG_LL baud rate
  ARM: tegra: fix DEBUG_LL combined with LPAE
  ARM: tegra: switch FUSE clock on before usage

Signed-off-by: Olof Johansson <[email protected]>

diff --combined arch/arm/mach-tegra/Kconfig
index 15c09294effa30dbb3c2ef662e61788ea140ba96,807e7bcd0ac3f57dcc46bc5f815cc3d7c26886fd..d1a12a496525290c15003c18bdd577fb7647990f
--- 1/arch/arm/mach-tegra/Kconfig
--- 2/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@@ -14,8 -14,6 +14,8 @@@ config ARCH_TEGR
        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
        select PINCTRL
 +      select ARCH_HAS_RESET_CONTROLLER
 +      select RESET_CONTROLLER
        select SOC_BUS
        select SPARSE_IRQ
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
@@@ -65,6 -63,7 +65,7 @@@ config ARCH_TEGRA_124_SO
        bool "Enable support for Tegra124 family"
        select ARM_L1_CACHE_SHIFT_6
        select HAVE_ARM_ARCH_TIMER
+       select PINCTRL_TEGRA124
        help
          Support for NVIDIA Tegra T124 processor family, based on the
          ARM CortexA15MP CPU

diff --combined arch/arm/mach-tegra/fuse.c
index 3a9c1f1c219dd47bd79ecb1c3bb9f1538abe4463,d610a408c0e0c928b38efeaa77a57811621d7118..c9ac23b385bef9b1e736e7d3480d2b05a6da63a4
--- 1/arch/arm/mach-tegra/fuse.c
--- 2/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@@ -22,6 -22,7 +22,7 @@@
  #include <linux/io.h>
  #include <linux/export.h>
  #include <linux/random.h>
+ #include <linux/clk.h>
  #include <linux/tegra-soc.h>
  
  #include "fuse.h"
@@@ -54,6 -55,7 +55,7 @@@ int tegra_cpu_speedo_id;              /* only exis
  int tegra_soc_speedo_id;
  enum tegra_revision tegra_revision;
  
+ static struct clk *fuse_clk;
  static int tegra_fuse_spare_bit;
  static void (*tegra_init_speedo_data)(void);
  
@@@ -77,6 -79,22 +79,22 @@@ static const char *tegra_revision_name[
        [TEGRA_REVISION_A04]     = "A04",
  };
  
+ static void tegra_fuse_enable_clk(void)
+ {
+       if (IS_ERR(fuse_clk))
+               fuse_clk = clk_get_sys(NULL, "fuse");
+       if (IS_ERR(fuse_clk))
+               return;
+       clk_prepare_enable(fuse_clk);
+ }
+ 
+ static void tegra_fuse_disable_clk(void)
+ {
+       if (IS_ERR(fuse_clk))
+               return;
+       clk_disable_unprepare(fuse_clk);
+ }
+ 
  u32 tegra_fuse_readl(unsigned long offset)
  {
        return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
@@@ -84,7 -102,15 +102,15 @@@
  
  bool tegra_spare_fuse(int bit)
  {
-       return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
+       bool ret;
+ 
+       tegra_fuse_enable_clk();
+ 
+       ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
+ 
+       tegra_fuse_disable_clk();
+ 
+       return ret;
  }
  
  static enum tegra_revision tegra_get_revision(u32 id)
@@@ -113,10 -139,14 +139,14 @@@ static void tegra_get_process_id(void
  {
        u32 reg;
  
+       tegra_fuse_enable_clk();
+ 
        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
        tegra_cpu_process_id = (reg >> 6) & 3;
        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
        tegra_core_process_id = (reg >> 12) & 3;
+ 
+       tegra_fuse_disable_clk();
  }
  
  u32 tegra_read_chipid(void)
@@@ -159,6 -189,15 +189,15 @@@ void __init tegra_init_fuse(void
        reg |= 1 << 28;
        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
  
+       /*
+        * Enable FUSE clock. This needs to be hardcoded because the clock
+        * subsystem is not active during early boot.
+        */
+       reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
+       reg |= 1 << 7;
+       writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
+       fuse_clk = ERR_PTR(-EINVAL);
+ 
        reg = tegra_fuse_readl(FUSE_SKU_INFO);
        randomness[0] = reg;
        tegra_sku_id = reg & 0xFF;
@@@ -198,12 -237,10 +237,12 @@@
        switch (tegra_chip_id) {
        case TEGRA20:
                tegra20_fuse_init_randomness();
 +              break;
        case TEGRA30:
        case TEGRA114:
        default:
                tegra30_fuse_init_randomness();
 +              break;
        }
  
        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
@@@ -211,3 -248,13 +250,3 @@@
                tegra_sku_id, tegra_cpu_process_id,
                tegra_core_process_id);
  }
 -
 -unsigned long long tegra_chip_uid(void)
 -{
 -      unsigned long long lo, hi;
 -
 -      lo = tegra_fuse_readl(FUSE_UID_LOW);
 -      hi = tegra_fuse_readl(FUSE_UID_HIGH);
 -      return (hi << 32ull) | lo;
 -}
 -EXPORT_SYMBOL(tegra_chip_uid);