[ARM] xsc3: fix xsc3_l2_inv_range

When 'start' and 'end' are less than a cacheline apart and 'start' is
unaligned we are done after cleaning and invalidating the first
cacheline.  So check for (start < end) which will not walk off into
invalid address ranges when (start > end).

This issue was caught by drivers/dma/dmatest.

2.6.27 is susceptible.

Cc: <[email protected]>
Cc: Haavard Skinnemoen <[email protected]>
Cc: Lothar WaÃ<9f>mann <[email protected]>
Cc: Lennert Buytenhek <[email protected]>
Cc: Eric Miao <[email protected]>
Signed-off-by: Dan Williams <[email protected]>

diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 10b1bae1a258f782f0aaf67e128f8a8aef514672..464de893a988033180ac9bb7e25c1a53daa6f149 100644 (file)
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -98,7 +98,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
        /*
         * Clean and invalidate partial last cache line.
         */
-       if (end & (CACHE_LINE_SIZE - 1)) {
+       if (start < end && (end & (CACHE_LINE_SIZE - 1))) {
                xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1));
                xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
                end &= ~(CACHE_LINE_SIZE - 1);
@@ -107,7 +107,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
        /*
         * Invalidate all full cache lines between 'start' and 'end'.
         */
-       while (start != end) {
+       while (start < end) {
                xsc3_l2_inv_pa(start);
                start += CACHE_LINE_SIZE;
        }