Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "ARM64 DT updates are fairly small this time, only two new SoCs and a
  handful of new machines get added, all of them similar to other
  hardware we already support.

  New SoC:

   - HiSilicon Kirin960/Hi3660 and HiKey960 development board

   - NXP LS1012a with three reference boards:
        http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-layerscape-arm-processors/qoriq-layerscape-1012a-low-power-communication-processor:LS1012A

  New development board:

   - Banana Pi M64, based on Allwinner A64:
        http://www.banana-pi.org/m64.html

   - SolidRun MACCHIATOBin based on Marvell Armada 8K:
        https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/

   - Broadcom BCM958712DxXMC NorthStar2 reference board (another one)

  A lot of platforms improve support for existing machines by adding
  extra devices for which a binding and driver is availabe:

  Allwinner:
   - MMC, USB

  ARM Juno:
   - Coresight, STM

  Broadcom:
   - NS2 GICv2m irqchip and PCIe

  Marvell:
   - Armada 3700 SPI, I2C, ethernet switch

  Mediatek:
   - MT8173 thermal

  NXP i.MX:
   - LS1046A thermal

  Qualcomm:
   - coresight on MSM8916, HDMI, WCNSS, SCM

  Renesas:
   - r8a779[56] thermal, powerdomain, ethernet, sound, pwm, can, can fd

  Rockchip:
   - thermal, eDP, pinctrl enhancements

  Samsung:
   - TM2 touchkey, Exynos5433 HDMI and power management improvements

  UniPhier:
   - SD reset, eMMC controller

  ZTE:
   - oppv2 cpufreq"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (110 commits)
  arm64: dts: qcom: Add msm8916 CoreSight components
  arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon
  arm64: allwinner: add BananaPi-M64 support
  arm64: allwinner: a64: add UART1 pin nodes
  arm64: allwinner: pine64: add MMC support
  arm64: allwinner: a64: Increase the MMC max frequency
  arm64: allwinner: a64: Add MMC pinctrl nodes
  arm64: allwinner: a64: Add MMC nodes
  dt-bindings: clockgen: Add compatible string for LS1012A
  Documentation: DT: add LS1012A compatible for SCFG and DCFG
  Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boards
  arm64: dts: marvell: add generic-ahci compatibles for CP110 ahci
  arm64: tegra: Use symbolic reset identifiers
  arm64: dts: r8a7796: Mark EthernetAVB device node disabled
  arm64: dts: r8a7795: Mark EthernetAVB device node disabled
  arm64: dts: r8a7795: tidyup audma definition order
  arm64: dts: r8a7796: Link ARM GIC to clock and clock domain
  arm64: dts: r8a7795: Link ARM GIC to clock and clock domain
  arm64: dts: r8a7796: Add R-Car Gen3 thermal support
  arm64: dts: r8a7795: Add R-Car Gen3 thermal support
  ...

diff --combined Documentation/devicetree/bindings/arm/cpus.txt
index 3c2fd72d0bf97f5e28025f22131b6fac0343c6d6,d748774444d29e33b5de5ae1c70f717377930e05..698ad1f097fa34c835478a84a7ad9bddfc86e9b6
--- 1/Documentation/devicetree/bindings/arm/cpus.txt
--- 2/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@@ -158,6 -158,7 +158,7 @@@ nodes to be present and contain the pro
                            "arm,cortex-a53"
                            "arm,cortex-a57"
                            "arm,cortex-a72"
+                           "arm,cortex-a73"
                            "arm,cortex-m0"
                            "arm,cortex-m0+"
                            "arm,cortex-m1"
@@@ -202,7 -203,6 +203,7 @@@
                            "marvell,armada-380-smp"
                            "marvell,armada-390-smp"
                            "marvell,armada-xp-smp"
 +                          "marvell,98dx3236-smp"
                            "mediatek,mt6589-smp"
                            "mediatek,mt81xx-tz-smp"
                            "qcom,gcc-msm8660"

diff --combined arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 135890cd8a859708c9adf6d3e184bd7ec093a3e0,7b02fd6e33e19d30a0ff97a649f6b810f3a7155e..16072c1c3ed3eaece9b91049d33a1ffd0ff7156b
--- 1/arch/arm64/boot/dts/exynos/exynos5433.dtsi
--- 2/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@@ -299,7 -299,7 +299,7 @@@
                        #clock-cells = <1>;
                };
  
-               cmu_peris: clock-controller@0x10040000 {
+               cmu_peris: clock-controller@10040000 {
                        compatible = "samsung,exynos5433-cmu-peris";
                        reg = <0x10040000 0x1000>;
                        #clock-cells = <1>;
@@@ -599,6 -599,30 +599,30 @@@
                        clock-names = "fin_pll", "mct";
                };
  
+               ppmu_d0_cpu: ppmu@10480000 {
+                       compatible = "samsung,exynos-ppmu-v2";
+                       reg = <0x10480000 0x2000>;
+                       status = "disabled";
+               };
+ 
+               ppmu_d0_general: ppmu@10490000 {
+                       compatible = "samsung,exynos-ppmu-v2";
+                       reg = <0x10490000 0x2000>;
+                       status = "disabled";
+               };
+ 
+               ppmu_d1_cpu: ppmu@104b0000 {
+                       compatible = "samsung,exynos-ppmu-v2";
+                       reg = <0x104b0000 0x2000>;
+                       status = "disabled";
+               };
+ 
+               ppmu_d1_general: ppmu@104c0000 {
+                       compatible = "samsung,exynos-ppmu-v2";
+                       reg = <0x104c0000 0x2000>;
+                       status = "disabled";
+               };
+ 
                pinctrl_alive: pinctrl@10580000 {
                        compatible = "samsung,exynos5433-pinctrl";
                        reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
@@@ -682,7 -706,7 +706,7 @@@
                        interrupts = <GIC_PPI 9 0xf04>;
                };
  
-               mipi_phy: video-phy@105c0710 {
+               mipi_phy: video-phy {
                        compatible = "samsung,exynos5433-mipi-video-phy";
                        #phy-cells = <1>;
                        samsung,pmu-syscon = <&pmu_system_controller>;
@@@ -727,6 -751,29 +751,29 @@@
                        };
                };
  
+               decon_tv: decon@13880000 {
+                       compatible = "samsung,exynos5433-decon-tv";
+                       reg = <0x13880000 0x20b8>;
+                       clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
+                                <&cmu_disp CLK_ACLK_DECON_TV>,
+                                <&cmu_disp CLK_ACLK_SMMU_TV0X>,
+                                <&cmu_disp CLK_ACLK_XIU_TV0X>,
+                                <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+                                <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
+                                <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
+                       clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
+                                     "aclk_xiu_decon0x", "pclk_smmu_decon0x",
+                                     "sclk_decon_vclk", "sclk_decon_eclk";
+                       samsung,disp-sysreg = <&syscon_disp>;
+                       interrupt-names = "fifo", "vsync", "lcd_sys";
+                       interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
+                       iommu-names = "m0", "m1";
+               };
+ 
                dsi: dsi@13900000 {
                        compatible = "samsung,exynos5433-mipi-dsi";
                        reg = <0x13900000 0xC0>;
@@@ -790,6 -837,35 +837,35 @@@
                        };
                };
  
+               hdmi: hdmi@13970000 {
+                       compatible = "samsung,exynos5433-hdmi";
+                       reg = <0x13970000 0x70000>;
+                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cmu_disp CLK_PCLK_HDMI>,
+                               <&cmu_disp CLK_PCLK_HDMIPHY>,
+                               <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
+                               <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
+                               <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
+                               <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
+                               <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
+                               <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
+                               <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
+                       clock-names = "hdmi_pclk", "hdmi_i_pclk",
+                               "i_tmds_clk", "i_pixel_clk",
+                               "tmds_clko", "tmds_clko_user",
+                               "pixel_clko", "pixel_clko_user",
+                               "oscclk", "i_spdif_clk";
+                       phy = <&hdmiphy>;
+                       ddc = <&hsi2c_11>;
+                       samsung,syscon-phandle = <&pmu_system_controller>;
+                       samsung,sysreg-phandle = <&syscon_disp>;
+                       status = "disabled";
+               };
+ 
+               hdmiphy: hdmiphy@13af0000 {
+                       reg = <0x13af0000 0x80>;
+               };
+ 
                syscon_disp: syscon@13b80000 {
                        compatible = "syscon";
                        reg = <0x13b80000 0x1010>;
@@@ -868,7 -944,7 +944,7 @@@
                        iommu-names = "left", "right";
                };
  
-               sysmmu_decon0x: sysmmu@0x13a00000 {
+               sysmmu_decon0x: sysmmu@13a00000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a00000 0x1000>;
                        interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
@@@ -878,7 -954,7 +954,7 @@@
                        #iommu-cells = <0>;
                };
  
-               sysmmu_decon1x: sysmmu@0x13a10000 {
+               sysmmu_decon1x: sysmmu@13a10000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a10000 0x1000>;
                        interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
@@@ -888,7 -964,27 +964,27 @@@
                        #iommu-cells = <0>;
                };
  
-               sysmmu_gscl0: sysmmu@0x13C80000 {
+               sysmmu_tv0x: sysmmu@13a20000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x13a20000 0x1000>;
+                       interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+                               <&cmu_disp CLK_ACLK_SMMU_TV0X>;
+                       #iommu-cells = <0>;
+               };
+ 
+               sysmmu_tv1x: sysmmu@13a30000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x13a30000 0x1000>;
+                       interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
+                               <&cmu_disp CLK_ACLK_SMMU_TV1X>;
+                       #iommu-cells = <0>;
+               };
+ 
+               sysmmu_gscl0: sysmmu@13c80000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13C80000 0x1000>;
                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
@@@ -898,7 -994,7 +994,7 @@@
                        #iommu-cells = <0>;
                };
  
-               sysmmu_gscl1: sysmmu@0x13C90000 {
+               sysmmu_gscl1: sysmmu@13c90000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13C90000 0x1000>;
                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
@@@ -908,7 -1004,7 +1004,7 @@@
                        #iommu-cells = <0>;
                };
  
-               sysmmu_gscl2: sysmmu@0x13CA0000 {
+               sysmmu_gscl2: sysmmu@13ca0000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13CA0000 0x1000>;
                        interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
@@@ -918,7 -1014,7 +1014,7 @@@
                        #iommu-cells = <0>;
                };
  
-               sysmmu_jpeg: sysmmu@0x15060000 {
+               sysmmu_jpeg: sysmmu@15060000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15060000 0x1000>;
                        interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
@@@ -928,7 -1024,7 +1024,7 @@@
                        #iommu-cells = <0>;
                };
  
-               sysmmu_mfc_0: sysmmu@0x15200000 {
+               sysmmu_mfc_0: sysmmu@15200000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15200000 0x1000>;
                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@@ -938,7 -1034,7 +1034,7 @@@
                        #iommu-cells = <0>;
                };
  
-               sysmmu_mfc_1: sysmmu@0x15210000 {
+               sysmmu_mfc_1: sysmmu@15210000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15210000 0x1000>;
                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
@@@ -1261,7 -1357,7 +1357,7 @@@
                        status = "disabled";
                };
  
-               usbdrd30: usb@15400000  {
+               usbdrd30: usbdrd {
                        compatible = "samsung,exynos5250-dwusb3";
                        clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
                                <&cmu_fsys CLK_SCLK_USBDRD30>;
@@@ -1308,7 -1404,7 +1404,7 @@@
                        status = "disabled";
                };
  
-               usbhost30: usb@15a00000 {
+               usbhost30: usbhost {
                        compatible = "samsung,exynos5250-dwusb3";
                        clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
                                <&cmu_fsys CLK_SCLK_USBHOST30>;
@@@ -1367,7 -1463,7 +1463,7 @@@
                };
  
                amba {
 -                      compatible = "arm,amba-bus";
 +                      compatible = "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
@@@ -1398,6 -1494,8 +1494,8 @@@
                audio-subsystem@11400000 {
                        compatible = "samsung,exynos5433-lpass";
                        reg = <0x11400000 0x100>, <0x11500000 0x08>;
+                       clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+                       clock-names = "sfr0_ctrl";
                        samsung,pmu-syscon = <&pmu_system_controller>;
                        #address-cells = <1>;
                        #size-cells = <1>;
@@@ -1458,5 -1556,6 +1556,6 @@@
        };
  };
  
+ #include "exynos5433-bus.dtsi"
  #include "exynos5433-pinctrl.dtsi"
  #include "exynos5433-tmu.dtsi"

diff --combined arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 40a02b29213e58a3049b4807161527a9d82f2366,d80ddb4a4a059d9643626acf734bb077c3257ab3..6922252f317bca508d1c8797dfc06941f5543859
--- 1/arch/arm64/boot/dts/mediatek/mt8173.dtsi
--- 2/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@@ -182,12 -182,12 +182,12 @@@
                                map@0 {
                                        trip = <&target>;
                                        cooling-device = <&cpu0 0 0>;
-                                       contribution = <1024>;
+                                       contribution = <3072>;
                                };
                                map@1 {
                                        trip = <&target>;
                                        cooling-device = <&cpu2 0 0>;
-                                       contribution = <2048>;
+                                       contribution = <1024>;
                                };
                        };
                };
@@@ -401,6 -401,11 +401,11 @@@
                efuse: efuse@10206000 {
                        compatible = "mediatek,mt8173-efuse";
                        reg = <0 0x10206000 0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       thermal_calibration: calib@528 {
+                               reg = <0x528 0xc>;
+                       };
                };
  
                apmixedsys: clock-controller@10209000 {
@@@ -574,6 -579,8 +579,8 @@@
                        resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
                        mediatek,auxadc = <&auxadc>;
                        mediatek,apmixedsys = <&apmixedsys>;
+                       nvmem-cells = <&thermal_calibration>;
+                       nvmem-cell-names = "calibration-data";
                };
  
                nor_flash: spi@1100d000 {
@@@ -728,11 -735,9 +735,11 @@@
                               <&phy_port1 PHY_TYPE_USB2>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
                        clocks = <&topckgen CLK_TOP_USB30_SEL>,
 +                               <&clk26m>,
                                 <&pericfg CLK_PERI_USB0>,
                                 <&pericfg CLK_PERI_USB1>;
                        clock-names = "sys_ck",
 +                                    "ref_ck",
                                      "wakeup_deb_p0",
                                      "wakeup_deb_p1";
                        mediatek,syscon-wakeup = <&pericfg>;
@@@ -747,8 -752,8 +754,8 @@@
                                reg-names = "mac";
                                interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
                                power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 -                              clocks = <&topckgen CLK_TOP_USB30_SEL>;
 -                              clock-names = "sys_ck";
 +                              clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 +                              clock-names = "sys_ck", "ref_ck";
                                status = "disabled";
                        };
                };
@@@ -780,6 -785,8 +787,8 @@@
                        compatible = "mediatek,mt8173-mmsys", "syscon";
                        reg = <0 0x14000000 0 0x1000>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+                       assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
+                       assigned-clock-rates = <400000000>;
                        #clock-cells = <1>;
                };