]> Git Repo - linux.git/commitdiff
Merge branch 'gpio-irqchip-rework' of /home/linus/linux-gpio into devel
authorLinus Walleij <[email protected]>
Thu, 9 Nov 2017 08:38:42 +0000 (09:38 +0100)
committerLinus Walleij <[email protected]>
Thu, 9 Nov 2017 08:38:42 +0000 (09:38 +0100)
15 files changed:
1  2 
MAINTAINERS
drivers/gpio/Kconfig
drivers/gpio/gpio-aspeed.c
drivers/gpio/gpio-rcar.c
drivers/gpio/gpiolib.c
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
drivers/pinctrl/intel/pinctrl-cherryview.c
drivers/pinctrl/intel/pinctrl-intel.c
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
drivers/pinctrl/pinctrl-amd.c
drivers/pinctrl/pinctrl-mcp23s08.c
drivers/pinctrl/pinctrl-sx150x.c
drivers/pinctrl/sirf/pinctrl-atlas7.c
drivers/pinctrl/sirf/pinctrl-sirf.c
drivers/pinctrl/spear/pinctrl-plgpio.c

diff --combined MAINTAINERS
index 2fcf18a768c9568caf17d941058d20ca6a70bdd1,213adea9d9ff3ff184a9f40752c0bf19e15049b7..1dea409da8800588d23e60c137de0f6851e1a9e5
@@@ -2017,6 -2017,7 +2017,7 @@@ M:      Masahiro Yamada <yamada.masahiro@soc
  L:    [email protected] (moderated for non-subscribers)
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
  S:    Maintained
+ F:    Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
  F:    arch/arm/boot/dts/uniphier*
  F:    arch/arm/include/asm/hardware/cache-uniphier.h
  F:    arch/arm/mach-uniphier/
@@@ -2024,6 -2025,7 +2025,7 @@@ F:      arch/arm/mm/cache-uniphier.
  F:    arch/arm64/boot/dts/socionext/
  F:    drivers/bus/uniphier-system-bus.c
  F:    drivers/clk/uniphier/
+ F:    drivers/gpio/gpio-uniphier.c
  F:    drivers/i2c/busses/i2c-uniphier*
  F:    drivers/irqchip/irq-uniphier-aidet.c
  F:    drivers/pinctrl/uniphier/
@@@ -10627,7 -10629,6 +10629,7 @@@ PIN CONTROLLER - RENESA
  M:    Laurent Pinchart <[email protected]>
  M:    Geert Uytterhoeven <[email protected]>
  L:    [email protected]
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
  S:    Maintained
  F:    drivers/pinctrl/sh-pfc/
  
@@@ -12884,6 -12885,13 +12886,13 @@@ F: arch/arc/plat-axs10
  F:    arch/arc/boot/dts/ax*
  F:    Documentation/devicetree/bindings/arc/axs10*
  
+ SYNOPSYS DESIGNWARE APB GPIO DRIVER
+ M:    Hoan Tran <[email protected]>
+ L:    [email protected]
+ S:    Maintained
+ F:    drivers/gpio/gpio-dwapb.c
+ F:    Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
  SYNOPSYS DESIGNWARE DMAC DRIVER
  M:    Viresh Kumar <[email protected]>
  M:    Andy Shevchenko <[email protected]>
diff --combined drivers/gpio/Kconfig
index e3f93d2d645bfcfb0eb8705339a196b6251d8257,4ed6a79677840ea85e57b769128004c2060ce6d7..03e34d9ca77804d12b476e815a0e89e7166e87ca
@@@ -139,7 -139,7 +139,7 @@@ config GPIO_BRCMST
        default y if (ARCH_BRCMSTB || BMIPS_GENERIC)
        depends on OF_GPIO && (ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST)
        select GPIO_GENERIC
-       select GPIOLIB_IRQCHIP
+       select IRQ_DOMAIN
        help
          Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
  
@@@ -286,8 -286,7 +286,7 @@@ config GPIO_LYNXPOIN
          Requires ACPI device enumeration code to set up a platform device.
  
  config GPIO_MB86S7X
-       bool "GPIO support for Fujitsu MB86S7x Platforms"
-       depends on ARCH_MB86S7X || COMPILE_TEST
+       tristate "GPIO support for Fujitsu MB86S7x Platforms"
        help
          Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs.
  
@@@ -442,6 -441,15 +441,15 @@@ config GPIO_TEGR
        help
          Say yes here to support GPIO pins on NVIDIA Tegra SoCs.
  
+ config GPIO_TEGRA186
+       tristate "NVIDIA Tegra186 GPIO support"
+       default ARCH_TEGRA_186_SOC
+       depends on ARCH_TEGRA_186_SOC || COMPILE_TEST
+       depends on OF_GPIO
+       select GPIOLIB_IRQCHIP
+       help
+         Say yes here to support GPIO pins on NVIDIA Tegra186 SoCs.
  config GPIO_TS4800
        tristate "TS-4800 DIO blocks and compatibles"
        depends on OF_GPIO
@@@ -474,6 -482,14 +482,14 @@@ config GPIO_TZ1090_PD
        help
          Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs.
  
+ config GPIO_UNIPHIER
+       tristate "UniPhier GPIO support"
+       depends on ARCH_UNIPHIER || COMPILE_TEST
+       depends on OF_GPIO
+       select IRQ_DOMAIN_HIERARCHY
+       help
+         Say yes here to support UniPhier GPIOs.
  config GPIO_VF610
        def_bool y
        depends on ARCH_MXC && SOC_VF610
@@@ -817,6 -833,15 +833,6 @@@ config GPIO_PCF857
          This driver provides an in-kernel interface to those GPIOs using
          platform-neutral GPIO calls.
  
 -config GPIO_SX150X
 -      bool "Semtech SX150x I2C GPIO expander (deprecated)"
 -      depends on PINCTRL && I2C=y
 -      select PINCTRL_SX150X
 -      default n
 -      help
 -        Say yes here to provide support for Semtech SX150x-series I2C
 -        GPIO expanders. The GPIO driver was replaced by a Pinctrl version.
 -
  config GPIO_TPIC2810
        tristate "TPIC2810 8-Bit I2C GPO expander"
        help
@@@ -1246,6 -1271,16 +1262,16 @@@ config GPIO_74X16
          shift registers. This driver can be used to provide access
          to more gpio outputs.
  
+ config GPIO_MAX3191X
+       tristate "Maxim MAX3191x industrial serializer"
+       select CRC8
+       help
+         GPIO driver for Maxim MAX31910, MAX31911, MAX31912, MAX31913,
+         MAX31953 and MAX31963 industrial serializer, a daisy-chainable
+         chip to make 8 digital 24V inputs available via SPI.  Supports
+         CRC checksums to guard against electromagnetic interference,
+         as well as undervoltage and overtemperature detection.
  config GPIO_MAX7301
        tristate "Maxim MAX7301 GPIO expander"
        select GPIO_MAX730X
index c269cc199707ac2fa1e6ff1311da5a25cb8e34ac,8781817d900366f99c29418c0f2631568d2f3fe6..6b3ca6601af2dd8b1a38fa688e913726873fe82d
@@@ -411,13 -411,16 +411,16 @@@ static int aspeed_gpio_set_type(struct 
        switch (type & IRQ_TYPE_SENSE_MASK) {
        case IRQ_TYPE_EDGE_BOTH:
                type2 |= bit;
+               /* fall through */
        case IRQ_TYPE_EDGE_RISING:
                type0 |= bit;
+               /* fall through */
        case IRQ_TYPE_EDGE_FALLING:
                handler = handle_edge_irq;
                break;
        case IRQ_TYPE_LEVEL_HIGH:
                type0 |= bit;
+               /* fall through */
        case IRQ_TYPE_LEVEL_LOW:
                type1 |= bit;
                handler = handle_level_irq;
@@@ -466,7 -469,7 +469,7 @@@ static void aspeed_gpio_irq_handler(str
                reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS));
  
                for_each_set_bit(p, &reg, 32) {
-                       girq = irq_find_mapping(gc->irqdomain, i * 32 + p);
+                       girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
                        generic_handle_irq(girq);
                }
  
@@@ -498,7 -501,7 +501,7 @@@ static void set_irq_valid_mask(struct a
                        if (i >= gpio->config->nr_gpios)
                                break;
  
-                       clear_bit(i, gpio->chip.irq_valid_mask);
+                       clear_bit(i, gpio->chip.irq.valid_mask);
                }
  
                props++;
@@@ -536,12 -539,12 +539,12 @@@ static int aspeed_gpio_request(struct g
        if (!have_gpio(gpiochip_get_data(chip), offset))
                return -ENODEV;
  
 -      return pinctrl_request_gpio(chip->base + offset);
 +      return pinctrl_gpio_request(chip->base + offset);
  }
  
  static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
  {
 -      pinctrl_free_gpio(chip->base + offset);
 +      pinctrl_gpio_free(chip->base + offset);
  }
  
  static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio,
@@@ -853,7 -856,7 +856,7 @@@ static int __init aspeed_gpio_probe(str
        gpio->chip.set_config = aspeed_gpio_set_config;
        gpio->chip.label = dev_name(&pdev->dev);
        gpio->chip.base = -1;
-       gpio->chip.irq_need_valid_mask = true;
+       gpio->chip.irq.need_valid_mask = true;
  
        rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
        if (rc < 0)
diff --combined drivers/gpio/gpio-rcar.c
index 43b51045aa47a0c2a57c2faaec63e1dcb0b24cca,0ea998a3e357bf74a9e33ea54b5ba4e6759ebd09..e76de57dd617d7e2c918c057dcc0ced6636be7b2
@@@ -24,6 -24,7 +24,7 @@@
  #include <linux/irq.h>
  #include <linux/module.h>
  #include <linux/of.h>
+ #include <linux/of_device.h>
  #include <linux/pinctrl/consumer.h>
  #include <linux/platform_device.h>
  #include <linux/pm_runtime.h>
@@@ -206,7 -207,7 +207,7 @@@ static irqreturn_t gpio_rcar_irq_handle
                          gpio_rcar_read(p, INTMSK))) {
                offset = __ffs(pending);
                gpio_rcar_write(p, INTCLR, BIT(offset));
-               generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
+               generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
                                                    offset));
                irqs_handled++;
        }
@@@ -249,7 -250,7 +250,7 @@@ static int gpio_rcar_request(struct gpi
        if (error < 0)
                return error;
  
 -      error = pinctrl_request_gpio(chip->base + offset);
 +      error = pinctrl_gpio_request(chip->base + offset);
        if (error)
                pm_runtime_put(&p->pdev->dev);
  
@@@ -260,7 -261,7 +261,7 @@@ static void gpio_rcar_free(struct gpio_
  {
        struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  
 -      pinctrl_free_gpio(chip->base + offset);
 +      pinctrl_gpio_free(chip->base + offset);
  
        /*
         * Set the GPIO as an input to ensure that the next GPIO request won't
@@@ -393,16 -394,11 +394,11 @@@ MODULE_DEVICE_TABLE(of, gpio_rcar_of_ta
  static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
  {
        struct device_node *np = p->pdev->dev.of_node;
-       const struct of_device_id *match;
        const struct gpio_rcar_info *info;
        struct of_phandle_args args;
        int ret;
  
-       match = of_match_node(gpio_rcar_of_table, np);
-       if (!match)
-               return -EINVAL;
-       info = match->data;
+       info = of_device_get_match_data(&p->pdev->dev);
  
        ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
        *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
@@@ -456,19 -452,17 +452,17 @@@ static int gpio_rcar_probe(struct platf
  
        pm_runtime_enable(dev);
  
-       io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-       if (!io || !irq) {
-               dev_err(dev, "missing IRQ or IOMEM\n");
+       if (!irq) {
+               dev_err(dev, "missing IRQ\n");
                ret = -EINVAL;
                goto err0;
        }
  
-       p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
-       if (!p->base) {
-               dev_err(dev, "failed to remap I/O memory\n");
-               ret = -ENXIO;
+       io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       p->base = devm_ioremap_resource(dev, io);
+       if (IS_ERR(p->base)) {
+               ret = PTR_ERR(p->base);
                goto err0;
        }
  
diff --combined drivers/gpio/gpiolib.c
index a9cb825ef335f84648fd2bec6dab8d39a67d2390,86dcd02cf602f91d85eb8af0342d07902c46878f..7397260141b477ce679e9b33a5015ead07de0702
@@@ -72,6 -72,8 +72,8 @@@ static LIST_HEAD(gpio_lookup_list)
  LIST_HEAD(gpio_devices);
  
  static void gpiochip_free_hogs(struct gpio_chip *chip);
+ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip,
+                               struct lock_class_key *key);
  static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip);
  static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip);
  static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip);
@@@ -365,28 -367,28 +367,28 @@@ static long linehandle_ioctl(struct fil
        struct linehandle_state *lh = filep->private_data;
        void __user *ip = (void __user *)arg;
        struct gpiohandle_data ghd;
+       int vals[GPIOHANDLES_MAX];
        int i;
  
        if (cmd == GPIOHANDLE_GET_LINE_VALUES_IOCTL) {
-               int val;
+               /* TODO: check if descriptors are really input */
+               int ret = gpiod_get_array_value_complex(false,
+                                                       true,
+                                                       lh->numdescs,
+                                                       lh->descs,
+                                                       vals);
+               if (ret)
+                       return ret;
  
                memset(&ghd, 0, sizeof(ghd));
-               /* TODO: check if descriptors are really input */
-               for (i = 0; i < lh->numdescs; i++) {
-                       val = gpiod_get_value_cansleep(lh->descs[i]);
-                       if (val < 0)
-                               return val;
-                       ghd.values[i] = val;
-               }
+               for (i = 0; i < lh->numdescs; i++)
+                       ghd.values[i] = vals[i];
  
                if (copy_to_user(ip, &ghd, sizeof(ghd)))
                        return -EFAULT;
  
                return 0;
        } else if (cmd == GPIOHANDLE_SET_LINE_VALUES_IOCTL) {
-               int vals[GPIOHANDLES_MAX];
                /* TODO: check if descriptors are really output */
                if (copy_from_user(&ghd, ip, sizeof(ghd)))
                        return -EFAULT;
@@@ -444,12 -446,25 +446,25 @@@ static int linehandle_create(struct gpi
        struct linehandle_state *lh;
        struct file *file;
        int fd, i, ret;
+       u32 lflags;
  
        if (copy_from_user(&handlereq, ip, sizeof(handlereq)))
                return -EFAULT;
        if ((handlereq.lines == 0) || (handlereq.lines > GPIOHANDLES_MAX))
                return -EINVAL;
  
+       lflags = handlereq.flags;
+       /* Return an error if an unknown flag is set */
+       if (lflags & ~GPIOHANDLE_REQUEST_VALID_FLAGS)
+               return -EINVAL;
+       /* OPEN_DRAIN and OPEN_SOURCE flags only make sense for output mode. */
+       if (!(lflags & GPIOHANDLE_REQUEST_OUTPUT) &&
+           ((lflags & GPIOHANDLE_REQUEST_OPEN_DRAIN) ||
+            (lflags & GPIOHANDLE_REQUEST_OPEN_SOURCE)))
+               return -EINVAL;
        lh = kzalloc(sizeof(*lh), GFP_KERNEL);
        if (!lh)
                return -ENOMEM;
        /* Request each GPIO */
        for (i = 0; i < handlereq.lines; i++) {
                u32 offset = handlereq.lineoffsets[i];
-               u32 lflags = handlereq.flags;
                struct gpio_desc *desc;
  
                if (offset >= gdev->ngpio) {
                        goto out_free_descs;
                }
  
-               /* Return an error if a unknown flag is set */
-               if (lflags & ~GPIOHANDLE_REQUEST_VALID_FLAGS) {
-                       ret = -EINVAL;
-                       goto out_free_descs;
-               }
                desc = &gdev->descs[offset];
                ret = gpiod_request(desc, lh->label);
                if (ret)
@@@ -1091,30 -1099,8 +1099,8 @@@ static void gpiochip_setup_devs(void
        }
  }
  
- /**
-  * gpiochip_add_data() - register a gpio_chip
-  * @chip: the chip to register, with chip->base initialized
-  * @data: driver-private data associated with this chip
-  *
-  * Context: potentially before irqs will work
-  *
-  * When gpiochip_add_data() is called very early during boot, so that GPIOs
-  * can be freely used, the chip->parent device must be registered before
-  * the gpio framework's arch_initcall().  Otherwise sysfs initialization
-  * for GPIOs will fail rudely.
-  *
-  * gpiochip_add_data() must only be called after gpiolib initialization,
-  * ie after core_initcall().
-  *
-  * If chip->base is negative, this requests dynamic assignment of
-  * a range of valid GPIOs.
-  *
-  * Returns:
-  * A negative errno if the chip can't be registered, such as because the
-  * chip->base is invalid or already associated with a different chip.
-  * Otherwise it returns zero as a success code.
-  */
- int gpiochip_add_data(struct gpio_chip *chip, void *data)
+ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
+                              struct lock_class_key *key)
  {
        unsigned long   flags;
        int             status = 0;
        if (status)
                goto err_remove_from_list;
  
+       status = gpiochip_add_irqchip(chip, key);
+       if (status)
+               goto err_remove_chip;
        status = of_gpiochip_add(chip);
        if (status)
                goto err_remove_chip;
@@@ -1303,7 -1293,7 +1293,7 @@@ err_free_gdev
        kfree(gdev);
        return status;
  }
- EXPORT_SYMBOL_GPL(gpiochip_add_data);
+ EXPORT_SYMBOL_GPL(gpiochip_add_data_with_key);
  
  /**
   * gpiochip_get_data() - get per-subdriver data for the chip
@@@ -1498,33 -1488,33 +1488,33 @@@ static struct gpio_chip *find_chip_by_n
  
  static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
  {
-       if (!gpiochip->irq_need_valid_mask)
+       if (!gpiochip->irq.need_valid_mask)
                return 0;
  
-       gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
+       gpiochip->irq.valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
                                           sizeof(long), GFP_KERNEL);
-       if (!gpiochip->irq_valid_mask)
+       if (!gpiochip->irq.valid_mask)
                return -ENOMEM;
  
        /* Assume by default all GPIOs are valid */
-       bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
+       bitmap_fill(gpiochip->irq.valid_mask, gpiochip->ngpio);
  
        return 0;
  }
  
  static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
  {
-       kfree(gpiochip->irq_valid_mask);
-       gpiochip->irq_valid_mask = NULL;
+       kfree(gpiochip->irq.valid_mask);
+       gpiochip->irq.valid_mask = NULL;
  }
  
  static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
                                       unsigned int offset)
  {
        /* No mask means all valid */
-       if (likely(!gpiochip->irq_valid_mask))
+       if (likely(!gpiochip->irq.valid_mask))
                return true;
-       return test_bit(offset, gpiochip->irq_valid_mask);
+       return test_bit(offset, gpiochip->irq.valid_mask);
  }
  
  /**
@@@ -1544,7 -1534,7 +1534,7 @@@ static void gpiochip_set_cascaded_irqch
  {
        unsigned int offset;
  
-       if (!gpiochip->irqdomain) {
+       if (!gpiochip->irq.domain) {
                chip_err(gpiochip, "called %s before setting up irqchip\n",
                         __func__);
                return;
                irq_set_chained_handler_and_data(parent_irq, parent_handler,
                                                 gpiochip);
  
-               gpiochip->irq_chained_parent = parent_irq;
+               gpiochip->irq.parents = &parent_irq;
+               gpiochip->irq.num_parents = 1;
        }
  
        /* Set the parent IRQ for all affected IRQs */
        for (offset = 0; offset < gpiochip->ngpio; offset++) {
                if (!gpiochip_irqchip_irq_valid(gpiochip, offset))
                        continue;
-               irq_set_parent(irq_find_mapping(gpiochip->irqdomain, offset),
+               irq_set_parent(irq_find_mapping(gpiochip->irq.domain, offset),
                               parent_irq);
        }
  }
@@@ -1591,6 -1582,11 +1582,11 @@@ void gpiochip_set_chained_irqchip(struc
                                  unsigned int parent_irq,
                                  irq_flow_handler_t parent_handler)
  {
+       if (gpiochip->irq.threaded) {
+               chip_err(gpiochip, "tried to chain a threaded gpiochip\n");
+               return;
+       }
        gpiochip_set_cascaded_irqchip(gpiochip, irqchip, parent_irq,
                                      parent_handler);
  }
@@@ -1607,10 -1603,6 +1603,6 @@@ void gpiochip_set_nested_irqchip(struc
                                 struct irq_chip *irqchip,
                                 unsigned int parent_irq)
  {
-       if (!gpiochip->irq_nested) {
-               chip_err(gpiochip, "tried to nest a chained gpiochip\n");
-               return;
-       }
        gpiochip_set_cascaded_irqchip(gpiochip, irqchip, parent_irq,
                                      NULL);
  }
@@@ -1626,10 -1618,11 +1618,11 @@@ EXPORT_SYMBOL_GPL(gpiochip_set_nested_i
   * gpiochip by assigning the gpiochip as chip data, and using the irqchip
   * stored inside the gpiochip.
   */
static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
-                           irq_hw_number_t hwirq)
+ int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
+                    irq_hw_number_t hwirq)
  {
        struct gpio_chip *chip = d->host_data;
+       int err = 0;
  
        if (!gpiochip_irqchip_irq_valid(chip, hwirq))
                return -ENXIO;
         * This lock class tells lockdep that GPIO irqs are in a different
         * category than their parents, so it won't report false recursion.
         */
-       irq_set_lockdep_class(irq, chip->lock_key);
-       irq_set_chip_and_handler(irq, chip->irqchip, chip->irq_handler);
+       irq_set_lockdep_class(irq, chip->irq.lock_key);
+       irq_set_chip_and_handler(irq, chip->irq.chip, chip->irq.handler);
        /* Chips that use nested thread handlers have them marked */
-       if (chip->irq_nested)
+       if (chip->irq.threaded)
                irq_set_nested_thread(irq, 1);
        irq_set_noprobe(irq);
  
+       if (chip->irq.num_parents == 1)
+               err = irq_set_parent(irq, chip->irq.parents[0]);
+       else if (chip->irq.map)
+               err = irq_set_parent(irq, chip->irq.map[hwirq]);
+       if (err < 0)
+               return err;
        /*
         * No set-up of the hardware will happen if IRQ_TYPE_NONE
         * is passed as default type.
         */
-       if (chip->irq_default_type != IRQ_TYPE_NONE)
-               irq_set_irq_type(irq, chip->irq_default_type);
+       if (chip->irq.default_type != IRQ_TYPE_NONE)
+               irq_set_irq_type(irq, chip->irq.default_type);
  
        return 0;
  }
+ EXPORT_SYMBOL_GPL(gpiochip_irq_map);
  
static void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)
+ void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)
  {
        struct gpio_chip *chip = d->host_data;
  
-       if (chip->irq_nested)
+       if (chip->irq.threaded)
                irq_set_nested_thread(irq, 0);
        irq_set_chip_and_handler(irq, NULL, NULL);
        irq_set_chip_data(irq, NULL);
  }
+ EXPORT_SYMBOL_GPL(gpiochip_irq_unmap);
  
  static const struct irq_domain_ops gpiochip_domain_ops = {
        .map    = gpiochip_irq_map,
@@@ -1702,7 -1705,94 +1705,94 @@@ static int gpiochip_to_irq(struct gpio_
  {
        if (!gpiochip_irqchip_irq_valid(chip, offset))
                return -ENXIO;
-       return irq_create_mapping(chip->irqdomain, offset);
+       return irq_create_mapping(chip->irq.domain, offset);
+ }
+ /**
+  * gpiochip_add_irqchip() - adds an IRQ chip to a GPIO chip
+  * @gpiochip: the GPIO chip to add the IRQ chip to
+  * @lock_key: lockdep class
+  */
+ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip,
+                               struct lock_class_key *lock_key)
+ {
+       struct irq_chip *irqchip = gpiochip->irq.chip;
+       const struct irq_domain_ops *ops;
+       struct device_node *np;
+       unsigned int type;
+       unsigned int i;
+       if (!irqchip)
+               return 0;
+       if (gpiochip->irq.parent_handler && gpiochip->can_sleep) {
+               chip_err(gpiochip, "you cannot have chained interrupts on a "
+                        "chip that may sleep\n");
+               return -EINVAL;
+       }
+       np = gpiochip->gpiodev->dev.of_node;
+       type = gpiochip->irq.default_type;
+       /*
+        * Specifying a default trigger is a terrible idea if DT or ACPI is
+        * used to configure the interrupts, as you may end up with
+        * conflicting triggers. Tell the user, and reset to NONE.
+        */
+       if (WARN(np && type != IRQ_TYPE_NONE,
+                "%s: Ignoring %u default trigger\n", np->full_name, type))
+               type = IRQ_TYPE_NONE;
+       if (has_acpi_companion(gpiochip->parent) && type != IRQ_TYPE_NONE) {
+               acpi_handle_warn(ACPI_HANDLE(gpiochip->parent),
+                                "Ignoring %u default trigger\n", type);
+               type = IRQ_TYPE_NONE;
+       }
+       gpiochip->to_irq = gpiochip_to_irq;
+       gpiochip->irq.default_type = type;
+       gpiochip->irq.lock_key = lock_key;
+       if (gpiochip->irq.domain_ops)
+               ops = gpiochip->irq.domain_ops;
+       else
+               ops = &gpiochip_domain_ops;
+       gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio,
+                                                    gpiochip->irq.first,
+                                                    ops, gpiochip);
+       if (!gpiochip->irq.domain)
+               return -EINVAL;
+       /*
+        * It is possible for a driver to override this, but only if the
+        * alternative functions are both implemented.
+        */
+       if (!irqchip->irq_request_resources &&
+           !irqchip->irq_release_resources) {
+               irqchip->irq_request_resources = gpiochip_irq_reqres;
+               irqchip->irq_release_resources = gpiochip_irq_relres;
+       }
+       if (gpiochip->irq.parent_handler) {
+               void *data = gpiochip->irq.parent_handler_data ?: gpiochip;
+               for (i = 0; i < gpiochip->irq.num_parents; i++) {
+                       /*
+                        * The parent IRQ chip is already using the chip_data
+                        * for this IRQ chip, so our callbacks simply use the
+                        * handler_data.
+                        */
+                       irq_set_chained_handler_and_data(gpiochip->irq.parents[i],
+                                                        gpiochip->irq.parent_handler,
+                                                        data);
+               }
+       }
+       acpi_gpiochip_request_interrupts(gpiochip);
+       return 0;
  }
  
  /**
@@@ -1717,26 -1807,34 +1807,34 @@@ static void gpiochip_irqchip_remove(str
  
        acpi_gpiochip_free_interrupts(gpiochip);
  
-       if (gpiochip->irq_chained_parent) {
-               irq_set_chained_handler(gpiochip->irq_chained_parent, NULL);
-               irq_set_handler_data(gpiochip->irq_chained_parent, NULL);
+       if (gpiochip->irq.chip && gpiochip->irq.parent_handler) {
+               struct gpio_irq_chip *irq = &gpiochip->irq;
+               unsigned int i;
+               for (i = 0; i < irq->num_parents; i++)
+                       irq_set_chained_handler_and_data(irq->parents[i],
+                                                        NULL, NULL);
        }
  
        /* Remove all IRQ mappings and delete the domain */
-       if (gpiochip->irqdomain) {
+       if (gpiochip->irq.domain) {
+               unsigned int irq;
                for (offset = 0; offset < gpiochip->ngpio; offset++) {
                        if (!gpiochip_irqchip_irq_valid(gpiochip, offset))
                                continue;
-                       irq_dispose_mapping(
-                               irq_find_mapping(gpiochip->irqdomain, offset));
+                       irq = irq_find_mapping(gpiochip->irq.domain, offset);
+                       irq_dispose_mapping(irq);
                }
-               irq_domain_remove(gpiochip->irqdomain);
+               irq_domain_remove(gpiochip->irq.domain);
        }
  
-       if (gpiochip->irqchip) {
-               gpiochip->irqchip->irq_request_resources = NULL;
-               gpiochip->irqchip->irq_release_resources = NULL;
-               gpiochip->irqchip = NULL;
+       if (gpiochip->irq.chip) {
+               gpiochip->irq.chip->irq_request_resources = NULL;
+               gpiochip->irq.chip->irq_release_resources = NULL;
+               gpiochip->irq.chip = NULL;
        }
  
        gpiochip_irqchip_free_valid_mask(gpiochip);
   * @handler: the irq handler to use (often a predefined irq core function)
   * @type: the default type for IRQs on this irqchip, pass IRQ_TYPE_NONE
   * to have the core avoid setting up any default type in the hardware.
-  * @nested: whether this is a nested irqchip calling handle_nested_irq()
-  * in its IRQ handler
+  * @threaded: whether this irqchip uses a nested thread handler
   * @lock_key: lockdep class
   *
   * This function closely associates a certain irqchip with a certain
@@@ -1774,7 -1871,7 +1871,7 @@@ int gpiochip_irqchip_add_key(struct gpi
                             unsigned int first_irq,
                             irq_flow_handler_t handler,
                             unsigned int type,
-                            bool nested,
+                            bool threaded,
                             struct lock_class_key *lock_key)
  {
        struct device_node *of_node;
                pr_err("missing gpiochip .dev parent pointer\n");
                return -EINVAL;
        }
-       gpiochip->irq_nested = nested;
+       gpiochip->irq.threaded = threaded;
        of_node = gpiochip->parent->of_node;
  #ifdef CONFIG_OF_GPIO
        /*
                type = IRQ_TYPE_NONE;
        }
  
-       gpiochip->irqchip = irqchip;
-       gpiochip->irq_handler = handler;
-       gpiochip->irq_default_type = type;
+       gpiochip->irq.chip = irqchip;
+       gpiochip->irq.handler = handler;
+       gpiochip->irq.default_type = type;
        gpiochip->to_irq = gpiochip_to_irq;
-       gpiochip->lock_key = lock_key;
-       gpiochip->irqdomain = irq_domain_add_simple(of_node,
+       gpiochip->irq.lock_key = lock_key;
+       gpiochip->irq.domain = irq_domain_add_simple(of_node,
                                        gpiochip->ngpio, first_irq,
                                        &gpiochip_domain_ops, gpiochip);
-       if (!gpiochip->irqdomain) {
-               gpiochip->irqchip = NULL;
+       if (!gpiochip->irq.domain) {
+               gpiochip->irq.chip = NULL;
                return -EINVAL;
        }
  
@@@ -1842,6 -1939,12 +1939,12 @@@ EXPORT_SYMBOL_GPL(gpiochip_irqchip_add_
  
  #else /* CONFIG_GPIOLIB_IRQCHIP */
  
+ static inline int gpiochip_add_irqchip(struct gpio_chip *gpiochip,
+                                      struct lock_class_key *key)
+ {
+       return 0;
+ }
  static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {}
  static inline int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
  {
@@@ -1859,7 -1962,7 +1962,7 @@@ static inline void gpiochip_irqchip_fre
   */
  int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset)
  {
 -      return pinctrl_request_gpio(chip->gpiodev->base + offset);
 +      return pinctrl_gpio_request(chip->gpiodev->base + offset);
  }
  EXPORT_SYMBOL_GPL(gpiochip_generic_request);
  
   */
  void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset)
  {
 -      pinctrl_free_gpio(chip->gpiodev->base + offset);
 +      pinctrl_gpio_free(chip->gpiodev->base + offset);
  }
  EXPORT_SYMBOL_GPL(gpiochip_generic_free);
  
@@@ -2013,7 -2116,7 +2116,7 @@@ EXPORT_SYMBOL_GPL(gpiochip_remove_pin_r
   * on each other, and help provide better diagnostics in debugfs.
   * They're called even less than the "set direction" calls.
   */
- static int __gpiod_request(struct gpio_desc *desc, const char *label)
+ static int gpiod_request_commit(struct gpio_desc *desc, const char *label)
  {
        struct gpio_chip        *chip = desc->gdev->chip;
        int                     status;
@@@ -2106,7 -2209,7 +2209,7 @@@ int gpiod_request(struct gpio_desc *des
        gdev = desc->gdev;
  
        if (try_module_get(gdev->owner)) {
-               status = __gpiod_request(desc, label);
+               status = gpiod_request_commit(desc, label);
                if (status < 0)
                        module_put(gdev->owner);
                else
        return status;
  }
  
- static bool __gpiod_free(struct gpio_desc *desc)
+ static bool gpiod_free_commit(struct gpio_desc *desc)
  {
        bool                    ret = false;
        unsigned long           flags;
  
  void gpiod_free(struct gpio_desc *desc)
  {
-       if (desc && desc->gdev && __gpiod_free(desc)) {
+       if (desc && desc->gdev && gpiod_free_commit(desc)) {
                module_put(desc->gdev->owner);
                put_device(&desc->gdev->dev);
        } else {
@@@ -2217,7 -2320,7 +2320,7 @@@ struct gpio_desc *gpiochip_request_own_
                return desc;
        }
  
-       err = __gpiod_request(desc, label);
+       err = gpiod_request_commit(desc, label);
        if (err < 0)
                return ERR_PTR(err);
  
@@@ -2235,7 -2338,7 +2338,7 @@@ EXPORT_SYMBOL_GPL(gpiochip_request_own_
  void gpiochip_free_own_desc(struct gpio_desc *desc)
  {
        if (desc)
-               __gpiod_free(desc);
+               gpiod_free_commit(desc);
  }
  EXPORT_SYMBOL_GPL(gpiochip_free_own_desc);
  
@@@ -2291,44 -2394,12 +2394,12 @@@ static int gpio_set_drive_single_ended(
        return gc->set_config ? gc->set_config(gc, offset, config) : -ENOTSUPP;
  }
  
- static int _gpiod_direction_output_raw(struct gpio_desc *desc, int value)
+ static int gpiod_direction_output_raw_commit(struct gpio_desc *desc, int value)
  {
        struct gpio_chip *gc = desc->gdev->chip;
        int val = !!value;
        int ret;
  
-       /* GPIOs used for IRQs shall not be set as output */
-       if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
-               gpiod_err(desc,
-                         "%s: tried to set a GPIO tied to an IRQ as output\n",
-                         __func__);
-               return -EIO;
-       }
-       if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
-               /* First see if we can enable open drain in hardware */
-               ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
-                                                 PIN_CONFIG_DRIVE_OPEN_DRAIN);
-               if (!ret)
-                       goto set_output_value;
-               /* Emulate open drain by not actively driving the line high */
-               if (val)
-                       return gpiod_direction_input(desc);
-       }
-       else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
-               ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
-                                                 PIN_CONFIG_DRIVE_OPEN_SOURCE);
-               if (!ret)
-                       goto set_output_value;
-               /* Emulate open source by not actively driving the line low */
-               if (!val)
-                       return gpiod_direction_input(desc);
-       } else {
-               gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
-                                           PIN_CONFIG_DRIVE_PUSH_PULL);
-       }
- set_output_value:
        if (!gc->set || !gc->direction_output) {
                gpiod_warn(desc,
                       "%s: missing set() or direction_output() operations\n",
  int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
  {
        VALIDATE_DESC(desc);
-       return _gpiod_direction_output_raw(desc, value);
+       return gpiod_direction_output_raw_commit(desc, value);
  }
  EXPORT_SYMBOL_GPL(gpiod_direction_output_raw);
  
   */
  int gpiod_direction_output(struct gpio_desc *desc, int value)
  {
+       struct gpio_chip *gc = desc->gdev->chip;
+       int ret;
        VALIDATE_DESC(desc);
        if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
                value = !value;
        else
                value = !!value;
-       return _gpiod_direction_output_raw(desc, value);
+       /* GPIOs used for IRQs shall not be set as output */
+       if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
+               gpiod_err(desc,
+                         "%s: tried to set a GPIO tied to an IRQ as output\n",
+                         __func__);
+               return -EIO;
+       }
+       if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
+               /* First see if we can enable open drain in hardware */
+               ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
+                                                 PIN_CONFIG_DRIVE_OPEN_DRAIN);
+               if (!ret)
+                       goto set_output_value;
+               /* Emulate open drain by not actively driving the line high */
+               if (value)
+                       return gpiod_direction_input(desc);
+       }
+       else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
+               ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
+                                                 PIN_CONFIG_DRIVE_OPEN_SOURCE);
+               if (!ret)
+                       goto set_output_value;
+               /* Emulate open source by not actively driving the line low */
+               if (!value)
+                       return gpiod_direction_input(desc);
+       } else {
+               gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
+                                           PIN_CONFIG_DRIVE_PUSH_PULL);
+       }
+ set_output_value:
+       return gpiod_direction_output_raw_commit(desc, value);
  }
  EXPORT_SYMBOL_GPL(gpiod_direction_output);
  
@@@ -2448,7 -2555,7 +2555,7 @@@ EXPORT_SYMBOL_GPL(gpiod_is_active_low)
   * that the GPIO was actually requested.
   */
  
- static int _gpiod_get_raw_value(const struct gpio_desc *desc)
+ static int gpiod_get_raw_value_commit(const struct gpio_desc *desc)
  {
        struct gpio_chip        *chip;
        int offset;
        return value;
  }
  
+ static int gpio_chip_get_multiple(struct gpio_chip *chip,
+                                 unsigned long *mask, unsigned long *bits)
+ {
+       if (chip->get_multiple) {
+               return chip->get_multiple(chip, mask, bits);
+       } else if (chip->get) {
+               int i, value;
+               for_each_set_bit(i, mask, chip->ngpio) {
+                       value = chip->get(chip, i);
+                       if (value < 0)
+                               return value;
+                       __assign_bit(i, bits, value);
+               }
+               return 0;
+       }
+       return -EIO;
+ }
+ int gpiod_get_array_value_complex(bool raw, bool can_sleep,
+                                 unsigned int array_size,
+                                 struct gpio_desc **desc_array,
+                                 int *value_array)
+ {
+       int i = 0;
+       while (i < array_size) {
+               struct gpio_chip *chip = desc_array[i]->gdev->chip;
+               unsigned long mask[BITS_TO_LONGS(chip->ngpio)];
+               unsigned long bits[BITS_TO_LONGS(chip->ngpio)];
+               int first, j, ret;
+               if (!can_sleep)
+                       WARN_ON(chip->can_sleep);
+               /* collect all inputs belonging to the same chip */
+               first = i;
+               memset(mask, 0, sizeof(mask));
+               do {
+                       const struct gpio_desc *desc = desc_array[i];
+                       int hwgpio = gpio_chip_hwgpio(desc);
+                       __set_bit(hwgpio, mask);
+                       i++;
+               } while ((i < array_size) &&
+                        (desc_array[i]->gdev->chip == chip));
+               ret = gpio_chip_get_multiple(chip, mask, bits);
+               if (ret)
+                       return ret;
+               for (j = first; j < i; j++) {
+                       const struct gpio_desc *desc = desc_array[j];
+                       int hwgpio = gpio_chip_hwgpio(desc);
+                       int value = test_bit(hwgpio, bits);
+                       if (!raw && test_bit(FLAG_ACTIVE_LOW, &desc->flags))
+                               value = !value;
+                       value_array[j] = value;
+                       trace_gpio_value(desc_to_gpio(desc), 1, value);
+               }
+       }
+       return 0;
+ }
  /**
   * gpiod_get_raw_value() - return a gpio's raw value
   * @desc: gpio whose value will be returned
@@@ -2477,7 -2649,7 +2649,7 @@@ int gpiod_get_raw_value(const struct gp
        VALIDATE_DESC(desc);
        /* Should be using gpio_get_value_cansleep() */
        WARN_ON(desc->gdev->chip->can_sleep);
-       return _gpiod_get_raw_value(desc);
+       return gpiod_get_raw_value_commit(desc);
  }
  EXPORT_SYMBOL_GPL(gpiod_get_raw_value);
  
@@@ -2499,7 -2671,7 +2671,7 @@@ int gpiod_get_value(const struct gpio_d
        /* Should be using gpio_get_value_cansleep() */
        WARN_ON(desc->gdev->chip->can_sleep);
  
-       value = _gpiod_get_raw_value(desc);
+       value = gpiod_get_raw_value_commit(desc);
        if (value < 0)
                return value;
  
  }
  EXPORT_SYMBOL_GPL(gpiod_get_value);
  
+ /**
+  * gpiod_get_raw_array_value() - read raw values from an array of GPIOs
+  * @array_size: number of elements in the descriptor / value arrays
+  * @desc_array: array of GPIO descriptors whose values will be read
+  * @value_array: array to store the read values
+  *
+  * Read the raw values of the GPIOs, i.e. the values of the physical lines
+  * without regard for their ACTIVE_LOW status.  Return 0 in case of success,
+  * else an error code.
+  *
+  * This function should be called from contexts where we cannot sleep,
+  * and it will complain if the GPIO chip functions potentially sleep.
+  */
+ int gpiod_get_raw_array_value(unsigned int array_size,
+                             struct gpio_desc **desc_array, int *value_array)
+ {
+       if (!desc_array)
+               return -EINVAL;
+       return gpiod_get_array_value_complex(true, false, array_size,
+                                            desc_array, value_array);
+ }
+ EXPORT_SYMBOL_GPL(gpiod_get_raw_array_value);
+ /**
+  * gpiod_get_array_value() - read values from an array of GPIOs
+  * @array_size: number of elements in the descriptor / value arrays
+  * @desc_array: array of GPIO descriptors whose values will be read
+  * @value_array: array to store the read values
+  *
+  * Read the logical values of the GPIOs, i.e. taking their ACTIVE_LOW status
+  * into account.  Return 0 in case of success, else an error code.
+  *
+  * This function should be called from contexts where we cannot sleep,
+  * and it will complain if the GPIO chip functions potentially sleep.
+  */
+ int gpiod_get_array_value(unsigned int array_size,
+                         struct gpio_desc **desc_array, int *value_array)
+ {
+       if (!desc_array)
+               return -EINVAL;
+       return gpiod_get_array_value_complex(false, false, array_size,
+                                            desc_array, value_array);
+ }
+ EXPORT_SYMBOL_GPL(gpiod_get_array_value);
  /*
-  *  _gpio_set_open_drain_value() - Set the open drain gpio's value.
+  *  gpio_set_open_drain_value_commit() - Set the open drain gpio's value.
   * @desc: gpio descriptor whose state need to be set.
   * @value: Non-zero for setting it HIGH otherwise it will set to LOW.
   */
- static void _gpio_set_open_drain_value(struct gpio_desc *desc, bool value)
+ static void gpio_set_open_drain_value_commit(struct gpio_desc *desc, bool value)
  {
        int err = 0;
        struct gpio_chip *chip = desc->gdev->chip;
   * @desc: gpio descriptor whose state need to be set.
   * @value: Non-zero for setting it HIGH otherwise it will set to LOW.
   */
- static void _gpio_set_open_source_value(struct gpio_desc *desc, bool value)
+ static void gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value)
  {
        int err = 0;
        struct gpio_chip *chip = desc->gdev->chip;
                          __func__, err);
  }
  
- static void _gpiod_set_raw_value(struct gpio_desc *desc, bool value)
+ static void gpiod_set_raw_value_commit(struct gpio_desc *desc, bool value)
  {
        struct gpio_chip        *chip;
  
        chip = desc->gdev->chip;
        trace_gpio_value(desc_to_gpio(desc), 0, value);
-       if (test_bit(FLAG_OPEN_DRAIN, &desc->flags))
-               _gpio_set_open_drain_value(desc, value);
-       else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags))
-               _gpio_set_open_source_value(desc, value);
-       else
-               chip->set(chip, gpio_chip_hwgpio(desc), value);
+       chip->set(chip, gpio_chip_hwgpio(desc), value);
  }
  
  /*
@@@ -2630,10 -2842,10 +2842,10 @@@ void gpiod_set_array_value_complex(boo
                         * collect all normal outputs belonging to the same chip
                         * open drain and open source outputs are set individually
                         */
-                       if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
-                               _gpio_set_open_drain_value(desc, value);
-                       } else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
-                               _gpio_set_open_source_value(desc, value);
+                       if (test_bit(FLAG_OPEN_DRAIN, &desc->flags) && !raw) {
+                               gpio_set_open_drain_value_commit(desc, value);
+                       } else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags) && !raw) {
+                               gpio_set_open_source_value_commit(desc, value);
                        } else {
                                __set_bit(hwgpio, mask);
                                if (value)
@@@ -2667,7 -2879,7 +2879,7 @@@ void gpiod_set_raw_value(struct gpio_de
        VALIDATE_DESC_VOID(desc);
        /* Should be using gpiod_set_value_cansleep() */
        WARN_ON(desc->gdev->chip->can_sleep);
-       _gpiod_set_raw_value(desc, value);
+       gpiod_set_raw_value_commit(desc, value);
  }
  EXPORT_SYMBOL_GPL(gpiod_set_raw_value);
  
   * @desc: gpio whose value will be assigned
   * @value: value to assign
   *
-  * Set the logical value of the GPIO, i.e. taking its ACTIVE_LOW status into
-  * account
+  * Set the logical value of the GPIO, i.e. taking its ACTIVE_LOW,
+  * OPEN_DRAIN and OPEN_SOURCE flags into account.
   *
   * This function should be called from contexts where we cannot sleep, and will
   * complain if the GPIO chip functions potentially sleep.
@@@ -2689,7 -2901,12 +2901,12 @@@ void gpiod_set_value(struct gpio_desc *
        WARN_ON(desc->gdev->chip->can_sleep);
        if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
                value = !value;
-       _gpiod_set_raw_value(desc, value);
+       if (test_bit(FLAG_OPEN_DRAIN, &desc->flags))
+               gpio_set_open_drain_value_commit(desc, value);
+       else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags))
+               gpio_set_open_source_value_commit(desc, value);
+       else
+               gpiod_set_raw_value_commit(desc, value);
  }
  EXPORT_SYMBOL_GPL(gpiod_set_value);
  
@@@ -2890,7 -3107,7 +3107,7 @@@ bool gpiochip_line_is_persistent(struc
        if (offset >= chip->ngpio)
                return false;
  
-       return !test_bit(FLAG_SLEEP_MAY_LOOSE_VALUE,
+       return !test_bit(FLAG_SLEEP_MAY_LOSE_VALUE,
                         &chip->gpiodev->descs[offset].flags);
  }
  EXPORT_SYMBOL_GPL(gpiochip_line_is_persistent);
@@@ -2908,7 -3125,7 +3125,7 @@@ int gpiod_get_raw_value_cansleep(const 
  {
        might_sleep_if(extra_checks);
        VALIDATE_DESC(desc);
-       return _gpiod_get_raw_value(desc);
+       return gpiod_get_raw_value_commit(desc);
  }
  EXPORT_SYMBOL_GPL(gpiod_get_raw_value_cansleep);
  
@@@ -2927,7 -3144,7 +3144,7 @@@ int gpiod_get_value_cansleep(const stru
  
        might_sleep_if(extra_checks);
        VALIDATE_DESC(desc);
-       value = _gpiod_get_raw_value(desc);
+       value = gpiod_get_raw_value_commit(desc);
        if (value < 0)
                return value;
  
  }
  EXPORT_SYMBOL_GPL(gpiod_get_value_cansleep);
  
+ /**
+  * gpiod_get_raw_array_value_cansleep() - read raw values from an array of GPIOs
+  * @array_size: number of elements in the descriptor / value arrays
+  * @desc_array: array of GPIO descriptors whose values will be read
+  * @value_array: array to store the read values
+  *
+  * Read the raw values of the GPIOs, i.e. the values of the physical lines
+  * without regard for their ACTIVE_LOW status.  Return 0 in case of success,
+  * else an error code.
+  *
+  * This function is to be called from contexts that can sleep.
+  */
+ int gpiod_get_raw_array_value_cansleep(unsigned int array_size,
+                                      struct gpio_desc **desc_array,
+                                      int *value_array)
+ {
+       might_sleep_if(extra_checks);
+       if (!desc_array)
+               return -EINVAL;
+       return gpiod_get_array_value_complex(true, true, array_size,
+                                            desc_array, value_array);
+ }
+ EXPORT_SYMBOL_GPL(gpiod_get_raw_array_value_cansleep);
+ /**
+  * gpiod_get_array_value_cansleep() - read values from an array of GPIOs
+  * @array_size: number of elements in the descriptor / value arrays
+  * @desc_array: array of GPIO descriptors whose values will be read
+  * @value_array: array to store the read values
+  *
+  * Read the logical values of the GPIOs, i.e. taking their ACTIVE_LOW status
+  * into account.  Return 0 in case of success, else an error code.
+  *
+  * This function is to be called from contexts that can sleep.
+  */
+ int gpiod_get_array_value_cansleep(unsigned int array_size,
+                                  struct gpio_desc **desc_array,
+                                  int *value_array)
+ {
+       might_sleep_if(extra_checks);
+       if (!desc_array)
+               return -EINVAL;
+       return gpiod_get_array_value_complex(false, true, array_size,
+                                            desc_array, value_array);
+ }
+ EXPORT_SYMBOL_GPL(gpiod_get_array_value_cansleep);
  /**
   * gpiod_set_raw_value_cansleep() - assign a gpio's raw value
   * @desc: gpio whose value will be assigned
@@@ -2952,7 -3216,7 +3216,7 @@@ void gpiod_set_raw_value_cansleep(struc
  {
        might_sleep_if(extra_checks);
        VALIDATE_DESC_VOID(desc);
-       _gpiod_set_raw_value(desc, value);
+       gpiod_set_raw_value_commit(desc, value);
  }
  EXPORT_SYMBOL_GPL(gpiod_set_raw_value_cansleep);
  
@@@ -2972,7 -3236,7 +3236,7 @@@ void gpiod_set_value_cansleep(struct gp
        VALIDATE_DESC_VOID(desc);
        if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
                value = !value;
-       _gpiod_set_raw_value(desc, value);
+       gpiod_set_raw_value_commit(desc, value);
  }
  EXPORT_SYMBOL_GPL(gpiod_set_value_cansleep);
  
@@@ -3268,8 -3532,8 +3532,8 @@@ int gpiod_configure_flags(struct gpio_d
                set_bit(FLAG_OPEN_DRAIN, &desc->flags);
        if (lflags & GPIO_OPEN_SOURCE)
                set_bit(FLAG_OPEN_SOURCE, &desc->flags);
-       if (lflags & GPIO_SLEEP_MAY_LOOSE_VALUE)
-               set_bit(FLAG_SLEEP_MAY_LOOSE_VALUE, &desc->flags);
+       if (lflags & GPIO_SLEEP_MAY_LOSE_VALUE)
+               set_bit(FLAG_SLEEP_MAY_LOSE_VALUE, &desc->flags);
  
        /* No particular flag request, return here... */
        if (!(dflags & GPIOD_FLAGS_BIT_DIR_SET)) {
index 5d08d989b1d06bd2083c01c115a78bd517a45135,b93f62dc87333f242489e591cb721eac7fe8a011..b70058caee5049845633717ba6d54fdb892ef56b
@@@ -172,7 -172,7 +172,7 @@@ static void iproc_gpio_irq_handler(stru
  
                for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
                        unsigned pin = NGPIOS_PER_BANK * i + bit;
-                       int child_irq = irq_find_mapping(gc->irqdomain, pin);
+                       int child_irq = irq_find_mapping(gc->irq.domain, pin);
  
                        /*
                         * Clear the interrupt before invoking the
@@@ -311,7 -311,7 +311,7 @@@ static int iproc_gpio_request(struct gp
        if (!chip->pinmux_is_supported)
                return 0;
  
 -      return pinctrl_request_gpio(gpio);
 +      return pinctrl_gpio_request(gpio);
  }
  
  static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
        if (!chip->pinmux_is_supported)
                return;
  
 -      pinctrl_free_gpio(gpio);
 +      pinctrl_gpio_free(gpio);
  }
  
  static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
index 8d50eaec95777e7693e383525bbd47042e7ecaab,e23def322de2d51f3200705a62558fd89a1dd6ac..d6bdf61eeed84ead94e4985d5845581e8ac282c8
@@@ -491,7 -491,7 +491,7 @@@ static const struct chv_community north
        .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
        .ngpios = ARRAY_SIZE(north_pins),
        /*
 -       * North community can benerate GPIO interrupts only for the first
 +       * North community can generate GPIO interrupts only for the first
         * 8 interrupts. The upper half (8-15) can only be used to trigger
         * GPEs.
         */
@@@ -1523,7 -1523,7 +1523,7 @@@ static void chv_gpio_irq_handler(struc
                unsigned irq, offset;
  
                offset = pctrl->intr_lines[intr_line];
-               irq = irq_find_mapping(gc->irqdomain, offset);
+               irq = irq_find_mapping(gc->irq.domain, offset);
                generic_handle_irq(irq);
        }
  
@@@ -1584,7 -1584,7 +1584,7 @@@ static int chv_gpio_probe(struct chv_pi
        chip->label = dev_name(pctrl->dev);
        chip->parent = pctrl->dev;
        chip->base = -1;
-       chip->irq_need_valid_mask = need_valid_mask;
+       chip->irq.need_valid_mask = need_valid_mask;
  
        ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
        if (ret) {
                intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
  
                if (need_valid_mask && intsel >= pctrl->community->nirqs)
-                       clear_bit(i, chip->irq_valid_mask);
+                       clear_bit(i, chip->irq.valid_mask);
        }
  
        /* Clear all interrupts */
index 3761fd29100f771f724c8e0927e6beb9ad510e10,ffda27bfd133c79fcf0f0d25ab8af46a00336032..12a1af45acb98557de6184e934360dc056fbc01a
@@@ -30,6 -30,8 +30,6 @@@
  
  #define PADBAR                                0x00c
  #define GPI_IS                                0x100
 -#define GPI_GPE_STS                   0x140
 -#define GPI_GPE_EN                    0x160
  
  #define PADOWN_BITS                   4
  #define PADOWN_SHIFT(p)                       ((p) % 8 * PADOWN_BITS)
@@@ -816,7 -818,7 +816,7 @@@ static void intel_gpio_irq_ack(struct i
        community = intel_get_community(pctrl, pin);
        if (community) {
                const struct intel_padgroup *padgrp;
 -              unsigned gpp, gpp_offset;
 +              unsigned gpp, gpp_offset, is_offset;
  
                padgrp = intel_community_get_padgroup(community, pin);
                if (!padgrp)
  
                gpp = padgrp->reg_num;
                gpp_offset = padgroup_offset(padgrp, pin);
 +              is_offset = community->is_offset + gpp * 4;
  
                raw_spin_lock(&pctrl->lock);
 -              writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 +              writel(BIT(gpp_offset), community->regs + is_offset);
                raw_spin_unlock(&pctrl->lock);
        }
  }
@@@ -842,7 -843,7 +842,7 @@@ static void intel_gpio_irq_enable(struc
        community = intel_get_community(pctrl, pin);
        if (community) {
                const struct intel_padgroup *padgrp;
 -              unsigned gpp, gpp_offset;
 +              unsigned gpp, gpp_offset, is_offset;
                unsigned long flags;
                u32 value;
  
  
                gpp = padgrp->reg_num;
                gpp_offset = padgroup_offset(padgrp, pin);
 +              is_offset = community->is_offset + gpp * 4;
  
                raw_spin_lock_irqsave(&pctrl->lock, flags);
                /* Clear interrupt status first to avoid unexpected interrupt */
 -              writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 +              writel(BIT(gpp_offset), community->regs + is_offset);
  
                value = readl(community->regs + community->ie_offset + gpp * 4);
                value |= BIT(gpp_offset);
@@@ -991,8 -991,7 +991,8 @@@ static irqreturn_t intel_gpio_community
                const struct intel_padgroup *padgrp = &community->gpps[gpp];
                unsigned long pending, enabled, gpp_offset;
  
 -              pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4);
 +              pending = readl(community->regs + community->is_offset +
 +                              padgrp->reg_num * 4);
                enabled = readl(community->regs + community->ie_offset +
                                padgrp->reg_num * 4);
  
                        if (padno >= community->npins)
                                break;
  
-                       irq = irq_find_mapping(gc->irqdomain,
+                       irq = irq_find_mapping(gc->irq.domain,
                                               community->pin_base + padno);
                        generic_handle_irq(irq);
  
@@@ -1242,9 -1241,6 +1242,9 @@@ int intel_pinctrl_probe(struct platform
                community->regs = regs;
                community->pad_regs = regs + padbar;
  
 +              if (!community->is_offset)
 +                      community->is_offset = GPI_IS;
 +
                ret = intel_pinctrl_add_padgroups(pctrl, community);
                if (ret)
                        return ret;
@@@ -1360,7 -1356,7 +1360,7 @@@ static void intel_gpio_irq_init(struct 
                for (gpp = 0; gpp < community->ngpps; gpp++) {
                        /* Mask and clear all interrupts */
                        writel(0, base + community->ie_offset + gpp * 4);
 -                      writel(0xffff, base + GPI_IS + gpp * 4);
 +                      writel(0xffff, base + community->is_offset + gpp * 4);
                }
        }
  }
index 4e8d836a8c6f6567d99cec078005be6c83b3a43a,d754a9b10e19de2b82e8cce78117e19d88827c95..d45af31b86b41ef6c85591a040fe2dd46c60de3e
@@@ -576,19 -576,6 +576,19 @@@ static int armada_37xx_irq_set_type(str
        case IRQ_TYPE_EDGE_FALLING:
                val |= (BIT(d->hwirq % GPIO_PER_REG));
                break;
 +      case IRQ_TYPE_EDGE_BOTH: {
 +              u32 in_val, in_reg = INPUT_VAL;
 +
 +              armada_37xx_irq_update_reg(&in_reg, d);
 +              regmap_read(info->regmap, in_reg, &in_val);
 +
 +              /* Set initial polarity based on current input level. */
 +              if (in_val & d->mask)
 +                      val |= d->mask;         /* falling */
 +              else
 +                      val &= ~d->mask;        /* rising */
 +              break;
 +      }
        default:
                spin_unlock_irqrestore(&info->irq_lock, flags);
                return -EINVAL;
        return 0;
  }
  
 +static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
 +                                           u32 pin_idx)
 +{
 +      u32 reg_idx = pin_idx / GPIO_PER_REG;
 +      u32 bit_num = pin_idx % GPIO_PER_REG;
 +      u32 p, l, ret;
 +      unsigned long flags;
 +
 +      regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
 +
 +      spin_lock_irqsave(&info->irq_lock, flags);
 +      p = readl(info->base + IRQ_POL + 4 * reg_idx);
 +      if ((p ^ l) & (1 << bit_num)) {
 +              /*
 +               * For the gpios which are used for both-edge irqs, when their
 +               * interrupts happen, their input levels are changed,
 +               * yet their interrupt polarities are kept in old values, we
 +               * should synchronize their interrupt polarities; for example,
 +               * at first a gpio's input level is low and its interrupt
 +               * polarity control is "Detect rising edge", then the gpio has
 +               * a interrupt , its level turns to high, we should change its
 +               * polarity control to "Detect falling edge" correspondingly.
 +               */
 +              p ^= 1 << bit_num;
 +              writel(p, info->base + IRQ_POL + 4 * reg_idx);
 +              ret = 0;
 +      } else {
 +              /* Spurious irq */
 +              ret = -1;
 +      }
 +
 +      spin_unlock_irqrestore(&info->irq_lock, flags);
 +      return ret;
 +}
  
  static void armada_37xx_irq_handler(struct irq_desc *desc)
  {
        struct gpio_chip *gc = irq_desc_get_handler_data(desc);
        struct irq_chip *chip = irq_desc_get_chip(desc);
        struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
-       struct irq_domain *d = gc->irqdomain;
+       struct irq_domain *d = gc->irq.domain;
        int i;
  
        chained_irq_enter(chip, desc);
                        u32 hwirq = ffs(status) - 1;
                        u32 virq = irq_find_mapping(d, hwirq +
                                                     i * GPIO_PER_REG);
 +                      u32 t = irq_get_trigger_type(virq);
 +
 +                      if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 +                              /* Swap polarity (race with GPIO line) */
 +                              if (armada_37xx_edge_both_irq_swap_pol(info,
 +                                      hwirq + i * GPIO_PER_REG)) {
 +                                      /*
 +                                       * For spurious irq, which gpio level
 +                                       * is not as expected after incoming
 +                                       * edge, just ack the gpio irq.
 +                                       */
 +                                      writel(1 << hwirq,
 +                                             info->base +
 +                                             IRQ_STATUS + 4 * i);
 +                                      continue;
 +                              }
 +                      }
  
                        generic_handle_irq(virq);
  
  
  static unsigned int armada_37xx_irq_startup(struct irq_data *d)
  {
-       struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
-       int irq = d->hwirq - chip->irq_base;
        /*
         * The mask field is a "precomputed bitmask for accessing the
         * chip registers" which was introduced for the generic
         * irqchip framework. As we don't use this framework, we can
         * reuse this field for our own usage.
         */
-       d->mask = BIT(irq % GPIO_PER_REG);
+       d->mask = BIT(d->hwirq % GPIO_PER_REG);
  
        armada_37xx_irq_unmask(d);
  
index d10d280ab1c902d6c05bee1d0e0683e440515fbe,06362bf84a5bf23b549052f1f961e79423e3e727..b9c0dd75319e22db0e3f85c41d1803d81391b916
@@@ -532,7 -532,7 +532,7 @@@ static irqreturn_t amd_gpio_irq_handler
                        regval = readl(regs + i);
                        if (!(regval & PIN_IRQ_PENDING))
                                continue;
-                       irq = irq_find_mapping(gc->irqdomain, irqnr + i);
+                       irq = irq_find_mapping(gc->irq.domain, irqnr + i);
                        generic_handle_irq(irq);
                        /* Clear interrupt */
                        writel(regval, regs + i);
@@@ -745,7 -745,7 +745,7 @@@ static bool amd_gpio_should_save(struc
        return false;
  }
  
 -int amd_gpio_suspend(struct device *dev)
 +static int amd_gpio_suspend(struct device *dev)
  {
        struct platform_device *pdev = to_platform_device(dev);
        struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
        return 0;
  }
  
 -int amd_gpio_resume(struct device *dev)
 +static int amd_gpio_resume(struct device *dev)
  {
        struct platform_device *pdev = to_platform_device(dev);
        struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
index a7602be296a21efea09586a559bdbbb296f5373e,db19a2f2f57576f06a5a7182d95a8b4d8f189a9b..0aef30ead5dcfa8214e32bd50f9eedc8aec0816e
@@@ -25,7 -25,6 +25,7 @@@
  #define MCP_TYPE_008  2
  #define MCP_TYPE_017  3
  #define MCP_TYPE_S18    4
 +#define MCP_TYPE_018    5
  
  #define MCP_MAX_DEV_PER_CS    8
  
@@@ -279,7 -278,8 +279,7 @@@ static int mcp_pinconf_set(struct pinct
  {
        struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
        enum pin_config_param param;
 -      u32 arg, mask;
 -      u16 val;
 +      u32 arg;
        int ret = 0;
        int i;
  
  
                switch (param) {
                case PIN_CONFIG_BIAS_PULL_UP:
 -                      val = arg ? 0xFFFF : 0x0000;
 -                      mask = BIT(pin);
                        ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
                        break;
                default:
@@@ -535,7 -537,7 +535,7 @@@ static irqreturn_t mcp23s08_irq(int irq
                    ((gpio_bit_changed || intcap_changed) &&
                        (BIT(i) & mcp->irq_fall) && !gpio_set) ||
                    defval_changed) {
-                       child_irq = irq_find_mapping(mcp->chip.irqdomain, i);
+                       child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
                        handle_nested_irq(child_irq);
                }
        }
@@@ -835,13 -837,6 +835,13 @@@ static int mcp23s08_probe_one(struct mc
                mcp->chip.ngpio = 16;
                mcp->chip.label = "mcp23017";
                break;
 +
 +      case MCP_TYPE_018:
 +              mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap);
 +              mcp->reg_shift = 1;
 +              mcp->chip.ngpio = 16;
 +              mcp->chip.label = "mcp23018";
 +              break;
  #endif /* CONFIG_I2C */
  
        default:
                if (mirror)
                        status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
  
 -              if (type == MCP_TYPE_S18)
 +              if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
                        status |= IOCON_INTCC | (IOCON_INTCC << 8);
  
                ret = mcp_write(mcp, MCP_IOCON, status);
@@@ -969,10 -964,6 +969,10 @@@ static const struct of_device_id mcp23s
                .compatible = "microchip,mcp23017",
                .data = (void *) MCP_TYPE_017,
        },
 +      {
 +              .compatible = "microchip,mcp23018",
 +              .data = (void *) MCP_TYPE_018,
 +      },
  /* NOTE: The use of the mcp prefix is deprecated and will be removed. */
        {
                .compatible = "mcp,mcp23008",
@@@ -1022,7 -1013,6 +1022,7 @@@ static int mcp230xx_probe(struct i2c_cl
  static const struct i2c_device_id mcp230xx_id[] = {
        { "mcp23008", MCP_TYPE_008 },
        { "mcp23017", MCP_TYPE_017 },
 +      { "mcp23018", MCP_TYPE_018 },
        { },
  };
  MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
index c5ab8cef942d68dc99249db9e29d28d7c84eaffc,7db4f6a6eb171f833653dd1735f01973840418fe..fb242c542dc926c9392d31b99f937c17215cec81
@@@ -561,7 -561,7 +561,7 @@@ static irqreturn_t sx150x_irq_thread_fn
  
        status = val;
        for_each_set_bit(n, &status, pctl->data->ngpios)
-               handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n));
+               handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
  
        return IRQ_HANDLED;
  }
@@@ -1087,7 -1087,7 +1087,7 @@@ static bool sx150x_reg_volatile(struct 
        return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
  }
  
 -const struct regmap_config sx150x_regmap_config = {
 +static const struct regmap_config sx150x_regmap_config = {
        .reg_bits = 8,
        .val_bits = 32,
  
index f4b192b493a0798aa94b2a2e7dbcb6642a58f884,f5cef6e5fa3e29f8fc909253372200a0d6c66a80..3abb028f615861a938b385d117236c8240dda439
@@@ -5820,7 -5820,7 +5820,7 @@@ static void atlas7_gpio_handle_irq(stru
                                __func__, gc->label,
                                bank->gpio_offset + pin_in_bank);
                        generic_handle_irq(
-                               irq_find_mapping(gc->irqdomain,
+                               irq_find_mapping(gc->irq.domain,
                                        bank->gpio_offset + pin_in_bank));
                }
  
@@@ -5860,7 -5860,7 +5860,7 @@@ static int atlas7_gpio_request(struct g
        if (ret < 0)
                return ret;
  
 -      if (pinctrl_request_gpio(chip->base + gpio))
 +      if (pinctrl_gpio_request(chip->base + gpio))
                return -ENODEV;
  
        raw_spin_lock_irqsave(&a7gc->lock, flags);
@@@ -5890,7 -5890,7 +5890,7 @@@ static void atlas7_gpio_free(struct gpi
  
        raw_spin_unlock_irqrestore(&a7gc->lock, flags);
  
 -      pinctrl_free_gpio(chip->base + gpio);
 +      pinctrl_gpio_free(chip->base + gpio);
  }
  
  static int atlas7_gpio_direction_input(struct gpio_chip *chip,
index d64add0b84cc01f37bd172558472ac4313744c32,8b14a1f1e67159bc577c06e17246742947e7b83c..ca2347d0d57946574840ee778f2f4124b388c328
@@@ -587,7 -587,7 +587,7 @@@ static void sirfsoc_gpio_handle_irq(str
                if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
                        pr_debug("%s: gpio id %d idx %d happens\n",
                                __func__, bank->id, idx);
-                       generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
+                       generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
                                        bank->id * SIRFSOC_GPIO_BANK_SIZE));
                }
  
@@@ -614,7 -614,7 +614,7 @@@ static int sirfsoc_gpio_request(struct 
        struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
        unsigned long flags;
  
 -      if (pinctrl_request_gpio(chip->base + offset))
 +      if (pinctrl_gpio_request(chip->base + offset))
                return -ENODEV;
  
        spin_lock_irqsave(&bank->lock, flags);
@@@ -644,7 -644,7 +644,7 @@@ static void sirfsoc_gpio_free(struct gp
  
        spin_unlock_irqrestore(&bank->lock, flags);
  
 -      pinctrl_free_gpio(chip->base + offset);
 +      pinctrl_gpio_free(chip->base + offset);
  }
  
  static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
index 7a33e2e1e3e752b6bead3361c2de31a3c0221364,72ae6bccee55f2522d02d582434767a78264e0c7..6a0ed8ab33b989069959191b5f5f59fd84ccde0f
@@@ -204,7 -204,7 +204,7 @@@ static int plgpio_request(struct gpio_c
        if (offset >= chip->ngpio)
                return -EINVAL;
  
 -      ret = pinctrl_request_gpio(gpio);
 +      ret = pinctrl_gpio_request(gpio);
        if (ret)
                return ret;
  
@@@ -242,7 -242,7 +242,7 @@@ err1
        if (!IS_ERR(plgpio->clk))
                clk_disable(plgpio->clk);
  err0:
 -      pinctrl_free_gpio(gpio);
 +      pinctrl_gpio_free(gpio);
        return ret;
  }
  
@@@ -273,7 -273,7 +273,7 @@@ disable_clk
        if (!IS_ERR(plgpio->clk))
                clk_disable(plgpio->clk);
  
 -      pinctrl_free_gpio(gpio);
 +      pinctrl_gpio_free(gpio);
  }
  
  /* PLGPIO IRQ */
@@@ -401,7 -401,7 +401,7 @@@ static void plgpio_irq_handler(struct i
                        /* get correct irq line number */
                        pin = i * MAX_GPIO_PER_REG + pin;
                        generic_handle_irq(
-                               irq_find_mapping(gc->irqdomain, pin));
+                               irq_find_mapping(gc->irq.domain, pin));
                }
        }
        chained_irq_exit(irqchip, desc);
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