iommu/arm-smmu: Log CBFRSYNRA register on context fault

Bits[15:0] in CBFRSYNRA register contain information about
StreamID of the incoming transaction that generated the
fault. Dump CBFRSYNRA register to get this info.
This is specially useful in a distributed SMMU architecture
where multiple masters are connected to the SMMU.
SID information helps to quickly identify the faulting
master device.

Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Robin Murphy <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Vivek Gautam <[email protected]>
Signed-off-by: Will Deacon <[email protected]>

diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
index a1226e4ab5f89716ec50d8b8f64594ed3c36453f..e9132a926761dfb6a8a699eca1fafa6715f36824 100644 (file)
--- a/drivers/iommu/arm-smmu-regs.h
+++ b/drivers/iommu/arm-smmu-regs.h
@@ -147,6 +147,8 @@ enum arm_smmu_s2cr_privcfg {
 #define CBAR_IRPTNDX_SHIFT             24
 #define CBAR_IRPTNDX_MASK              0xff
 
 #define CBAR_IRPTNDX_SHIFT             24
 #define CBAR_IRPTNDX_MASK              0xff
 

+#define ARM_SMMU_GR1_CBFRSYNRA(n)      (0x400 + ((n) << 2))
+

 #define ARM_SMMU_GR1_CBA2R(n)          (0x800 + ((n) << 2))
 #define CBA2R_RW64_32BIT               (0 << 0)
 #define CBA2R_RW64_64BIT               (1 << 0)
 #define ARM_SMMU_GR1_CBA2R(n)          (0x800 + ((n) << 2))
 #define CBA2R_RW64_32BIT               (0 << 0)
 #define CBA2R_RW64_64BIT               (1 << 0)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 930c076359564ab6c2e1db2490095848fd7afdf6..5e54cc0a28b30516b65c2516c666ee3d9c398141 100644 (file)
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -570,12 +570,13 @@ static const struct iommu_gather_ops arm_smmu_s2_tlb_ops_v1 = {
 
 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 {
 
 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 {

-       u32 fsr, fsynr;
+       u32 fsr, fsynr, cbfrsynra;

        unsigned long iova;
        struct iommu_domain *domain = dev;
        struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
        struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
        struct arm_smmu_device *smmu = smmu_domain->smmu;
        unsigned long iova;
        struct iommu_domain *domain = dev;
        struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
        struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
        struct arm_smmu_device *smmu = smmu_domain->smmu;

+       void __iomem *gr1_base = ARM_SMMU_GR1(smmu);

        void __iomem *cb_base;
 
        cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
        void __iomem *cb_base;
 
        cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);


@@ -586,10 +587,11 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 
        fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
        iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
 
        fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
        iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);

+       cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));

 
        dev_err_ratelimited(smmu->dev,
 
        dev_err_ratelimited(smmu->dev,

-       "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
-                           fsr, iova, fsynr, cfg->cbndx);
+       "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
+                           fsr, iova, fsynr, cbfrsynra, cfg->cbndx);

 
        writel(fsr, cb_base + ARM_SMMU_CB_FSR);
        return IRQ_HANDLED;
 
        writel(fsr, cb_base + ARM_SMMU_CB_FSR);
        return IRQ_HANDLED;