Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 perf updates from Will Deacon:
 "The main addition here is support for Broadcom's Vulcan core using the
  architected ID registers for discovering supported events.

   - Support for the PMU in Broadcom's Vulcan CPU

   - Dynamic event detection using the PMCEIDn_EL0 ID registers"

* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: perf: don't expose CHAIN event in sysfs
  arm64/perf: Add Broadcom Vulcan PMU support
  arm64/perf: Filter common events based on PMCEIDn_EL0
  arm64/perf: Access pmu register using <read/write>_sys_reg
  arm64/perf: Define complete ARMv8 recommended implementation defined events
  arm64/perf: Changed events naming as per the ARM ARM
  arm64: dts: Add Broadcom Vulcan PMU in dts
  Documentation: arm64: pmu: Add Broadcom Vulcan PMU binding

diff --combined arch/arm64/boot/dts/broadcom/vulcan.dtsi
index 85820e2bca9df4ce72f63f69670d88586c23930a,03dd845394c028bc0770a0995f647689b32161bf..34e11a9db2a0d586123b05cd277f6a8760511f66
--- 1/arch/arm64/boot/dts/broadcom/vulcan.dtsi
--- 2/arch/arm64/boot/dts/broadcom/vulcan.dtsi
+++ b/arch/arm64/boot/dts/broadcom/vulcan.dtsi
@@@ -86,7 -86,7 +86,7 @@@
        };
  
        pmu {
-               compatible = "arm,armv8-pmuv3";
+               compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
        };
  
@@@ -108,15 -108,12 +108,15 @@@
                reg = <0x0 0x30000000  0x0 0x10000000>;
                reg-names = "PCI ECAM";
  
 -                        /* IO 0x4000_0000 - 0x4001_0000 */
 -              ranges = <0x01000000 0 0x40000000 0 0x40000000 0 0x00010000
 -                        /* MEM 0x4800_0000 - 0x5000_0000 */
 -                        0x02000000 0 0x48000000 0 0x48000000 0 0x08000000
 -                        /* MEM64 pref 0x6_0000_0000 - 0x7_0000_0000 */
 -                        0x43000000 6 0x00000000 6 0x00000000 1 0x00000000>;
 +              /*
 +               * PCI ranges:
 +               *   IO         no supported
 +               *   MEM        0x4000_0000 - 0x6000_0000
 +               *   MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
 +               */
 +              ranges =
 +                <0x02000000    0 0x40000000    0 0x40000000    0 0x20000000
 +                 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
                interrupt-map-mask = <0 0 0 7>;
                interrupt-map =
                      /* addr  pin  ic   icaddr  icintr */