Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integr...

Pull mailbox updates from Jassi Brar:

 - qcom:
     - enable support for ipq8074, sm1850 and sm7180
     - add child device node for qcs404
     - misc fixes

 - mediatek:
     - enable support for mt8183
     - misc rejig of cmdq driver
     - new client-reg dt property

 - armada:
     - use device-managed registration api

* tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: qcom-apcs: fix max_register value
  mailbox: qcom: Add support for IPQ8074 APCS
  dt-bindings: mailbox: qom: Add ipq8074 APPS compatible
  mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
  dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
  mbox: qcom: replace integer with valid macro
  mbox: qcom: add APCS child device for QCS404
  mailbox: mediatek: cmdq: clear the event in cmdq initial flow
  mailbox: mediatek: cmdq: support mt8183 gce function
  mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data
  dt-binding: gce: add binding for gce client reg property
  dt-binding: gce: add gce header file for mt8183
  dt-binding: gce: remove thread-num property
  mailbox: armada-37xx-rwtm: Use device-managed registration API

diff --combined include/linux/soc/mediatek/mtk-cmdq.h
index f3ae45d02e80143148853ac042b35aa4d167aa37,4e8899972db4ddfa89321205efe08e1880284c27..9618debb9cebbd0bd7849da5c6f0aa042442e13a
--- 1/include/linux/soc/mediatek/mtk-cmdq.h
--- 2/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@@ -13,9 -13,6 +13,6 @@@
  
  #define CMDQ_NO_TIMEOUT               0xffffffffu
  
- /** cmdq event maximum */
- #define CMDQ_MAX_EVENT                                0x3ff
- 
  struct cmdq_pkt;
  
  struct cmdq_client {
@@@ -63,26 -60,26 +60,26 @@@ void cmdq_pkt_destroy(struct cmdq_pkt *
  /**
   * cmdq_pkt_write() - append write command to the CMDQ packet
   * @pkt:      the CMDQ packet
 - * @value:    the specified target register value
   * @subsys:   the CMDQ sub system code
   * @offset:   register offset from CMDQ sub system
 + * @value:    the specified target register value
   *
   * Return: 0 for success; else the error code is returned
   */
 -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset);
 +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
  
  /**
   * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
   * @pkt:      the CMDQ packet
 - * @value:    the specified target register value
   * @subsys:   the CMDQ sub system code
   * @offset:   register offset from CMDQ sub system
 + * @value:    the specified target register value
   * @mask:     the specified target register mask
   *
   * Return: 0 for success; else the error code is returned
   */
 -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
 -                      u32 subsys, u32 offset, u32 mask);
 +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
 +                      u16 offset, u32 value, u32 mask);
  
  /**
   * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
@@@ -91,7 -88,7 +88,7 @@@
   *
   * Return: 0 for success; else the error code is returned
   */
 -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
 +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
  
  /**
   * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
@@@ -100,7 -97,7 +97,7 @@@
   *
   * Return: 0 for success; else the error code is returned
   */
 -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event);
 +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
  
  /**
   * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ