]> Git Repo - linux.git/commitdiff
Merge tag 'davinci-for-v4.11/soc-2' of git://git.kernel.org/pub/scm/linux/kernel...
authorArnd Bergmann <[email protected]>
Thu, 16 Feb 2017 16:15:39 +0000 (17:15 +0100)
committerArnd Bergmann <[email protected]>
Thu, 16 Feb 2017 16:15:39 +0000 (17:15 +0100)
Pull "SoC updates needed for SATA support on DA850" from Sekhar Nori:

This includes a merge of non-critical-fixes
branch already queued for v4.11 because
SATA clock addition conflicts with the fix-up
done earlier.

* tag 'davinci-for-v4.11/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: remove BUG_ON() from da850_register_sata()
  ARM: davinci: da850: model the SATA refclk
  ARM: davinci: da850: add con_id for the SATA clock
  ARM: davinci: da8xx-dt: add OF_DEV_AUXDATA entry for SATA
  ARM: davinci: add skeleton for pdata-quirks
  bus: da850-mstpri: fix my e-mail address
  ARM: davinci: da850: fix da850_set_pll0rate()
  ARM: davinci: da850: coding style fix

1  2 
arch/arm/mach-davinci/da850.c

index 1d873d15b545c26a97eefdf15d92d437ff2e1701,8ab3c099e9aab8337d6836618c3b1be07bf93586..d09765ba246b9083d528142bc37f6a79f051b6de
@@@ -319,16 -319,6 +319,16 @@@ static struct clk emac_clk = 
        .gpsc           = 1,
  };
  
 +/*
 + * In order to avoid adding the emac_clk to the clock lookup table twice (and
 + * screwing up the linked list in the process) create a separate clock for
 + * mdio inheriting the rate from emac_clk.
 + */
 +static struct clk mdio_clk = {
 +      .name           = "mdio",
 +      .parent         = &emac_clk,
 +};
 +
  static struct clk mcasp_clk = {
        .name           = "mcasp",
        .parent         = &async3_clk,
@@@ -377,16 -367,6 +377,16 @@@ static struct clk aemif_clk = 
        .flags          = ALWAYS_ENABLED,
  };
  
 +/*
 + * In order to avoid adding the aemif_clk to the clock lookup table twice (and
 + * screwing up the linked list in the process) create a separate clock for
 + * nand inheriting the rate from aemif_clk.
 + */
 +static struct clk aemif_nand_clk = {
 +      .name           = "nand",
 +      .parent         = &aemif_clk,
 +};
 +
  static struct clk usb11_clk = {
        .name           = "usb11",
        .parent         = &pll0_sysclk4,
@@@ -549,7 -529,7 +549,7 @@@ static struct clk_lookup da850_clks[] 
        CLK(NULL,               "arm",          &arm_clk),
        CLK(NULL,               "rmii",         &rmii_clk),
        CLK("davinci_emac.1",   NULL,           &emac_clk),
 -      CLK("davinci_mdio.0",   "fck",          &emac_clk),
 +      CLK("davinci_mdio.0",   "fck",          &mdio_clk),
        CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
        CLK("davinci-mcbsp.0",  NULL,           &mcbsp0_clk),
        CLK("davinci-mcbsp.1",  NULL,           &mcbsp1_clk),
        CLK("da830-mmc.0",      NULL,           &mmcsd0_clk),
        CLK("da830-mmc.1",      NULL,           &mmcsd1_clk),
        CLK("ti-aemif",         NULL,           &aemif_clk),
 -      CLK(NULL,               "aemif",        &aemif_clk),
 +      /*
 +       * The only user of this clock is davinci_nand and it get's it through
 +       * con_id. The nand node itself is created from within the aemif
 +       * driver to guarantee that it's probed after the aemif timing
 +       * parameters are configured. of_dev_auxdata is not accessible from
 +       * the aemif driver and can't be passed to of_platform_populate(). For
 +       * that reason we're leaving the dev_id here as NULL.
 +       */
 +      CLK(NULL,               "aemif",        &aemif_nand_clk),
        CLK("ohci-da8xx",       "usb11",        &usb11_clk),
        CLK("musb-da8xx",       "usb20",        &usb20_clk),
        CLK("spi_davinci.0",    NULL,           &spi0_clk),
        CLK("spi_davinci.1",    NULL,           &spi1_clk),
        CLK("vpif",             NULL,           &vpif_clk),
-       CLK("ahci_da850",               NULL,           &sata_clk),
+       CLK("ahci_da850",       "fck",          &sata_clk),
        CLK("davinci-rproc.0",  NULL,           &dsp_clk),
        CLK(NULL,               NULL,           &ehrpwm_clk),
        CLK("ehrpwm.0",         "fck",          &ehrpwm0_clk),
@@@ -1202,14 -1174,28 +1202,28 @@@ static int da850_set_armrate(struct cl
        return clk_set_rate(pllclk, index);
  }
  
- static int da850_set_pll0rate(struct clk *clk, unsigned long index)
+ static int da850_set_pll0rate(struct clk *clk, unsigned long rate)
  {
-       unsigned int prediv, mult, postdiv;
-       struct da850_opp *opp;
        struct pll_data *pll = clk->pll_data;
+       struct cpufreq_frequency_table *freq;
+       unsigned int prediv, mult, postdiv;
+       struct da850_opp *opp = NULL;
        int ret;
  
-       opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
+       rate /= 1000;
+       for (freq = da850_freq_table;
+            freq->frequency != CPUFREQ_TABLE_END; freq++) {
+               /* rate is in Hz, freq->frequency is in KHz */
+               if (freq->frequency == rate) {
+                       opp = (struct da850_opp *)freq->driver_data;
+                       break;
+               }
+       }
+       if (!opp)
+               return -EINVAL;
        prediv = opp->prediv;
        mult = opp->mult;
        postdiv = opp->postdiv;
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